Unroll 8 bits division inner loop (2 versions, 4 entry points for 4 quadrants)

diff --git a/sm.asm b/sm.asm
index 02f3b2b..8d6b692 100644 (file)
--- a/sm.asm
+++ b/sm.asm
@@ -1029,30 +1029,111 @@ divu:  ; positive dividend, positive divisor
 ; now optimized to only inc/dec a when doing zero-crossing, fix above analysis
 
 div:   jr      c,div1
-div0:  ld      b,8
+div0:  ; bit 0, above
        scf
        rla
-div00: adc     hl,hl
+       adc     hl,hl
        sbc     hl,de
        jr      nc,div01
        dec     a
-       jr      div11
-div01: add     a,a
-       djnz    div00
+div11: ; bit 1, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      nc,div12
+       inc     a
+div02: ; bit 2, above
+       add     a,a
+       adc     hl,hl
+       sbc     hl,de
+       jr      nc,div03
+       dec     a
+div13: ; bit 3, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      nc,div14
+       inc     a
+div04: ; bit 4, above
+       add     a,a
+       adc     hl,hl
+       sbc     hl,de
+       jr      nc,div05
+       dec     a
+div15: ; bit 5, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      nc,div16
+       inc     a
+div06: ; bit 6, above
+       add     a,a
+       adc     hl,hl
+       sbc     hl,de
+       jr      nc,div07
+       dec     a
+div17: ; bit 7, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      nc,div18
+       inc     a
+div08: ; done, above
+       add     a,a
        dec     a
        or      a
        ret
 
-div1:  ; enter with cf=0
-       ld      b,8
+div1:  ; bit 0, below
        add     a,a
-div10: adc     hl,hl
+       adc     hl,hl
        add     hl,de
        jr      nc,div11
        inc     a
-       jr      div01
-div11: add     a,a
-       djnz    div10
+div01: ; bit 1, above
+       add     a,a
+       adc     hl,hl
+       sbc     hl,de
+       jr      nc,div02
+       dec     a
+div12: ; bit 2, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      nc,div13
+       inc     a
+div03: ; bit 3, above
+       add     a,a
+       adc     hl,hl
+       sbc     hl,de
+       jr      nc,div04
+       dec     a
+div14: ; bit 4, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      nc,div15
+       inc     a
+div05: ; bit 5, above
+       add     a,a
+       adc     hl,hl
+       sbc     hl,de
+       jr      nc,div06
+       dec     a
+div16: ; bit 6, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      nc,div17
+       inc     a
+div07: ; bit 7, above
+       add     a,a
+       adc     hl,hl
+       sbc     hl,de
+       jr      nc,div08
+       dec     a
+div18: ; done, below
+       add     a,a
        ;inc    a
        ;dec    a                       ; compensation
        scf
@@ -1065,30 +1146,119 @@ div11: add     a,a
 ; when remainder negative and vice versa, need to clear carry after add hl,hl
 
 divn:  jr      c,divn1
-divn0: ld      b,8
+divn0: ; bit 0, above
        scf
        rla
-divn00:        adc     hl,hl
+       adc     hl,hl
        or      a
        sbc     hl,de
        jr      c,divn01
        dec     a
-       jr      divn11
-divn01:        add     a,a
-       djnz    divn00
+divn11:        ; bit 1, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      c,divn12
+       inc     a
+divn02:        ; bit 2, above
+       add     a,a
+       adc     hl,hl
+       or      a
+       sbc     hl,de
+       jr      c,divn03
+       dec     a
+divn13:        ; bit 3, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      c,divn14
+       inc     a
+divn04:        ; bit 4, above
+       add     a,a
+       adc     hl,hl
+       or      a
+       sbc     hl,de
+       jr      c,divn05
+       dec     a
+divn15:        ; bit 5, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      c,divn16
+       inc     a
+divn06:        ; bit 6, above
+       add     a,a
+       adc     hl,hl
+       or      a
+       sbc     hl,de
+       jr      c,divn07
+       dec     a
+divn17:        ; bit 7, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      c,divn18
+       inc     a
+divn08:        ; done, above
+       add     a,a
        dec     a
        or      a
        ret
 
-divn1: ld      b,8
+divn1: ; bit 0, below
        add     a,a
-divn10:        adc     hl,hl
+       adc     hl,hl
        add     hl,de
        jr      c,divn11
        inc     a
-       jr      divn01
-divn11:        add     a,a
-       djnz    divn10
+divn01:        ; bit 1, above
+       add     a,a
+       adc     hl,hl
+       or      a
+       sbc     hl,de
+       jr      c,divn02
+       dec     a
+divn12:        ; bit 2, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      c,divn13
+       inc     a
+divn03:        ; bit 3, above
+       add     a,a
+       adc     hl,hl
+       or      a
+       sbc     hl,de
+       jr      c,divn04
+       dec     a
+divn14:        ; bit 4, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      c,divn15
+       inc     a
+divn05:        ; bit 5, above
+       add     a,a
+       adc     hl,hl
+       or      a
+       sbc     hl,de
+       jr      c,divn06
+       dec     a
+divn16:        ; bit 6, below
+       add     a,a
+       adc     hl,hl
+       add     hl,de
+       jr      c,divn17
+       inc     a
+divn07:        ; bit 7, above
+       add     a,a
+       adc     hl,hl
+       or      a
+       sbc     hl,de
+       jr      c,divn08
+       dec     a
+divn18:        ; done, below
+       add     a,a
        ;inc    a
        ;dec    a                       ; compensation
        scf