// gcc specific
#define INLINE __attribute__((always_inline))
-// convenient byte register access
-#define A (self->regs.byte.a)
-#define X (self->regs.byte.x)
-#define Y (self->regs.byte.y)
-#define P (self->regs.byte.p)
-#define S (self->regs.byte.s)
-
-// convenient word register access
-#define SP (self->regs.word.sp)
-#define PC (self->regs.word.pc)
-
-// convenient flags bit access
-#define FLAG_C (1 << CPU_65C02_REG_P_BIT_C)
-#define FLAG_Z (1 << CPU_65C02_REG_P_BIT_Z)
-#define FLAG_I (1 << CPU_65C02_REG_P_BIT_I)
-#define FLAG_D (1 << CPU_65C02_REG_P_BIT_D)
-#define FLAG_V (1 << CPU_65C02_REG_P_BIT_V)
-#define FLAG_N (1 << CPU_65C02_REG_P_BIT_N)
-
-// read, write, fetch, push, pop byte/word for instruction decode/execute
-// these routines automatically apply cycle count of 1 (byte) or 2 (word)
-#define RB(addr) cpu_65c02_rb(self, (addr))
-#define RW(addr) cpu_65c02_rw(self, (addr))
-#define RW_ZPG(addr) cpu_65c02_rw_zpg(self, (addr))
-#define WB(addr, data) cpu_65c02_wb(self, (addr), (data))
-#define WW(addr, data) cpu_65c02_ww(self, (addr), (data))
-#define FB(addr) cpu_65c02_fb(self)
-#define FW(addr) cpu_65c02_fw(self)
-#define PHB(data) cpu_65c02_phb(self, (data))
-#define PHW(data) cpu_65c02_phw(self, (data))
-#define PLB(addr) cpu_65c02_plb(self)
-#define PLW(addr) cpu_65c02_plw(self)
-
// routines that take an effective address can also operate on a register
// by means of special memory locations that are inaccessible by software
#define EA_A (CPU_65C02_REG_A - CPU_65C02_N_REGS)
#define EA_P (CPU_65C02_REG_P - CPU_65C02_N_REGS)
#define EA_S (CPU_65C02_REG_S - CPU_65C02_N_REGS)
-// lvalue modes
-// effective address calculations that involve indexing require their
-// own callable routines (which are INLINE) to check for penalty cycles
-// those without indexing have their own routine just for readability
-#define EA_ABS() cpu_65c02_ea_abs(self)
-#define EA_ABS_IDX(rvalue) cpu_65c02_ea_abs_idx(self, (rvalue))
-#define EA_ABS_IDX_IND(rvalue) cpu_65c02_ea_abs_idx_ind(self, (rvalue))
-#define EA_ABS_IND() cpu_65c02_ea_abs_ind(self)
-#define EA_REL() cpu_65c02_ea_rel(self)
-#define EA_ZPG() cpu_65c02_ea_zpg(self)
-#define EA_ZPG_IDX(rvalue) cpu_65c02_ea_zpg_idx(self, (rvalue))
-#define EA_ZPG_IDX_IND(rvalue) cpu_65c02_ea_zpg_idx_ind(self, (rvalue))
-#define EA_ZPG_IND() cpu_65c02_ea_zpg_ind(self)
-#define EA_ZPG_IND_IDX(rvalue) cpu_65c02_ea_zpg_ind_idx(self, (rvalue))
-
-// rvalue modes
-#define IMM() FB()
-#define ABS() RB(EA_ABS())
-#define ABS_IDX(rvalue) RB(EA_ABS_IDX(rvalue))
-#define ABS_IDX_IND(rvalue) RB(EA_ABS_IDX_IND(rvalue))
-#define ABS_IND() RB(EA_ABS_IND())
-#define REL() RB(EA_REL())
-#define ZPG() RB(EA_ZPG())
-#define ZPG_IDX(rvalue) RB(EA_ZPG_IDX(rvalue))
-#define ZPG_IDX_IND(rvalue) RB(EA_ZPG_IDX_IND(rvalue))
-#define ZPG_IND() RB(EA_ZPG_IND())
-#define ZPG_IND_IDX(rvalue) RB(EA_ZPG_IND_IDX(rvalue))
-
-// decompose the conventional opcode here using special EA values, etc
-// write and read-modify-write instructions take an lvalue (EA) and do
-// their own memory accesses; read instructions take an rvalue, so we
-// either wrap an EA in RB(), or use FB() to fetch an immediate rvalue
-#define ADC(rvalue) cpu_65c02_adc(self, (rvalue))
-#define AND(rvalue) cpu_65c02_and(self, (rvalue))
-#define ASL(lvalue) cpu_65c02_asl(self, (lvalue))
-#define BBR0(rvalue, lvalue) cpu_65c02_bbr(self, (rvalue) & 1, (lvalue))
-#define BBR1(rvalue, lvalue) cpu_65c02_bbr(self, (rvalue) & 2, (lvalue))
-#define BBR2(rvalue, lvalue) cpu_65c02_bbr(self, (rvalue) & 4, (lvalue))
-#define BBR3(rvalue, lvalue) cpu_65c02_bbr(self, (rvalue) & 8, (lvalue))
-#define BBR4(rvalue, lvalue) cpu_65c02_bbr(self, (rvalue) & 0x10, (lvalue))
-#define BBR5(rvalue, lvalue) cpu_65c02_bbr(self, (rvalue) & 0x20, (lvalue))
-#define BBR6(rvalue, lvalue) cpu_65c02_bbr(self, (rvalue) & 0x40, (lvalue))
-#define BBR7(rvalue, lvalue) cpu_65c02_bbr(self, (rvalue) & 0x80, (lvalue))
-#define BBS0(rvalue, lvalue) cpu_65c02_bbs(self, (rvalue) & 1, (lvalue))
-#define BBS1(rvalue, lvalue) cpu_65c02_bbs(self, (rvalue) & 2, (lvalue))
-#define BBS2(rvalue, lvalue) cpu_65c02_bbs(self, (rvalue) & 4, (lvalue))
-#define BBS3(rvalue, lvalue) cpu_65c02_bbs(self, (rvalue) & 8, (lvalue))
-#define BBS4(rvalue, lvalue) cpu_65c02_bbs(self, (rvalue) & 0x10, (lvalue))
-#define BBS5(rvalue, lvalue) cpu_65c02_bbs(self, (rvalue) & 0x20, (lvalue))
-#define BBS6(rvalue, lvalue) cpu_65c02_bbs(self, (rvalue) & 0x40, (lvalue))
-#define BBS7(rvalue, lvalue) cpu_65c02_bbs(self, (rvalue) & 0x80, (lvalue))
-#define BCC(lvalue) cpu_65c02_bc(self, FLAG_C, (lvalue))
-#define BCS(lvalue) cpu_65c02_bs(self, FLAG_C, (lvalue))
-#define BEQ(lvalue) cpu_65c02_bs(self, FLAG_Z, (lvalue))
-#define BIT(rvalue) cpu_65c02_bit(self, (rvalue))
-// BIT_IMM() is the same as BIT() but only affects the Z flag
-#define BIT_IMM(rvalue) cpu_65c02_bit_imm(self, (rvalue))
-#define BMI(lvalue) cpu_65c02_bs(self, FLAG_N, (lvalue))
-#define BNE(lvalue) cpu_65c02_bc(self, FLAG_Z, (lvalue))
-#define BPL(lvalue) cpu_65c02_bc(self, FLAG_N, (lvalue))
-#define BRA(lvalue) cpu_65c02_bc(self, 0, (lvalue))
-#define BRK() cpu_65c02_brk(self)
-#define BVC(lvalue) cpu_65c02_bc(self, FLAG_V, (lvalue))
-#define BVS(lvalue) cpu_65c02_bs(self, FLAG_V, (lvalue))
-#define CLC() cpu_65c02_cl(self, FLAG_C)
-#define CLD() cpu_65c02_cl(self, FLAG_D)
-#define CLI() cpu_65c02_cl(self, FLAG_I)
-#define CLV() cpu_65c02_cl(self, FLAG_V)
-#define CMP(rvalue) cpu_65c02_cmp(self, A, (rvalue))
-#define CPX(rvalue) cpu_65c02_cmp(self, X, (rvalue))
-#define CPY(rvalue) cpu_65c02_cmp(self, Y, (rvalue))
-#define DEC(lvalue) cpu_65c02_dec(self, (lvalue))
-#define DEX() cpu_65c02_dec(self, EA_X)
-#define DEY() cpu_65c02_dec(self, EA_Y)
-#define EOR(rvalue) cpu_65c02_eor(self, (rvalue))
-// the illegal opcodes ILLmn() perform as m-byte, n-cycle nops
-#define ILL11() cpu_65c02_ill11(self)
-#define ILL22() cpu_65c02_ill22(self)
-#define ILL23() cpu_65c02_ill23(self)
-#define ILL24() cpu_65c02_ill24(self)
-#define ILL34() cpu_65c02_ill34(self)
-#define ILL38() cpu_65c02_ill38(self)
-#define INC(lvalue) cpu_65c02_inc(self, (lvalue))
-#define INX() cpu_65c02_inc(self, EA_X)
-#define INY() cpu_65c02_inc(self, EA_Y)
-#define JMP(lvalue) cpu_65c02_jmp(self, (lvalue))
-#define JSR(lvalue) cpu_65c02_jsr(self, (lvalue))
-#define LDA(rvalue) cpu_65c02_ld(self, EA_A, (rvalue))
-#define LDX(rvalue) cpu_65c02_ld(self, EA_X, (rvalue))
-#define LDY(rvalue) cpu_65c02_ld(self, EA_Y, (rvalue))
-#define LSR(lvalue) cpu_65c02_lsr(self, (lvalue))
-#define NOP() cpu_65c02_nop(self)
-#define ORA(rvalue) cpu_65c02_ora(self, (rvalue))
-#define PHA() cpu_65c02_ph(self, A)
-#define PHP() cpu_65c02_ph(self, P)
-#define PHX() cpu_65c02_ph(self, X)
-#define PHY() cpu_65c02_ph(self, Y)
-#define PLA() cpu_65c02_pl(self, EA_A)
-// note: cpu_65c02_plp() is like cpu_65c02_pl(), but does not set Z/N flags,
-// and forces unimplemented flags to 1 (need to ensure they stay 1 for php)
-#define PLP() cpu_65c02_plp(self)
-#define PLX() cpu_65c02_pl(self, EA_X)
-#define PLY() cpu_65c02_pl(self, EA_Y)
-#define RMB0(lvalue) cpu_65c02_rmb(self, 1, (lvalue))
-#define RMB1(lvalue) cpu_65c02_rmb(self, 2, (lvalue))
-#define RMB2(lvalue) cpu_65c02_rmb(self, 4, (lvalue))
-#define RMB3(lvalue) cpu_65c02_rmb(self, 8, (lvalue))
-#define RMB4(lvalue) cpu_65c02_rmb(self, 0x10, (lvalue))
-#define RMB5(lvalue) cpu_65c02_rmb(self, 0x20, (lvalue))
-#define RMB6(lvalue) cpu_65c02_rmb(self, 0x40, (lvalue))
-#define RMB7(lvalue) cpu_65c02_rmb(self, 0x80, (lvalue))
-#define ROL(lvalue) cpu_65c02_rol(self, (lvalue))
-#define ROR(lvalue) cpu_65c02_ror(self, (lvalue))
-#define RTI() cpu_65c02_rti(self)
-#define RTS() cpu_65c02_rts(self)
-#define SBC(rvalue) cpu_65c02_sbc(self, (rvalue))
-#define SEC() cpu_65c02_se(self, FLAG_C)
-#define SED() cpu_65c02_se(self, FLAG_D)
-#define SEI() cpu_65c02_se(self, FLAG_I)
-#define SMB0(lvalue) cpu_65c02_smb(self, 1, (lvalue))
-#define SMB1(lvalue) cpu_65c02_smb(self, 2, (lvalue))
-#define SMB2(lvalue) cpu_65c02_smb(self, 4, (lvalue))
-#define SMB3(lvalue) cpu_65c02_smb(self, 8, (lvalue))
-#define SMB4(lvalue) cpu_65c02_smb(self, 0x10, (lvalue))
-#define SMB5(lvalue) cpu_65c02_smb(self, 0x20, (lvalue))
-#define SMB6(lvalue) cpu_65c02_smb(self, 0x40, (lvalue))
-#define SMB7(lvalue) cpu_65c02_smb(self, 0x80, (lvalue))
-#define STA(lvalue) cpu_65c02_st(self, A, (lvalue))
-#define STP() cpu_65c02_stp(self)
-#define STX(lvalue) cpu_65c02_st(self, X, (lvalue))
-#define STY(lvalue) cpu_65c02_st(self, Y, (lvalue))
-#define STZ(lvalue) cpu_65c02_st(self, 0, (lvalue))
-#define TAX() cpu_65c02_ld(self, EA_X, A)
-#define TAY() cpu_65c02_ld(self, EA_Y, A)
-#define TRB(lvalue) cpu_65c02_trb(self, (lvalue))
-#define TSB(lvalue) cpu_65c02_tsb(self, (lvalue))
-#define TSX() cpu_65c02_ld(self, EA_X, S)
-#define TXA() cpu_65c02_ld(self, EA_A, X)
-// TXS is the only transfer instruction that does not set flags
-#define TXS() cpu_65c02_st(self, X, EA_S)
-#define TYA() cpu_65c02_ld(self, EA_A, Y)
-#define WAI() cpu_65c02_wai(self)
-
// initialization
void cpu_65c02_init(
struct cpu_65c02 *self,
}
INLINE int cpu_65c02_rw(struct cpu_65c02 *self, int addr) {
- int data = RB(addr);
- return data | (RB(addr + 1) << 8);
+ int data = cpu_65c02_rb(self, addr);
+ return data | (cpu_65c02_rb(self, addr + 1) << 8);
}
INLINE int cpu_65c02_rw_zpg(struct cpu_65c02 *self, int addr) {
- int data = RB(addr & 0xff);
- return data | (RB((addr + 1) & 0xff) << 8);
+ int data = cpu_65c02_rb(self, addr & 0xff);
+ return data | (cpu_65c02_rb(self, (addr + 1) & 0xff) << 8);
}
INLINE void cpu_65c02_wb(struct cpu_65c02 *self, int addr, int data) {
}
INLINE void cpu_65c02_ww(struct cpu_65c02 *self, int addr, int data) {
- WB(addr, data & 0xff);
- WB(addr + 1, data >> 8);
+ cpu_65c02_wb(self, addr, data & 0xff);
+ cpu_65c02_wb(self, addr + 1, data >> 8);
}
INLINE int cpu_65c02_fb(struct cpu_65c02 *self) {
- int data = RB(PC++);
+ int data = cpu_65c02_rb(self, self->regs.word.pc++);
return data;
}
INLINE int cpu_65c02_fw(struct cpu_65c02 *self) {
- int data = FB();
- return data | (FB() << 8);
+ int data = cpu_65c02_fb(self);
+ return data | (cpu_65c02_fb(self) << 8);
}
INLINE void cpu_65c02_phb(struct cpu_65c02 *self, int data) {
- WB(SP, data);
- --S;
+ cpu_65c02_wb(self, self->regs.word.sp, data);
+ --self->regs.byte.s;
}
INLINE void cpu_65c02_phw(struct cpu_65c02 *self, int data) {
- PHB(data >> 8);
- PHB(data & 0xff);
+ cpu_65c02_phb(self, data >> 8);
+ cpu_65c02_phb(self, data & 0xff);
}
INLINE int cpu_65c02_plb(struct cpu_65c02 *self) {
- ++S;
- return RB(SP);
+ ++self->regs.byte.s;
+ return cpu_65c02_rb(self, self->regs.word.sp);
}
INLINE int cpu_65c02_plw(struct cpu_65c02 *self) {
- int data = PLB();
- return data | (PLB() << 8);
+ int data = cpu_65c02_plb(self);
+ return data | (cpu_65c02_plb(self) << 8);
}
// effective address calculation
INLINE int cpu_65c02_ea_abs(struct cpu_65c02 *self) {
- return FW();
+ return cpu_65c02_fw(self);
}
INLINE int cpu_65c02_ea_abs_idx(struct cpu_65c02 *self, int rvalue) {
- int addr = EA_ABS();
+ int addr = cpu_65c02_ea_abs(self);
self->cycles += ((addr & 0xff) + (rvalue & 0xff)) >> 8;
return addr + rvalue;
}
INLINE int cpu_65c02_ea_abs_idx_ind(struct cpu_65c02 *self, int rvalue) {
- return RW(EA_ABS_IDX(rvalue));
+ return cpu_65c02_rw(self, cpu_65c02_ea_abs_idx(self, rvalue));
}
INLINE int cpu_65c02_ea_abs_ind(struct cpu_65c02 *self) {
- return RW(EA_ABS());
+ return cpu_65c02_rw(self, cpu_65c02_ea_abs(self));
}
INLINE int cpu_65c02_ea_rel(struct cpu_65c02 *self) {
- int offset = FB();
- return offset - ((offset << 1) & 0x100); // sign extend
+ int offset = cpu_65c02_fb(self);
+ return offset - ((offset << 1) & 0x100);
}
INLINE int cpu_65c02_ea_zpg(struct cpu_65c02 *self) {
- return FB();
+ return cpu_65c02_fb(self);
}
INLINE int cpu_65c02_ea_zpg_idx(struct cpu_65c02 *self, int rvalue) {
- return (EA_ZPG() + rvalue) & 0xff;
+ return (cpu_65c02_ea_zpg(self) + rvalue) & 0xff;
}
INLINE int cpu_65c02_ea_zpg_idx_ind(struct cpu_65c02 *self, int rvalue) {
- return RW_ZPG(EA_ZPG_IDX(rvalue));
+ return cpu_65c02_rw_zpg(self, cpu_65c02_ea_zpg_idx(self, rvalue));
}
INLINE int cpu_65c02_ea_zpg_ind(struct cpu_65c02 *self) {
- return RW_ZPG(EA_ZPG());
+ return cpu_65c02_rw_zpg(self, cpu_65c02_ea_zpg(self));
}
INLINE int cpu_65c02_ea_zpg_ind_idx(struct cpu_65c02 *self, int rvalue) {
- int addr = RW_ZPG(EA_ZPG());
+ int addr = cpu_65c02_rw_zpg(self, cpu_65c02_ea_zpg(self));
self->cycles += ((addr & 0xff) + (rvalue & 0xff)) >> 8;
return addr + rvalue;
}
INLINE void cpu_65c02_adc(struct cpu_65c02 *self, int rvalue) {
int result0, result1, result2;
if (self->regs.bit.df) {
- result0 = (A & 0xf) + (rvalue & 0xf) + self->regs.bit.cf;
+ result0 = (self->regs.byte.a & 0xf) + (rvalue & 0xf) + self->regs.bit.cf;
if (result0 >= 0xa)
result0 = (result0 + 6) & 0x1f;
- result0 += (A & 0x70) + (rvalue & 0x70);
- result1 = (A & 0x80) + (rvalue & 0x80) + result0;
+ result0 += (self->regs.byte.a & 0x70) + (rvalue & 0x70);
+ result1 = (self->regs.byte.a & 0x80) + (rvalue & 0x80) + result0;
result2 = result1;
if (result2 >= 0xa0)
result2 = (result2 + 0x60) & 0x1ff;
}
else {
- result0 = (A & 0x7f) + (rvalue & 0x7f) + self->regs.bit.cf;
- result1 = (A & 0x80) + (rvalue & 0x80) + result0;
+ result0 = (self->regs.byte.a & 0x7f) + (rvalue & 0x7f) + self->regs.bit.cf;
+ result1 = (self->regs.byte.a & 0x80) + (rvalue & 0x80) + result0;
result2 = result1;
}
- A = result2 & 0xff;
+ self->regs.byte.a = result2 & 0xff;
self->regs.bit.cf = result2 >> 8;
self->regs.bit.zf = (result2 & 0xff) == 0;
self->regs.bit.vf = ((result0 >> 7) ^ (result1 >> 8)) & 1;
}
INLINE void cpu_65c02_and(struct cpu_65c02 *self, int rvalue) {
- int result = A & rvalue;
- A = result;
+ int result = self->regs.byte.a & rvalue;
+ self->regs.byte.a = result;
self->regs.bit.zf = result == 0;
self->regs.bit.nf = (result >> 7) & 1;
}
INLINE void cpu_65c02_asl(struct cpu_65c02 *self, int lvalue) {
- int result = RB(lvalue) << 1;
+ int result = cpu_65c02_rb(self, lvalue) << 1;
++self->cycles;
- WB(lvalue, result & 0xff);
+ cpu_65c02_wb(self, lvalue, result & 0xff);
self->regs.bit.cf = result >> 8;
self->regs.bit.zf = (result & 0xff) == 0;
self->regs.bit.nf = (result >> 7) & 1;
INLINE void cpu_65c02_bbr(struct cpu_65c02 *self, int rvalue, int lvalue) {
if (rvalue == 0) {
- self->cycles += ((PC & 0xff) + (lvalue & 0xff)) >> 8;
- PC = (PC + lvalue) & 0xffff;
+ self->cycles += ((self->regs.word.pc & 0xff) + (lvalue & 0xff)) >> 8;
+ self->regs.word.pc = (self->regs.word.pc + lvalue) & 0xffff;
}
}
INLINE void cpu_65c02_bbs(struct cpu_65c02 *self, int rvalue, int lvalue) {
if (rvalue) {
- self->cycles += ((PC & 0xff) + (lvalue & 0xff)) >> 8;
- PC = (PC + lvalue) & 0xffff;
+ self->cycles += ((self->regs.word.pc & 0xff) + (lvalue & 0xff)) >> 8;
+ self->regs.word.pc = (self->regs.word.pc + lvalue) & 0xffff;
}
}
INLINE void cpu_65c02_bc(struct cpu_65c02 *self, int flag, int lvalue) {
- if ((P & flag) == 0) {
- self->cycles += ((PC & 0xff) + (lvalue & 0xff)) >> 8;
- PC = (PC + lvalue) & 0xffff;
+ if ((self->regs.byte.p & flag) == 0) {
+ self->cycles += ((self->regs.word.pc & 0xff) + (lvalue & 0xff)) >> 8;
+ self->regs.word.pc = (self->regs.word.pc + lvalue) & 0xffff;
}
}
INLINE void cpu_65c02_bs(struct cpu_65c02 *self, int flag, int lvalue) {
- if (P & flag) {
- self->cycles += ((PC & 0xff) + (lvalue & 0xff)) >> 8;
- PC = (PC + lvalue) & 0xffff;
+ if (self->regs.byte.p & flag) {
+ self->cycles += ((self->regs.word.pc & 0xff) + (lvalue & 0xff)) >> 8;
+ self->regs.word.pc = (self->regs.word.pc + lvalue) & 0xffff;
}
}
INLINE void cpu_65c02_bit(struct cpu_65c02 *self, int rvalue) {
- int result = A & rvalue;
+ int result = self->regs.byte.a & rvalue;
self->regs.bit.zf = result == 0;
self->regs.bit.vf = (rvalue >> 6) & 1;
self->regs.bit.nf = (rvalue >> 7) & 1;
}
INLINE void cpu_65c02_bit_imm(struct cpu_65c02 *self, int rvalue) {
- int result = A & rvalue;
+ int result = self->regs.byte.a & rvalue;
self->regs.bit.zf = result == 0;
}
INLINE void cpu_65c02_brk(struct cpu_65c02 *self) {
- ++self->cycles; // operand is ignored
- PHW((PC + 1) & 0xffff);
- PHB(P); // already has break flag set
- PC = RW(IRQ_VECTOR);
+ ++self->cycles;
+ cpu_65c02_phw(self, (self->regs.word.pc + 1) & 0xffff);
+ cpu_65c02_phb(self, self->regs.byte.p);
+ self->regs.word.pc = cpu_65c02_rw(self, IRQ_VECTOR);
self->regs.bit._if = true;
self->regs.bit.df = false;
}
INLINE void cpu_65c02_cl(struct cpu_65c02 *self, int flag) {
- P &= ~flag;
+ self->regs.byte.p &= ~flag;
}
INLINE void cpu_65c02_cmp(struct cpu_65c02 *self, int rvalue0, int rvalue1) {
}
INLINE void cpu_65c02_dec(struct cpu_65c02 *self, int lvalue) {
- int result = (RB(lvalue) - 1) & 0xff;
+ int result = (cpu_65c02_rb(self, lvalue) - 1) & 0xff;
++self->cycles;
- WB(lvalue, result);
+ cpu_65c02_wb(self, lvalue, result);
self->regs.bit.zf = result == 0;
self->regs.bit.nf = (result >> 7) & 1;
}
INLINE void cpu_65c02_eor(struct cpu_65c02 *self, int rvalue) {
- int result = A ^ rvalue;
- A = result;
+ int result = self->regs.byte.a ^ rvalue;
+ self->regs.byte.a = result;
self->regs.bit.zf = result == 0;
self->regs.bit.nf = (result >> 7) & 1;
}
INLINE void cpu_65c02_ill22(struct cpu_65c02 *self) {
++self->cycles;
- PC = (PC + 1) & 0xffff;
+ self->regs.word.pc = (self->regs.word.pc + 1) & 0xffff;
}
INLINE void cpu_65c02_ill23(struct cpu_65c02 *self) {
self->cycles += 2;
- PC = (PC + 1) & 0xffff;
+ self->regs.word.pc = (self->regs.word.pc + 1) & 0xffff;
}
INLINE void cpu_65c02_ill24(struct cpu_65c02 *self) {
self->cycles += 3;
- PC = (PC + 1) & 0xffff;
+ self->regs.word.pc = (self->regs.word.pc + 1) & 0xffff;
}
INLINE void cpu_65c02_ill34(struct cpu_65c02 *self) {
self->cycles += 3;
- PC = (PC + 2) & 0xffff;
+ self->regs.word.pc = (self->regs.word.pc + 2) & 0xffff;
}
INLINE void cpu_65c02_ill38(struct cpu_65c02 *self) {
self->cycles += 7;
- PC = (PC + 2) & 0xffff;
+ self->regs.word.pc = (self->regs.word.pc + 2) & 0xffff;
}
INLINE void cpu_65c02_inc(struct cpu_65c02 *self, int lvalue) {
- int result = (RB(lvalue) + 1) & 0xff;
+ int result = (cpu_65c02_rb(self, lvalue) + 1) & 0xff;
++self->cycles;
- WB(lvalue, result);
+ cpu_65c02_wb(self, lvalue, result);
self->regs.bit.zf = result == 0;
self->regs.bit.nf = (result >> 7) & 1;
}
INLINE void cpu_65c02_jmp(struct cpu_65c02 *self, int lvalue) {
- PC = lvalue;
+ self->regs.word.pc = lvalue;
}
INLINE void cpu_65c02_jsr(struct cpu_65c02 *self, int lvalue) {
- PHW((PC - 1) & 0xffff);
- PC = lvalue;
+ cpu_65c02_phw(self, (self->regs.word.pc - 1) & 0xffff);
+ self->regs.word.pc = lvalue;
}
INLINE void cpu_65c02_ld(struct cpu_65c02 *self, int lvalue, int rvalue) {
- WB(lvalue, rvalue);
+ cpu_65c02_wb(self, lvalue, rvalue);
self->regs.bit.zf = rvalue == 0;
self->regs.bit.nf = (rvalue >> 7) & 1;
}
INLINE void cpu_65c02_lsr(struct cpu_65c02 *self, int lvalue) {
- int result = RB(lvalue);
+ int result = cpu_65c02_rb(self, lvalue);
++self->cycles;
- WB(lvalue, result >> 1);
+ cpu_65c02_wb(self, lvalue, result >> 1);
self->regs.bit.cf = result & 1;
self->regs.bit.zf = (result & 0xfe) == 0;
self->regs.bit.nf = false;
}
INLINE void cpu_65c02_ora(struct cpu_65c02 *self, int rvalue) {
- int result = A | rvalue;
- A = result;
+ int result = self->regs.byte.a | rvalue;
+ self->regs.byte.a = result;
self->regs.bit.zf = result == 0;
self->regs.bit.nf = (result >> 7) & 1;
}
INLINE void cpu_65c02_ph(struct cpu_65c02 *self, int rvalue) {
- PHB(rvalue);
+ cpu_65c02_phb(self, rvalue);
}
INLINE void cpu_65c02_pl(struct cpu_65c02 *self, int lvalue) {
- int result = PLB();
- WB(lvalue, result);
+ int result = cpu_65c02_plb(self);
+ cpu_65c02_wb(self, lvalue, result);
self->regs.bit.zf = result == 0;
self->regs.bit.nf = (result >> 7) & 1;
}
INLINE void cpu_65c02_plp(struct cpu_65c02 *self) {
- P = PLB() | 0x30;
+ self->regs.byte.p = cpu_65c02_plb(self) | 0x30;
}
INLINE void cpu_65c02_rmb(struct cpu_65c02 *self, int rvalue, int lvalue) {
- int result = RB(lvalue) & ~rvalue;
+ int result = cpu_65c02_rb(self, lvalue) & ~rvalue;
++self->cycles;
- WB(lvalue, result);
+ cpu_65c02_wb(self, lvalue, result);
}
INLINE void cpu_65c02_rol(struct cpu_65c02 *self, int lvalue) {
- int result = (RB(lvalue) << 1) | self->regs.bit.cf;
+ int result = (cpu_65c02_rb(self, lvalue) << 1) | self->regs.bit.cf;
++self->cycles;
- WB(lvalue, result & 0xff);
+ cpu_65c02_wb(self, lvalue, result & 0xff);
self->regs.bit.cf = result >> 8;
self->regs.bit.zf = (result & 0xff) == 0;
self->regs.bit.nf = (result >> 7) & 1;
}
INLINE void cpu_65c02_ror(struct cpu_65c02 *self, int lvalue) {
- int result = RB(lvalue) | (self->regs.bit.cf << 8);
+ int result = cpu_65c02_rb(self, lvalue) | (self->regs.bit.cf << 8);
++self->cycles;
- WB(lvalue, result >> 1);
+ cpu_65c02_wb(self, lvalue, result >> 1);
self->regs.bit.cf = result & 1;
self->regs.bit.zf = (result & 0x1fe) == 0;
self->regs.bit.nf = (result >> 8) & 1;
}
INLINE void cpu_65c02_rti(struct cpu_65c02 *self) {
- P = PLB() | 0x30;
- PC = PLW();
+ self->regs.byte.p = cpu_65c02_plb(self) | 0x30;
+ self->regs.word.pc = cpu_65c02_plw(self);
}
INLINE void cpu_65c02_rts(struct cpu_65c02 *self) {
- PC = (PLW() + 1) & 0xffff;
+ self->regs.word.pc = (cpu_65c02_plw(self) + 1) & 0xffff;
}
INLINE void cpu_65c02_sbc(struct cpu_65c02 *self, int rvalue) {
rvalue ^= 0xff;
int result0, result1, result2;
if (self->regs.bit.df) {
- result0 = (A & 0xf) + (rvalue & 0xf) + self->regs.bit.cf;
+ result0 = (self->regs.byte.a & 0xf) + (rvalue & 0xf) + self->regs.bit.cf;
if (result0 < 0x10)
result0 = (result0 - 6) & 0x1f;
- result0 += (A & 0x70) + (rvalue & 0x70);
- result1 = (A & 0x80) + (rvalue & 0x80) + result0;
+ result0 += (self->regs.byte.a & 0x70) + (rvalue & 0x70);
+ result1 = (self->regs.byte.a & 0x80) + (rvalue & 0x80) + result0;
result2 = result1;
if (result2 < 0x100)
result2 = (result2 - 0x60) & 0x1ff;
}
else {
- result0 = (A & 0x7f) + (rvalue & 0x7f) + self->regs.bit.cf;
- result1 = (A & 0x80) + (rvalue & 0x80) + result0;
+ result0 = (self->regs.byte.a & 0x7f) + (rvalue & 0x7f) + self->regs.bit.cf;
+ result1 = (self->regs.byte.a & 0x80) + (rvalue & 0x80) + result0;
result2 = result1;
}
- A = result2 & 0xff;
+ self->regs.byte.a = result2 & 0xff;
self->regs.bit.cf = result2 >> 8;
self->regs.bit.zf = (result2 & 0xff) == 0;
self->regs.bit.vf = ((result0 >> 7) ^ (result1 >> 8)) & 1;
}
INLINE void cpu_65c02_se(struct cpu_65c02 *self, int flag) {
- P |= flag;
+ self->regs.byte.p |= flag;
}
INLINE void cpu_65c02_smb(struct cpu_65c02 *self, int rvalue, int lvalue) {
- int result = RB(lvalue) | rvalue;
+ int result = cpu_65c02_rb(self, lvalue) | rvalue;
++self->cycles;
- WB(lvalue, result);
+ cpu_65c02_wb(self, lvalue, result);
}
INLINE void cpu_65c02_st(struct cpu_65c02 *self, int rvalue, int lvalue) {
- WB(lvalue, rvalue);
+ cpu_65c02_wb(self, lvalue, rvalue);
}
INLINE void cpu_65c02_stp(struct cpu_65c02 *self) {
}
INLINE void cpu_65c02_trb(struct cpu_65c02 *self, int lvalue) {
- int result = RB(lvalue);
+ int result = cpu_65c02_rb(self, lvalue);
++self->cycles;
- WB(lvalue, result & ~A);
- result &= A;
+ cpu_65c02_wb(self, lvalue, result & ~self->regs.byte.a);
+ result &= self->regs.byte.a;
self->regs.bit.zf = result == 0;
}
INLINE void cpu_65c02_tsb(struct cpu_65c02 *self, int lvalue) {
- int result = RB(lvalue);
+ int result = cpu_65c02_rb(self, lvalue);
++self->cycles;
- WB(lvalue, result | A);
- result &= A;
+ cpu_65c02_wb(self, lvalue, result | self->regs.byte.a);
+ result &= self->regs.byte.a;
self->regs.bit.zf = result == 0;
}
// instruction decode
void cpu_65c02_execute(struct cpu_65c02 *self) {
- switch (FB()) {
+ switch (cpu_65c02_fb(self)) {
case 0x00:
- BRK();
+ cpu_65c02_brk(self);
break;
case 0x01:
- ORA(ZPG_IDX_IND(X));
+ cpu_65c02_ora(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx_ind(self, self->regs.byte.x)));
break;
case 0x02:
- ILL22();
+ cpu_65c02_ill22(self);
break;
case 0x03:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x04:
- TSB(EA_ZPG());
+ cpu_65c02_tsb(self, cpu_65c02_ea_zpg(self));
break;
case 0x05:
- ORA(ZPG());
+ cpu_65c02_ora(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0x06:
- ASL(EA_ZPG());
+ cpu_65c02_asl(self, cpu_65c02_ea_zpg(self));
break;
case 0x07:
- RMB0(EA_ZPG());
+ cpu_65c02_rmb(self, 1, cpu_65c02_ea_zpg(self));
break;
case 0x08:
- PHP();
+ cpu_65c02_ph(self, self->regs.byte.p);
break;
case 0x09:
- ORA(IMM());
+ cpu_65c02_ora(self, cpu_65c02_fb(self));
break;
case 0x0a:
- ASL(EA_A);
+ cpu_65c02_asl(self, EA_A);
break;
case 0x0b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x0c:
- TSB(EA_ABS());
+ cpu_65c02_tsb(self, cpu_65c02_ea_abs(self));
break;
case 0x0d:
- ORA(ABS());
+ cpu_65c02_ora(self, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0x0e:
- ASL(EA_ABS());
+ cpu_65c02_asl(self, cpu_65c02_ea_abs(self));
break;
case 0x0f:
{
- int rvalue = ZPG();
- BBR0(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbr(self, rvalue & 1, cpu_65c02_ea_rel(self));
}
break;
case 0x10:
- BPL(EA_REL());
+ cpu_65c02_bc(self, (1 << CPU_65C02_REG_P_BIT_N), cpu_65c02_ea_rel(self));
break;
case 0x11:
- ORA(ZPG_IND_IDX(Y));
+ cpu_65c02_ora(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind_idx(self, self->regs.byte.y)));
break;
case 0x12:
- ORA(ZPG_IND());
+ cpu_65c02_ora(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind(self)));
break;
case 0x13:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x14:
- TRB(EA_ZPG());
+ cpu_65c02_trb(self, cpu_65c02_ea_zpg(self));
break;
case 0x15:
- ORA(ZPG_IDX(X));
+ cpu_65c02_ora(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x)));
break;
case 0x16:
- ASL(EA_ZPG_IDX(X));
+ cpu_65c02_asl(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x));
break;
case 0x17:
- RMB1(EA_ZPG());
+ cpu_65c02_rmb(self, 2, cpu_65c02_ea_zpg(self));
break;
case 0x18:
- CLC();
+ cpu_65c02_cl(self, (1 << CPU_65C02_REG_P_BIT_C));
break;
case 0x19:
- ORA(ABS_IDX(Y));
+ cpu_65c02_ora(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.y)));
break;
case 0x1a:
- INC(EA_A);
+ cpu_65c02_inc(self, EA_A);
break;
case 0x1b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x1c:
- TRB(EA_ABS());
+ cpu_65c02_trb(self, cpu_65c02_ea_abs(self));
break;
case 0x1d:
- ORA(ABS_IDX(X));
+ cpu_65c02_ora(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x)));
break;
case 0x1e:
- ASL(EA_ABS_IDX(X));
+ cpu_65c02_asl(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x));
break;
case 0x1f:
{
- int rvalue = ZPG();
- BBR1(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbr(self, rvalue & 2, cpu_65c02_ea_rel(self));
}
break;
case 0x20:
- JSR(EA_ABS());
+ cpu_65c02_jsr(self, cpu_65c02_ea_abs(self));
break;
case 0x21:
- AND(ZPG_IDX_IND(X));
+ cpu_65c02_and(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx_ind(self, self->regs.byte.x)));
break;
case 0x22:
- ILL22();
+ cpu_65c02_ill22(self);
break;
case 0x23:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x24:
- BIT(ZPG());
+ cpu_65c02_bit(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0x25:
- AND(ZPG());
+ cpu_65c02_and(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0x26:
- ROL(EA_ZPG());
+ cpu_65c02_rol(self, cpu_65c02_ea_zpg(self));
break;
case 0x27:
- RMB2(EA_ZPG());
+ cpu_65c02_rmb(self, 4, cpu_65c02_ea_zpg(self));
break;
case 0x28:
- PLP();
+ cpu_65c02_plp(self);
break;
case 0x29:
- AND(IMM());
+ cpu_65c02_and(self, cpu_65c02_fb(self));
break;
case 0x2a:
- ROL(EA_A);
+ cpu_65c02_rol(self, EA_A);
break;
case 0x2b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x2c:
- BIT(ABS());
+ cpu_65c02_bit(self, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0x2d:
- AND(ABS());
+ cpu_65c02_and(self, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0x2e:
- ROL(EA_ABS());
+ cpu_65c02_rol(self, cpu_65c02_ea_abs(self));
break;
case 0x2f:
{
- int rvalue = ZPG();
- BBR2(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbr(self, rvalue & 4, cpu_65c02_ea_rel(self));
}
break;
case 0x30:
- BMI(EA_REL());
+ cpu_65c02_bs(self, (1 << CPU_65C02_REG_P_BIT_N), cpu_65c02_ea_rel(self));
break;
case 0x31:
- AND(ZPG_IND_IDX(Y));
+ cpu_65c02_and(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind_idx(self, self->regs.byte.y)));
break;
case 0x32:
- AND(ZPG_IND());
+ cpu_65c02_and(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind(self)));
break;
case 0x33:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x34:
- BIT(ZPG_IDX(X));
+ cpu_65c02_bit(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x)));
break;
case 0x35:
- AND(ZPG_IDX(X));
+ cpu_65c02_and(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x)));
break;
case 0x36:
- ROL(EA_ZPG_IDX(X));
+ cpu_65c02_rol(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x));
break;
case 0x37:
- RMB3(EA_ZPG());
+ cpu_65c02_rmb(self, 8, cpu_65c02_ea_zpg(self));
break;
case 0x38:
- SEC();
+ cpu_65c02_se(self, (1 << CPU_65C02_REG_P_BIT_C));
break;
case 0x39:
- AND(ABS_IDX(Y));
+ cpu_65c02_and(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.y)));
break;
case 0x3a:
- DEC(EA_A);
+ cpu_65c02_dec(self, EA_A);
break;
case 0x3b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x3c:
- BIT(ABS_IDX(X));
+ cpu_65c02_bit(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x)));
break;
case 0x3d:
- AND(ABS_IDX(X));
+ cpu_65c02_and(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x)));
break;
case 0x3e:
- ROL(EA_ABS_IDX(X));
+ cpu_65c02_rol(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x));
break;
case 0x3f:
{
- int rvalue = ZPG();
- BBR3(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbr(self, rvalue & 8, cpu_65c02_ea_rel(self));
}
break;
case 0x40:
- RTI();
+ cpu_65c02_rti(self);
break;
case 0x41:
- EOR(ZPG_IDX_IND(X));
+ cpu_65c02_eor(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx_ind(self, self->regs.byte.x)));
break;
case 0x42:
- ILL22();
+ cpu_65c02_ill22(self);
break;
case 0x43:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x44:
- ILL23();
+ cpu_65c02_ill23(self);
break;
case 0x45:
- EOR(ZPG());
+ cpu_65c02_eor(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0x46:
- LSR(EA_ZPG());
+ cpu_65c02_lsr(self, cpu_65c02_ea_zpg(self));
break;
case 0x47:
- RMB4(EA_ZPG());
+ cpu_65c02_rmb(self, 0x10, cpu_65c02_ea_zpg(self));
break;
case 0x48:
- PHA();
+ cpu_65c02_ph(self, self->regs.byte.a);
break;
case 0x49:
- EOR(IMM());
+ cpu_65c02_eor(self, cpu_65c02_fb(self));
break;
case 0x4a:
- LSR(EA_A);
+ cpu_65c02_lsr(self, EA_A);
break;
case 0x4b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x4c:
- JMP(EA_ABS());
+ cpu_65c02_jmp(self, cpu_65c02_ea_abs(self));
break;
case 0x4d:
- EOR(ABS());
+ cpu_65c02_eor(self, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0x4e:
- LSR(EA_ABS());
+ cpu_65c02_lsr(self, cpu_65c02_ea_abs(self));
break;
case 0x4f:
{
- int rvalue = ZPG();
- BBR4(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbr(self, rvalue & 0x10, cpu_65c02_ea_rel(self));
}
break;
case 0x50:
- BVC(EA_REL());
+ cpu_65c02_bc(self, (1 << CPU_65C02_REG_P_BIT_V), cpu_65c02_ea_rel(self));
break;
case 0x51:
- EOR(ZPG_IND_IDX(Y));
+ cpu_65c02_eor(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind_idx(self, self->regs.byte.y)));
break;
case 0x52:
- EOR(ZPG_IND());
+ cpu_65c02_eor(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind(self)));
break;
case 0x53:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x54:
- ILL24();
+ cpu_65c02_ill24(self);
break;
case 0x55:
- EOR(ZPG_IDX(X));
+ cpu_65c02_eor(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x)));
break;
case 0x56:
- LSR(EA_ZPG_IDX(X));
+ cpu_65c02_lsr(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x));
break;
case 0x57:
- RMB5(EA_ZPG());
+ cpu_65c02_rmb(self, 0x20, cpu_65c02_ea_zpg(self));
break;
case 0x58:
- CLI();
+ cpu_65c02_cl(self, (1 << CPU_65C02_REG_P_BIT_I));
break;
case 0x59:
- EOR(ABS_IDX(Y));
+ cpu_65c02_eor(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.y)));
break;
case 0x5a:
- PHY();
+ cpu_65c02_ph(self, self->regs.byte.y);
break;
case 0x5b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x5c:
- ILL38();
+ cpu_65c02_ill38(self);
break;
case 0x5d:
- EOR(ABS_IDX(X));
+ cpu_65c02_eor(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x)));
break;
case 0x5e:
- LSR(EA_ABS_IDX(X));
+ cpu_65c02_lsr(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x));
break;
case 0x5f:
{
- int rvalue = ZPG();
- BBR5(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbr(self, rvalue & 0x20, cpu_65c02_ea_rel(self));
}
break;
case 0x60:
- RTS();
+ cpu_65c02_rts(self);
break;
case 0x61:
- ADC(ZPG_IDX_IND(X));
+ cpu_65c02_adc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx_ind(self, self->regs.byte.x)));
break;
case 0x62:
- ILL22();
+ cpu_65c02_ill22(self);
break;
case 0x63:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x64:
- STZ(EA_ZPG());
+ cpu_65c02_st(self, 0, cpu_65c02_ea_zpg(self));
break;
case 0x65:
- ADC(ZPG());
+ cpu_65c02_adc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0x66:
- ROR(EA_ZPG());
+ cpu_65c02_ror(self, cpu_65c02_ea_zpg(self));
break;
case 0x67:
- RMB6(EA_ZPG());
+ cpu_65c02_rmb(self, 0x40, cpu_65c02_ea_zpg(self));
break;
case 0x68:
- PLA();
+ cpu_65c02_pl(self, EA_A);
break;
case 0x69:
- ADC(IMM());
+ cpu_65c02_adc(self, cpu_65c02_fb(self));
break;
case 0x6a:
- ROR(EA_A);
+ cpu_65c02_ror(self, EA_A);
break;
case 0x6b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x6c:
- JMP(EA_ABS_IND());
+ cpu_65c02_jmp(self, cpu_65c02_ea_abs_ind(self));
break;
case 0x6d:
- ADC(ABS());
+ cpu_65c02_adc(self, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0x6e:
- ROR(EA_ABS());
+ cpu_65c02_ror(self, cpu_65c02_ea_abs(self));
break;
case 0x6f:
{
- int rvalue = ZPG();
- BBR6(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbr(self, rvalue & 0x40, cpu_65c02_ea_rel(self));
}
break;
case 0x70:
- BVS(EA_REL());
+ cpu_65c02_bs(self, (1 << CPU_65C02_REG_P_BIT_V), cpu_65c02_ea_rel(self));
break;
case 0x71:
- ADC(ZPG_IND_IDX(Y));
+ cpu_65c02_adc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind_idx(self, self->regs.byte.y)));
break;
case 0x72:
- ADC(ZPG_IND());
+ cpu_65c02_adc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind(self)));
break;
case 0x73:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x74:
- STZ(EA_ZPG_IDX(X));
+ cpu_65c02_st(self, 0, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x));
break;
case 0x75:
- ADC(ZPG_IDX(X));
+ cpu_65c02_adc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x)));
break;
case 0x76:
- ROR(EA_ZPG_IDX(X));
+ cpu_65c02_ror(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x));
break;
case 0x77:
- RMB7(EA_ZPG());
+ cpu_65c02_rmb(self, 0x80, cpu_65c02_ea_zpg(self));
break;
case 0x78:
- SEI();
+ cpu_65c02_se(self, (1 << CPU_65C02_REG_P_BIT_I));
break;
case 0x79:
- ADC(ABS_IDX(Y));
+ cpu_65c02_adc(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.y)));
break;
case 0x7a:
- PLY();
+ cpu_65c02_pl(self, EA_Y);
break;
case 0x7b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x7c:
- JMP(EA_ABS_IDX_IND(X));
+ cpu_65c02_jmp(self, cpu_65c02_ea_abs_idx_ind(self, self->regs.byte.x));
break;
case 0x7d:
- ADC(ABS_IDX(X));
+ cpu_65c02_adc(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x)));
break;
case 0x7e:
- ROR(EA_ABS_IDX(X));
+ cpu_65c02_ror(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x));
break;
case 0x7f:
{
- int rvalue = ZPG();
- BBR7(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbr(self, rvalue & 0x80, cpu_65c02_ea_rel(self));
}
break;
case 0x80:
- BRA(EA_REL());
+ cpu_65c02_bc(self, 0, cpu_65c02_ea_rel(self));
break;
case 0x81:
- STA(EA_ZPG_IDX_IND(X));
+ cpu_65c02_st(self, self->regs.byte.a, cpu_65c02_ea_zpg_idx_ind(self, self->regs.byte.x));
break;
case 0x82:
- ILL22();
+ cpu_65c02_ill22(self);
break;
case 0x83:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x84:
- STY(EA_ZPG());
+ cpu_65c02_st(self, self->regs.byte.y, cpu_65c02_ea_zpg(self));
break;
case 0x85:
- STA(EA_ZPG());
+ cpu_65c02_st(self, self->regs.byte.a, cpu_65c02_ea_zpg(self));
break;
case 0x86:
- STX(EA_ZPG());
+ cpu_65c02_st(self, self->regs.byte.x, cpu_65c02_ea_zpg(self));
break;
case 0x87:
- SMB0(EA_ZPG());
+ cpu_65c02_smb(self, 1, cpu_65c02_ea_zpg(self));
break;
case 0x88:
- DEY();
+ cpu_65c02_dec(self, EA_Y);
break;
case 0x89:
- BIT_IMM(IMM());
+ cpu_65c02_bit_imm(self, cpu_65c02_fb(self));
break;
case 0x8a:
- TXA();
+ cpu_65c02_ld(self, EA_A, self->regs.byte.x);
break;
case 0x8b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x8c:
- STY(EA_ABS());
+ cpu_65c02_st(self, self->regs.byte.y, cpu_65c02_ea_abs(self));
break;
case 0x8d:
- STA(EA_ABS());
+ cpu_65c02_st(self, self->regs.byte.a, cpu_65c02_ea_abs(self));
break;
case 0x8e:
- STX(EA_ABS());
+ cpu_65c02_st(self, self->regs.byte.x, cpu_65c02_ea_abs(self));
break;
case 0x8f:
{
- int rvalue = ZPG();
- BBS0(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbs(self, rvalue & 1, cpu_65c02_ea_rel(self));
}
break;
case 0x90:
- BCC(EA_REL());
+ cpu_65c02_bc(self, (1 << CPU_65C02_REG_P_BIT_C), cpu_65c02_ea_rel(self));
break;
case 0x91:
- STA(EA_ZPG_IND_IDX(Y));
+ cpu_65c02_st(self, self->regs.byte.a, cpu_65c02_ea_zpg_ind_idx(self, self->regs.byte.y));
break;
case 0x92:
- STA(EA_ZPG_IND());
+ cpu_65c02_st(self, self->regs.byte.a, cpu_65c02_ea_zpg_ind(self));
break;
case 0x93:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x94:
- STY(EA_ZPG_IDX(X));
+ cpu_65c02_st(self, self->regs.byte.y, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x));
break;
case 0x95:
- STA(EA_ZPG_IDX(X));
+ cpu_65c02_st(self, self->regs.byte.a, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x));
break;
case 0x96:
- STX(EA_ZPG_IDX(Y));
+ cpu_65c02_st(self, self->regs.byte.x, cpu_65c02_ea_zpg_idx(self, self->regs.byte.y));
break;
case 0x97:
- SMB1(EA_ZPG());
+ cpu_65c02_smb(self, 2, cpu_65c02_ea_zpg(self));
break;
case 0x98:
- TYA();
+ cpu_65c02_ld(self, EA_A, self->regs.byte.y);
break;
case 0x99:
- STA(EA_ABS_IDX(Y));
+ cpu_65c02_st(self, self->regs.byte.a, cpu_65c02_ea_abs_idx(self, self->regs.byte.y));
break;
case 0x9a:
- TXS();
+ cpu_65c02_st(self, self->regs.byte.x, EA_S);
break;
case 0x9b:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0x9c:
- STZ(EA_ABS());
+ cpu_65c02_st(self, 0, cpu_65c02_ea_abs(self));
break;
case 0x9d:
- STA(EA_ABS_IDX(X));
+ cpu_65c02_st(self, self->regs.byte.a, cpu_65c02_ea_abs_idx(self, self->regs.byte.x));
break;
case 0x9e:
- STZ(EA_ABS_IDX(X));
+ cpu_65c02_st(self, 0, cpu_65c02_ea_abs_idx(self, self->regs.byte.x));
break;
case 0x9f:
{
- int rvalue = ZPG();
- BBS1(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbs(self, rvalue & 2, cpu_65c02_ea_rel(self));
}
break;
case 0xa0:
- LDY(IMM());
+ cpu_65c02_ld(self, EA_Y, cpu_65c02_fb(self));
break;
case 0xa1:
- LDA(ZPG_IDX_IND(X));
+ cpu_65c02_ld(self, EA_A, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx_ind(self, self->regs.byte.x)));
break;
case 0xa2:
- LDX(IMM());
+ cpu_65c02_ld(self, EA_X, cpu_65c02_fb(self));
break;
case 0xa3:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xa4:
- LDY(ZPG());
+ cpu_65c02_ld(self, EA_Y, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0xa5:
- LDA(ZPG());
+ cpu_65c02_ld(self, EA_A, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0xa6:
- LDX(ZPG());
+ cpu_65c02_ld(self, EA_X, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0xa7:
- SMB2(EA_ZPG());
+ cpu_65c02_smb(self, 4, cpu_65c02_ea_zpg(self));
break;
case 0xa8:
- TAY();
+ cpu_65c02_ld(self, EA_Y, self->regs.byte.a);
break;
case 0xa9:
- LDA(IMM());
+ cpu_65c02_ld(self, EA_A, cpu_65c02_fb(self));
break;
case 0xaa:
- TAX();
+ cpu_65c02_ld(self, EA_X, self->regs.byte.a);
break;
case 0xab:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xac:
- LDY(ABS());
+ cpu_65c02_ld(self, EA_Y, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0xad:
- LDA(ABS());
+ cpu_65c02_ld(self, EA_A, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0xae:
- LDX(ABS());
+ cpu_65c02_ld(self, EA_X, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0xaf:
{
- int rvalue = ZPG();
- BBS2(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbs(self, rvalue & 4, cpu_65c02_ea_rel(self));
}
break;
case 0xb0:
- BCS(EA_REL());
+ cpu_65c02_bs(self, (1 << CPU_65C02_REG_P_BIT_C), cpu_65c02_ea_rel(self));
break;
case 0xb1:
- LDA(ZPG_IND_IDX(Y));
+ cpu_65c02_ld(self, EA_A, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind_idx(self, self->regs.byte.y)));
break;
case 0xb2:
- LDA(ZPG_IND());
+ cpu_65c02_ld(self, EA_A, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind(self)));
break;
case 0xb3:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xb4:
- LDY(ZPG_IDX(X));
+ cpu_65c02_ld(self, EA_Y, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x)));
break;
case 0xb5:
- LDA(ZPG_IDX(X));
+ cpu_65c02_ld(self, EA_A, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x)));
break;
case 0xb6:
- LDX(ZPG_IDX(Y));
+ cpu_65c02_ld(self, EA_X, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.y)));
break;
case 0xb7:
- SMB3(EA_ZPG());
+ cpu_65c02_smb(self, 8, cpu_65c02_ea_zpg(self));
break;
case 0xb8:
- CLV();
+ cpu_65c02_cl(self, (1 << CPU_65C02_REG_P_BIT_V));
break;
case 0xb9:
- LDA(ABS_IDX(Y));
+ cpu_65c02_ld(self, EA_A, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.y)));
break;
case 0xba:
- TSX();
+ cpu_65c02_ld(self, EA_X, self->regs.byte.s);
break;
case 0xbb:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xbc:
- LDY(ABS_IDX(X));
+ cpu_65c02_ld(self, EA_Y, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x)));
break;
case 0xbd:
- LDA(ABS_IDX(X));
+ cpu_65c02_ld(self, EA_A, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x)));
break;
case 0xbe:
- LDX(ABS_IDX(Y));
+ cpu_65c02_ld(self, EA_X, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.y)));
break;
case 0xbf:
{
- int rvalue = ZPG();
- BBS3(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbs(self, rvalue & 8, cpu_65c02_ea_rel(self));
}
break;
case 0xc0:
- CPY(IMM());
+ cpu_65c02_cmp(self, self->regs.byte.y, cpu_65c02_fb(self));
break;
case 0xc1:
- CMP(ZPG_IDX_IND(X));
+ cpu_65c02_cmp(self, self->regs.byte.a, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx_ind(self, self->regs.byte.x)));
break;
case 0xc2:
- ILL22();
+ cpu_65c02_ill22(self);
break;
case 0xc3:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xc4:
- CPY(ZPG());
+ cpu_65c02_cmp(self, self->regs.byte.y, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0xc5:
- CMP(ZPG());
+ cpu_65c02_cmp(self, self->regs.byte.a, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0xc6:
- DEC(EA_ZPG());
+ cpu_65c02_dec(self, cpu_65c02_ea_zpg(self));
break;
case 0xc7:
- SMB4(EA_ZPG());
+ cpu_65c02_smb(self, 0x10, cpu_65c02_ea_zpg(self));
break;
case 0xc8:
- INY();
+ cpu_65c02_inc(self, EA_Y);
break;
case 0xc9:
- CMP(IMM());
+ cpu_65c02_cmp(self, self->regs.byte.a, cpu_65c02_fb(self));
break;
case 0xca:
- DEX();
+ cpu_65c02_dec(self, EA_X);
break;
case 0xcb:
- WAI();
+ cpu_65c02_wai(self);
break;
case 0xcc:
- CPY(ABS());
+ cpu_65c02_cmp(self, self->regs.byte.y, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0xcd:
- CMP(ABS());
+ cpu_65c02_cmp(self, self->regs.byte.a, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0xce:
- DEC(EA_ABS());
+ cpu_65c02_dec(self, cpu_65c02_ea_abs(self));
break;
case 0xcf:
{
- int rvalue = ZPG();
- BBS4(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbs(self, rvalue & 0x10, cpu_65c02_ea_rel(self));
}
break;
case 0xd0:
- BNE(EA_REL());
+ cpu_65c02_bc(self, (1 << CPU_65C02_REG_P_BIT_Z), cpu_65c02_ea_rel(self));
break;
case 0xd1:
- CMP(ZPG_IND_IDX(Y));
+ cpu_65c02_cmp(self, self->regs.byte.a, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind_idx(self, self->regs.byte.y)));
break;
case 0xd2:
- CMP(ZPG_IND());
+ cpu_65c02_cmp(self, self->regs.byte.a, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind(self)));
break;
case 0xd3:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xd4:
- ILL24();
+ cpu_65c02_ill24(self);
break;
case 0xd5:
- CMP(ZPG_IDX(X));
+ cpu_65c02_cmp(self, self->regs.byte.a, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x)));
break;
case 0xd6:
- DEC(EA_ZPG_IDX(X));
+ cpu_65c02_dec(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x));
break;
case 0xd7:
- SMB5(EA_ZPG());
+ cpu_65c02_smb(self, 0x20, cpu_65c02_ea_zpg(self));
break;
case 0xd8:
- CLD();
+ cpu_65c02_cl(self, (1 << CPU_65C02_REG_P_BIT_D));
break;
case 0xd9:
- CMP(ABS_IDX(Y));
+ cpu_65c02_cmp(self, self->regs.byte.a, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.y)));
break;
case 0xda:
- PHX();
+ cpu_65c02_ph(self, self->regs.byte.x);
break;
case 0xdb:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xdc:
- ILL34();
+ cpu_65c02_ill34(self);
break;
case 0xdd:
- CMP(ABS_IDX(X));
+ cpu_65c02_cmp(self, self->regs.byte.a, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x)));
break;
case 0xde:
- DEC(EA_ABS_IDX(X));
+ cpu_65c02_dec(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x));
break;
case 0xdf:
{
- int rvalue = ZPG();
- BBS5(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbs(self, rvalue & 0x20, cpu_65c02_ea_rel(self));
}
break;
case 0xe0:
- CPX(IMM());
+ cpu_65c02_cmp(self, self->regs.byte.x, cpu_65c02_fb(self));
break;
case 0xe1:
- SBC(ZPG_IDX_IND(X));
+ cpu_65c02_sbc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx_ind(self, self->regs.byte.x)));
break;
case 0xe2:
- ILL22();
+ cpu_65c02_ill22(self);
break;
case 0xe3:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xe4:
- CPX(ZPG());
+ cpu_65c02_cmp(self, self->regs.byte.x, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0xe5:
- SBC(ZPG());
+ cpu_65c02_sbc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg(self)));
break;
case 0xe6:
- INC(EA_ZPG());
+ cpu_65c02_inc(self, cpu_65c02_ea_zpg(self));
break;
case 0xe7:
- SMB6(EA_ZPG());
+ cpu_65c02_smb(self, 0x40, cpu_65c02_ea_zpg(self));
break;
case 0xe8:
- INX();
+ cpu_65c02_inc(self, EA_X);
break;
case 0xe9:
- SBC(IMM());
+ cpu_65c02_sbc(self, cpu_65c02_fb(self));
break;
case 0xea:
- NOP();
+ cpu_65c02_nop(self);
break;
case 0xeb:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xec:
- CPX(ABS());
+ cpu_65c02_cmp(self, self->regs.byte.x, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0xed:
- SBC(ABS());
+ cpu_65c02_sbc(self, cpu_65c02_rb(self, cpu_65c02_ea_abs(self)));
break;
case 0xee:
- INC(EA_ABS());
+ cpu_65c02_inc(self, cpu_65c02_ea_abs(self));
break;
case 0xef:
{
- int rvalue = ZPG();
- BBS6(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbs(self, rvalue & 0x40, cpu_65c02_ea_rel(self));
}
break;
case 0xf0:
- BEQ(EA_REL());
+ cpu_65c02_bs(self, (1 << CPU_65C02_REG_P_BIT_Z), cpu_65c02_ea_rel(self));
break;
case 0xf1:
- SBC(ZPG_IND_IDX(Y));
+ cpu_65c02_sbc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind_idx(self, self->regs.byte.y)));
break;
case 0xf2:
- SBC(ZPG_IND());
+ cpu_65c02_sbc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_ind(self)));
break;
case 0xf3:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xf4:
- ILL24();
+ cpu_65c02_ill24(self);
break;
case 0xf5:
- SBC(ZPG_IDX(X));
+ cpu_65c02_sbc(self, cpu_65c02_rb(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x)));
break;
case 0xf6:
- INC(EA_ZPG_IDX(X));
+ cpu_65c02_inc(self, cpu_65c02_ea_zpg_idx(self, self->regs.byte.x));
break;
case 0xf7:
- SMB7(EA_ZPG());
+ cpu_65c02_smb(self, 0x80, cpu_65c02_ea_zpg(self));
break;
case 0xf8:
- SED();
+ cpu_65c02_se(self, (1 << CPU_65C02_REG_P_BIT_D));
break;
case 0xf9:
- SBC(ABS_IDX(Y));
+ cpu_65c02_sbc(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.y)));
break;
case 0xfa:
- PLX();
+ cpu_65c02_pl(self, EA_X);
break;
case 0xfb:
- ILL11();
+ cpu_65c02_ill11(self);
break;
case 0xfc:
- ILL34();
+ cpu_65c02_ill34(self);
break;
case 0xfd:
- SBC(ABS_IDX(X));
+ cpu_65c02_sbc(self, cpu_65c02_rb(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x)));
break;
case 0xfe:
- INC(EA_ABS_IDX(X));
+ cpu_65c02_inc(self, cpu_65c02_ea_abs_idx(self, self->regs.byte.x));
break;
case 0xff:
{
- int rvalue = ZPG();
- BBS7(rvalue, EA_REL());
+ int rvalue = cpu_65c02_rb(self, cpu_65c02_ea_zpg(self));
+ cpu_65c02_bbs(self, rvalue & 0x80, cpu_65c02_ea_rel(self));
}
break;
}
public / multi_emu.git / commitdiff