Split disassembly part of decode_z80.py into instr_z80.py via text file

diff --git a/decode_z80.py b/decode_z80.py
index 3a2db5b..1771a95 100755 (executable)
--- a/decode_z80.py
+++ b/decode_z80.py
@@ -1,6 +1,5 @@
 #!/usr/bin/env python3
 
-import z80dis.z80
 import sys
 
 # for these opcodes, the last operand is rvalue (any other is lvalue)
@@ -216,68 +215,74 @@ cb_opcodes = {
 }
 
 prefixes = [[], [0xcb], [0xdd], [0xdd, 0xcb], [0xed], [0xfd], [0xfd, 0xcb]]
-for i in range(0x700):
-  if (i & 0xff) == 0:
-    print(
-      'void cpu_z80_execute{0:s}(struct cpu_z80 *self) {{'.format(
-        ''.join([f'_{j:02x}' for j in prefixes[i >> 8]])
-      )
+for i in prefixes:
+  line = sys.stdin.readline().strip()
+  assert line == 'opcodes{0:s}'.format(''.join([f' 0x{j:02x}' for j in i]))
+
+  print(
+    'void cpu_z80_execute{0:s}(struct cpu_z80 *self) {{'.format(
+      ''.join([f'_{j:02x}' for j in i])
     )
-    print('  switch (cpu_z80_fetch_byte(self)) {')
-  print(f'  case 0x{i & 0xff:02x}:')
-  opcodes = prefixes[i >> 8] + [i & 0xff]
-  if opcodes in prefixes:
-    print(
-      '    cpu_z80_execute{0:s}(self);'.format(
-        ''.join([f'_{j:02x}' for j in opcodes])
+  )
+  print('  switch (cpu_z80_fetch_byte(self)) {')
+
+  for j in range(0x100):
+    line = sys.stdin.readline().strip()
+
+    print(f'  case 0x{j:02x}:')
+    k = i + [j]
+    if k in prefixes:
+      print(
+        '    cpu_z80_execute{0:s}(self);'.format(
+          ''.join([f'_{k:02x}' for k in k])
+        )
       )
-    )
-  else:
-    instr = z80dis.z80.disasm(
-      # for DDCB and FDCB the displacement goes before the next opcode
-      bytes(opcodes[:2] + [0x12] + opcodes[2:] + [0x34])
-    ).lower().split()
-    if len(instr) == 0:
-      instr = ['ill']
-    elif len(instr) >= 2:
-      instr[1:] = [k for j in instr[1:] for k in j.split(',')]
-    if len(instr) >= 4: # the undocumented DDCB and FDCB variants
-      assert instr[0] == 'ld'
-      instr = instr[2:] + instr[1:2] # "ld a,op (ix+n)" to "op (ix+n),a"
-    #print('xxx', instr)
-    suffix = ''
-    if instr[0] not in byte_opcodes and instr[0] not in word_opcodes:
-      for j in instr[1:]:
-        if j in byte_operands:
-          assert suffix != '_word'
-          suffix = '_byte'
-        elif j in word_operands:
-          assert suffix != '_byte'
-          suffix = '_word'
-    j = len(instr) - int(instr[0] in rvalue_opcodes)
-    if suffix == '_byte' or instr[0] in byte_opcodes:
-      for k in range(1, j):
-        instr[k] = byte_lvalue_modes[instr[k]]
-      for k in range(j, len(instr)):
-        instr[k] = byte_rvalue_modes[instr[k]]
-    elif suffix == '_word' or instr[0] in word_opcodes:
-      for k in range(1, j):
-        instr[k] = word_lvalue_modes[instr[k]]
-      for k in range(j, len(instr)):
-        instr[k] = word_rvalue_modes[instr[k]]
-    if len(instr) < pred_opcodes.get(instr[0], 0):
-      instr[1:1] = ['true']
-    if len(instr) < cb_opcodes.get(instr[0], 0):
-      instr.append('CPU_Z80_EA_SINK')
-    print(
-      '    cpu_z80_{0:s}{1:s}(self{2:s});'.format(
-        instr[0],
-        suffix,
-        ''.join([', ' + j for j in instr[1:]])
+    else:
+      instr = line.lower().split()
+      if len(instr) == 0:
+        instr = ['ill']
+      elif len(instr) >= 2:
+        instr[1:] = [l for k in instr[1:] for l in k.split(',')]
+      if len(instr) >= 4: # the undocumented DDCB and FDCB variants
+        assert instr[0] == 'ld'
+        instr = instr[2:] + instr[1:2] # "ld a,op (ix+n)" to "op (ix+n),a"
+      #print('xxx', instr)
+      suffix = ''
+      if instr[0] not in byte_opcodes and instr[0] not in word_opcodes:
+        for k in instr[1:]:
+          if k in byte_operands:
+            assert suffix != '_word'
+            suffix = '_byte'
+          elif k in word_operands:
+            assert suffix != '_byte'
+            suffix = '_word'
+      k = len(instr) - int(instr[0] in rvalue_opcodes)
+      if suffix == '_byte' or instr[0] in byte_opcodes:
+        for l in range(1, k):
+          instr[l] = byte_lvalue_modes[instr[l]]
+        for l in range(k, len(instr)):
+          instr[l] = byte_rvalue_modes[instr[l]]
+      elif suffix == '_word' or instr[0] in word_opcodes:
+        for l in range(1, k):
+          instr[l] = word_lvalue_modes[instr[l]]
+        for l in range(k, len(instr)):
+          instr[l] = word_rvalue_modes[instr[l]]
+      if len(instr) < pred_opcodes.get(instr[0], 0):
+        instr[1:1] = ['true']
+      if len(instr) < cb_opcodes.get(instr[0], 0):
+        instr.append('CPU_Z80_EA_SINK')
+      print(
+        '    cpu_z80_{0:s}{1:s}(self{2:s});'.format(
+          instr[0],
+          suffix,
+          ''.join([', ' + k for k in instr[1:]])
+        )
       )
-    )
-  print('    break;')
-  if (i & 0xff) == 0xff:
-    print('  }')
-    print('}')
-    print()
+    print('    break;')
+
+  line = sys.stdin.readline().strip()
+  assert len(line) == 0
+
+  print('  }')
+  print('}')
+  print()

diff --git a/instr_z80.py b/instr_z80.py
new file mode 100755 (executable)
index 0000000..b9cc723
--- /dev/null
+++ b/instr_z80.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+
+import z80dis.z80
+
+prefixes = [[], [0xcb], [0xdd], [0xdd, 0xcb], [0xed], [0xfd], [0xfd, 0xcb]]
+for i in prefixes:
+  print('opcodes{0:s}'.format(''.join([f' 0x{j:02x}' for j in i])))
+  for j in range(0x100):
+    k = i + [j]
+    print(
+      z80dis.z80.disasm(
+        # for DDCB and FDCB the displacement goes before the next opcode
+        bytes(k[:2] + [0x12] + k[2:] + [0x34])
+      )
+    )
+  print()

diff --git a/instr_z80.txt b/instr_z80.txt
new file mode 100644 (file)
index 0000000..2039a78
--- /dev/null
+++ b/instr_z80.txt
@@ -0,0 +1,1806 @@
+opcodes
+NOP
+LD BC,0x3412
+LD (BC),A
+INC BC
+INC B
+DEC B
+LD B,0x12
+RLCA
+EX AF,AF'
+ADD HL,BC
+LD A,(BC)
+DEC BC
+INC C
+DEC C
+LD C,0x12
+RRCA
+DJNZ 0x0014
+LD DE,0x3412
+LD (DE),A
+INC DE
+INC D
+DEC D
+LD D,0x12
+RLA
+JR 0x0014
+ADD HL,DE
+LD A,(DE)
+DEC DE
+INC E
+DEC E
+LD E,0x12
+RRA
+JR nz,0x0014
+LD HL,0x3412
+LD (0x3412),HL
+INC HL
+INC H
+DEC H
+LD H,0x12
+DAA
+JR z,0x0014
+ADD HL,HL
+LD HL,(0x3412)
+DEC HL
+INC L
+DEC L
+LD L,0x12
+CPL
+JR nc,0x0014
+LD SP,0x3412
+LD (0x3412),A
+INC SP
+INC (HL)
+DEC (HL)
+LD (HL),0x12
+SCF
+JR c,0x0014
+ADD HL,SP
+LD A,(0x3412)
+DEC SP
+INC A
+DEC A
+LD A,0x12
+CCF
+LD B,B
+LD B,C
+LD B,D
+LD B,E
+LD B,H
+LD B,L
+LD B,(HL)
+LD B,A
+LD C,B
+LD C,C
+LD C,D
+LD C,E
+LD C,H
+LD C,L
+LD C,(HL)
+LD C,A
+LD D,B
+LD D,C
+LD D,D
+LD D,E
+LD D,H
+LD D,L
+LD D,(HL)
+LD D,A
+LD E,B
+LD E,C
+LD E,D
+LD E,E
+LD E,H
+LD E,L
+LD E,(HL)
+LD E,A
+LD H,B
+LD H,C
+LD H,D
+LD H,E
+LD H,H
+LD H,L
+LD H,(HL)
+LD H,A
+LD L,B
+LD L,C
+LD L,D
+LD L,E
+LD L,H
+LD L,L
+LD L,(HL)
+LD L,A
+LD (HL),B
+LD (HL),C
+LD (HL),D
+LD (HL),E
+LD (HL),H
+LD (HL),L
+HALT
+LD (HL),A
+LD A,B
+LD A,C
+LD A,D
+LD A,E
+LD A,H
+LD A,L
+LD A,(HL)
+LD A,A
+ADD A,B
+ADD A,C
+ADD A,D
+ADD A,E
+ADD A,H
+ADD A,L
+ADD A,(HL)
+ADD A,A
+ADC A,B
+ADC A,C
+ADC A,D
+ADC A,E
+ADC A,H
+ADC A,L
+ADC A,(HL)
+ADC A,A
+SUB B
+SUB C
+SUB D
+SUB E
+SUB H
+SUB L
+SUB (HL)
+SUB A
+SBC A,B
+SBC A,C
+SBC A,D
+SBC A,E
+SBC A,H
+SBC A,L
+SBC A,(HL)
+SBC A,A
+AND B
+AND C
+AND D
+AND E
+AND H
+AND L
+AND (HL)
+AND A
+XOR B
+XOR C
+XOR D
+XOR E
+XOR H
+XOR L
+XOR (HL)
+XOR A
+OR B
+OR C
+OR D
+OR E
+OR H
+OR L
+OR (HL)
+OR A
+CP B
+CP C
+CP D
+CP E
+CP H
+CP L
+CP (HL)
+CP A
+RET nz
+POP BC
+JP nz,0x3412
+JP 0x3412
+CALL nz,0x3412
+PUSH BC
+ADD A,0x12
+RST 0
+RET z
+RET
+JP z,0x3412
+RL D
+CALL z,0x3412
+CALL 0x3412
+ADC A,0x12
+RST 8
+RET nc
+POP DE
+JP nc,0x3412
+OUT (0x0012),A
+CALL nc,0x3412
+PUSH DE
+SUB 0x12
+RST 0x10
+RET c
+EXX
+JP c,0x3412
+IN A,(0x0012)
+CALL c,0x3412
+LD (DE),A
+SBC A,0x12
+RST 0x18
+RET po
+POP HL
+JP po,0x3412
+EX (SP),HL
+CALL po,0x3412
+PUSH HL
+AND 0x12
+RST 0x20
+RET pe
+JP (HL)
+JP pe,0x3412
+EX DE,HL
+CALL pe,0x3412
+
+XOR 0x12
+RST 0x28
+RET p
+POP AF
+JP p,0x3412
+DI
+CALL p,0x3412
+PUSH AF
+OR 0x12
+RST 0x30
+RET m
+LD SP,HL
+JP m,0x3412
+EI
+CALL m,0x3412
+LD (DE),A
+CP 0x12
+RST 0x38
+
+opcodes 0xcb
+RLC B
+RLC C
+RLC D
+RLC E
+RLC H
+RLC L
+RLC (HL)
+RLC A
+RRC B
+RRC C
+RRC D
+RRC E
+RRC H
+RRC L
+RRC (HL)
+RRC A
+RL B
+RL C
+RL D
+RL E
+RL H
+RL L
+RL (HL)
+RL A
+RR B
+RR C
+RR D
+RR E
+RR H
+RR L
+RR (HL)
+RR A
+SLA B
+SLA C
+SLA D
+SLA E
+SLA H
+SLA L
+SLA (HL)
+SLA A
+SRA B
+SRA C
+SRA D
+SRA E
+SRA H
+SRA L
+SRA (HL)
+SRA A
+SLL B
+SLL C
+SLL D
+SLL E
+SLL H
+SLL L
+SLL (HL)
+SLL A
+SRL B
+SRL C
+SRL D
+SRL E
+SRL H
+SRL L
+SRL (HL)
+SRL A
+BIT 0,B
+BIT 0,C
+BIT 0,D
+BIT 0,E
+BIT 0,H
+BIT 0,L
+BIT 0,(HL)
+BIT 0,A
+BIT 1,B
+BIT 1,C
+BIT 1,D
+BIT 1,E
+BIT 1,H
+BIT 1,L
+BIT 1,(HL)
+BIT 1,A
+BIT 2,B
+BIT 2,C
+BIT 2,D
+BIT 2,E
+BIT 2,H
+BIT 2,L
+BIT 2,(HL)
+BIT 2,A
+BIT 3,B
+BIT 3,C
+BIT 3,D
+BIT 3,E
+BIT 3,H
+BIT 3,L
+BIT 3,(HL)
+BIT 3,A
+BIT 4,B
+BIT 4,C
+BIT 4,D
+BIT 4,E
+BIT 4,H
+BIT 4,L
+BIT 4,(HL)
+BIT 4,A
+BIT 5,B
+BIT 5,C
+BIT 5,D
+BIT 5,E
+BIT 5,H
+BIT 5,L
+BIT 5,(HL)
+BIT 5,A
+BIT 6,B
+BIT 6,C
+BIT 6,D
+BIT 6,E
+BIT 6,H
+BIT 6,L
+BIT 6,(HL)
+BIT 6,A
+BIT 7,B
+BIT 7,C
+BIT 7,D
+BIT 7,E
+BIT 7,H
+BIT 7,L
+BIT 7,(HL)
+BIT 7,A
+RES 0,B
+RES 0,C
+RES 0,D
+RES 0,E
+RES 0,H
+RES 0,L
+RES 0,(HL)
+RES 0,A
+RES 1,B
+RES 1,C
+RES 1,D
+RES 1,E
+RES 1,H
+RES 1,L
+RES 1,(HL)
+RES 1,A
+RES 2,B
+RES 2,C
+RES 2,D
+RES 2,E
+RES 2,H
+RES 2,L
+RES 2,(HL)
+RES 2,A
+RES 3,B
+RES 3,C
+RES 3,D
+RES 3,E
+RES 3,H
+RES 3,L
+RES 3,(HL)
+RES 3,A
+RES 4,B
+RES 4,C
+RES 4,D
+RES 4,E
+RES 4,H
+RES 4,L
+RES 4,(HL)
+RES 4,A
+RES 5,B
+RES 5,C
+RES 5,D
+RES 5,E
+RES 5,H
+RES 5,L
+RES 5,(HL)
+RES 5,A
+RES 6,B
+RES 6,C
+RES 6,D
+RES 6,E
+RES 6,H
+RES 6,L
+RES 6,(HL)
+RES 6,A
+RES 7,B
+RES 7,C
+RES 7,D
+RES 7,E
+RES 7,H
+RES 7,L
+RES 7,(HL)
+RES 7,A
+SET 0,B
+SET 0,C
+SET 0,D
+SET 0,E
+SET 0,H
+SET 0,L
+SET 0,(HL)
+SET 0,A
+SET 1,B
+SET 1,C
+SET 1,D
+SET 1,E
+SET 1,H
+SET 1,L
+SET 1,(HL)
+SET 1,A
+SET 2,B
+SET 2,C
+SET 2,D
+SET 2,E
+SET 2,H
+SET 2,L
+SET 2,(HL)
+SET 2,A
+SET 3,B
+SET 3,C
+SET 3,D
+SET 3,E
+SET 3,H
+SET 3,L
+SET 3,(HL)
+SET 3,A
+SET 4,B
+SET 4,C
+SET 4,D
+SET 4,E
+SET 4,H
+SET 4,L
+SET 4,(HL)
+SET 4,A
+SET 5,B
+SET 5,C
+SET 5,D
+SET 5,E
+SET 5,H
+SET 5,L
+SET 5,(HL)
+SET 5,A
+SET 6,B
+SET 6,C
+SET 6,D
+SET 6,E
+SET 6,H
+SET 6,L
+SET 6,(HL)
+SET 6,A
+SET 7,B
+SET 7,C
+SET 7,D
+SET 7,E
+SET 7,H
+SET 7,L
+SET 7,(HL)
+SET 7,A
+
+opcodes 0xdd
+NOP
+LD BC,0x3412
+LD (BC),A
+INC BC
+INC B
+DEC B
+LD B,0x12
+RLCA
+EX AF,AF'
+ADD IX,BC
+LD A,(BC)
+DEC BC
+INC C
+DEC C
+LD C,0x12
+RRCA
+DJNZ 0x0015
+LD DE,0x3412
+LD (DE),A
+INC DE
+INC D
+DEC D
+LD D,0x12
+RLA
+JR 0x0015
+ADD IX,DE
+LD A,(DE)
+DEC DE
+INC E
+DEC E
+LD E,0x12
+RRA
+JR nz,0x0015
+LD IX,0x3412
+LD (0x3412),IX
+INC IX
+INC IXH
+DEC IXH
+LD IXH,0x12
+DAA
+JR z,0x0015
+ADD IX,IX
+LD IX,(0x3412)
+DEC IX
+INC IXL
+DEC IXL
+LD IXL,0x12
+CPL
+JR nc,0x0015
+LD SP,0x3412
+LD (0x3412),A
+INC SP
+INC (IX+0x12)
+DEC (IX+0x12)
+LD (IX+0x12),0x34
+SCF
+JR c,0x0015
+ADD IX,SP
+LD A,(0x3412)
+DEC SP
+INC A
+DEC A
+LD A,0x12
+CCF
+LD B,B
+LD B,C
+LD B,D
+LD B,E
+LD B,IXH
+LD B,IXL
+LD B,(IX+0x12)
+LD B,A
+LD C,B
+LD C,C
+LD C,D
+LD C,E
+LD C,IXH
+LD C,IXL
+LD C,(IX+0x12)
+LD C,A
+LD D,B
+LD D,C
+LD D,D
+LD D,E
+LD D,IXH
+LD D,IXL
+LD D,(IX+0x12)
+LD D,A
+LD E,B
+LD E,C
+LD E,D
+LD E,E
+LD E,IXH
+LD E,IXL
+LD E,(IX+0x12)
+LD E,A
+LD IXH,B
+LD IXH,C
+LD IXH,D
+LD IXH,E
+LD IXH,IXH
+LD IXH,IXL
+LD H,(IX+0x12)
+LD IXH,A
+LD IXL,B
+LD IXL,C
+LD IXL,D
+LD IXL,E
+LD IXL,IXH
+LD IXL,IXL
+LD L,(IX+0x12)
+LD IXL,A
+LD (IX+0x12),B
+LD (IX+0x12),C
+LD (IX+0x12),D
+LD (IX+0x12),E
+LD (IX+0x12),H
+LD (IX+0x12),L
+HALT
+LD (IX+0x12),A
+LD A,B
+LD A,C
+LD A,D
+LD A,E
+LD A,IXH
+LD A,IXL
+LD A,(IX+0x12)
+LD A,A
+ADD A,B
+ADD A,C
+ADD A,D
+ADD A,E
+ADD A,IXH
+ADD A,IXL
+ADD A,(IX+0x12)
+ADD A,A
+ADC A,B
+ADC A,C
+ADC A,D
+ADC A,E
+ADC A,IXH
+ADC A,IXL
+ADC A,(IX+0x12)
+ADC A,A
+SUB B
+SUB C
+SUB D
+SUB E
+SUB IXH
+SUB IXL
+SUB (IX+0x12)
+SUB A
+SBC A,B
+SBC A,C
+SBC A,D
+SBC A,E
+SBC A,IXH
+SBC A,IXL
+SBC A,(IX+0x12)
+SBC A,A
+AND B
+AND C
+AND D
+AND E
+AND IXH
+AND IXL
+AND (IX+0x12)
+AND A
+XOR B
+XOR C
+XOR D
+XOR E
+XOR IXH
+XOR IXL
+XOR (IX+0x12)
+XOR A
+OR B
+OR C
+OR D
+OR E
+OR IXH
+OR IXL
+OR (IX+0x12)
+OR A
+CP B
+CP C
+CP D
+CP E
+CP IXH
+CP IXL
+CP (IX+0x12)
+CP A
+RET nz
+POP BC
+JP nz,0x3412
+JP 0x3412
+CALL nz,0x3412
+PUSH BC
+ADD A,0x12
+RST 0
+RET z
+RET
+JP z,0x3412
+ld H,SLL (IX+0x12)
+CALL z,0x3412
+CALL 0x3412
+ADC A,0x12
+RST 8
+RET nc
+POP DE
+JP nc,0x3412
+OUT (0x0012),A
+CALL nc,0x3412
+PUSH DE
+SUB 0x12
+RST 0x10
+RET c
+EXX
+JP c,0x3412
+IN A,(0x0012)
+CALL c,0x3412
+
+SBC A,0x12
+RST 0x18
+RET po
+POP IX
+JP po,0x3412
+EX (SP),IX
+CALL po,0x3412
+PUSH IX
+AND 0x12
+RST 0x20
+RET pe
+JP (IX)
+JP pe,0x3412
+EX DE,HL
+CALL pe,0x3412
+
+XOR 0x12
+RST 0x28
+RET p
+POP AF
+JP p,0x3412
+DI
+CALL p,0x3412
+PUSH AF
+OR 0x12
+RST 0x30
+RET m
+LD SP,IX
+JP m,0x3412
+EI
+CALL m,0x3412
+
+CP 0x12
+RST 0x38
+
+opcodes 0xdd 0xcb
+ld B,RLC (IX+0x12)
+ld C,RLC (IX+0x12)
+ld D,RLC (IX+0x12)
+ld E,RLC (IX+0x12)
+ld H,RLC (IX+0x12)
+ld L,RLC (IX+0x12)
+RLC (IX+0x12)
+ld A,RLC (IX+0x12)
+ld B,RRC (IX+0x12)
+ld C,RRC (IX+0x12)
+ld D,RRC (IX+0x12)
+ld E,RRC (IX+0x12)
+ld H,RRC (IX+0x12)
+ld L,RRC (IX+0x12)
+RRC (IX+0x12)
+ld A,RRC (IX+0x12)
+ld B,RL (IX+0x12)
+ld C,RL (IX+0x12)
+ld D,RL (IX+0x12)
+ld E,RL (IX+0x12)
+ld H,RL (IX+0x12)
+ld L,RL (IX+0x12)
+RL (IX+0x12)
+ld A,RL (IX+0x12)
+ld B,RR (IX+0x12)
+ld C,RR (IX+0x12)
+ld D,RR (IX+0x12)
+ld E,RR (IX+0x12)
+ld H,RR (IX+0x12)
+ld L,RR (IX+0x12)
+RR (IX+0x12)
+ld A,RR (IX+0x12)
+ld B,SLA (IX+0x12)
+ld C,SLA (IX+0x12)
+ld D,SLA (IX+0x12)
+ld E,SLA (IX+0x12)
+ld H,SLA (IX+0x12)
+ld L,SLA (IX+0x12)
+SLA (IX+0x12)
+ld A,SLA (IX+0x12)
+ld B,SRA (IX+0x12)
+ld C,SRA (IX+0x12)
+ld D,SRA (IX+0x12)
+ld E,SRA (IX+0x12)
+ld H,SRA (IX+0x12)
+ld L,SRA (IX+0x12)
+SRA (IX+0x12)
+ld A,SRA (IX+0x12)
+ld B,SLL (IX+0x12)
+ld C,SLL (IX+0x12)
+ld D,SLL (IX+0x12)
+ld E,SLL (IX+0x12)
+ld H,SLL (IX+0x12)
+ld L,SLL (IX+0x12)
+SLL (IX+0x12)
+ld A,SLL (IX+0x12)
+ld B,SRL (IX+0x12)
+ld C,SRL (IX+0x12)
+ld D,SRL (IX+0x12)
+ld E,SRL (IX+0x12)
+ld H,SRL (IX+0x12)
+ld L,SRL (IX+0x12)
+SRL (IX+0x12)
+ld A,SRL (IX+0x12)
+BIT 0,(IX+0x12)
+BIT 0,(IX+0x12)
+BIT 0,(IX+0x12)
+BIT 0,(IX+0x12)
+BIT 0,(IX+0x12)
+BIT 0,(IX+0x12)
+BIT 0,(IX+0x12)
+BIT 0,(IX+0x12)
+BIT 1,(IX+0x12)
+BIT 1,(IX+0x12)
+BIT 1,(IX+0x12)
+BIT 1,(IX+0x12)
+BIT 1,(IX+0x12)
+BIT 1,(IX+0x12)
+BIT 1,(IX+0x12)
+BIT 1,(IX+0x12)
+BIT 2,(IX+0x12)
+BIT 2,(IX+0x12)
+BIT 2,(IX+0x12)
+BIT 2,(IX+0x12)
+BIT 2,(IX+0x12)
+BIT 2,(IX+0x12)
+BIT 2,(IX+0x12)
+BIT 2,(IX+0x12)
+BIT 3,(IX+0x12)
+BIT 3,(IX+0x12)
+BIT 3,(IX+0x12)
+BIT 3,(IX+0x12)
+BIT 3,(IX+0x12)
+BIT 3,(IX+0x12)
+BIT 3,(IX+0x12)
+BIT 3,(IX+0x12)
+BIT 4,(IX+0x12)
+BIT 4,(IX+0x12)
+BIT 4,(IX+0x12)
+BIT 4,(IX+0x12)
+BIT 4,(IX+0x12)
+BIT 4,(IX+0x12)
+BIT 4,(IX+0x12)
+BIT 4,(IX+0x12)
+BIT 5,(IX+0x12)
+BIT 5,(IX+0x12)
+BIT 5,(IX+0x12)
+BIT 5,(IX+0x12)
+BIT 5,(IX+0x12)
+BIT 5,(IX+0x12)
+BIT 5,(IX+0x12)
+BIT 5,(IX+0x12)
+BIT 6,(IX+0x12)
+BIT 6,(IX+0x12)
+BIT 6,(IX+0x12)
+BIT 6,(IX+0x12)
+BIT 6,(IX+0x12)
+BIT 6,(IX+0x12)
+BIT 6,(IX+0x12)
+BIT 6,(IX+0x12)
+BIT 7,(IX+0x12)
+BIT 7,(IX+0x12)
+BIT 7,(IX+0x12)
+BIT 7,(IX+0x12)
+BIT 7,(IX+0x12)
+BIT 7,(IX+0x12)
+BIT 7,(IX+0x12)
+BIT 7,(IX+0x12)
+ld B,RES 0,(IX+0x12)
+ld C,RES 0,(IX+0x12)
+ld D,RES 0,(IX+0x12)
+ld E,RES 0,(IX+0x12)
+ld H,RES 0,(IX+0x12)
+ld L,RES 0,(IX+0x12)
+RES 0,(IX+0x12)
+ld A,RES 0,(IX+0x12)
+ld B,RES 1,(IX+0x12)
+ld C,RES 1,(IX+0x12)
+ld D,RES 1,(IX+0x12)
+ld E,RES 1,(IX+0x12)
+ld H,RES 1,(IX+0x12)
+ld L,RES 1,(IX+0x12)
+RES 1,(IX+0x12)
+ld A,RES 1,(IX+0x12)
+ld B,RES 2,(IX+0x12)
+ld C,RES 2,(IX+0x12)
+ld D,RES 2,(IX+0x12)
+ld E,RES 2,(IX+0x12)
+ld H,RES 2,(IX+0x12)
+ld L,RES 2,(IX+0x12)
+RES 2,(IX+0x12)
+ld A,RES 2,(IX+0x12)
+ld B,RES 3,(IX+0x12)
+ld C,RES 3,(IX+0x12)
+ld D,RES 3,(IX+0x12)
+ld E,RES 3,(IX+0x12)
+ld H,RES 3,(IX+0x12)
+ld L,RES 3,(IX+0x12)
+RES 3,(IX+0x12)
+ld A,RES 3,(IX+0x12)
+ld B,RES 4,(IX+0x12)
+ld C,RES 4,(IX+0x12)
+ld D,RES 4,(IX+0x12)
+ld E,RES 4,(IX+0x12)
+ld H,RES 4,(IX+0x12)
+ld L,RES 4,(IX+0x12)
+RES 4,(IX+0x12)
+ld A,RES 4,(IX+0x12)
+ld B,RES 5,(IX+0x12)
+ld C,RES 5,(IX+0x12)
+ld D,RES 5,(IX+0x12)
+ld E,RES 5,(IX+0x12)
+ld H,RES 5,(IX+0x12)
+ld L,RES 5,(IX+0x12)
+RES 5,(IX+0x12)
+ld A,RES 5,(IX+0x12)
+ld B,RES 6,(IX+0x12)
+ld C,RES 6,(IX+0x12)
+ld D,RES 6,(IX+0x12)
+ld E,RES 6,(IX+0x12)
+ld H,RES 6,(IX+0x12)
+ld L,RES 6,(IX+0x12)
+RES 6,(IX+0x12)
+ld A,RES 6,(IX+0x12)
+ld B,RES 7,(IX+0x12)
+ld C,RES 7,(IX+0x12)
+ld D,RES 7,(IX+0x12)
+ld E,RES 7,(IX+0x12)
+ld H,RES 7,(IX+0x12)
+ld L,RES 7,(IX+0x12)
+RES 7,(IX+0x12)
+ld A,RES 7,(IX+0x12)
+ld B,SET 0,(IX+0x12)
+ld C,SET 0,(IX+0x12)
+ld D,SET 0,(IX+0x12)
+ld E,SET 0,(IX+0x12)
+ld H,SET 0,(IX+0x12)
+ld L,SET 0,(IX+0x12)
+SET 0,(IX+0x12)
+ld A,SET 0,(IX+0x12)
+ld B,SET 1,(IX+0x12)
+ld C,SET 1,(IX+0x12)
+ld D,SET 1,(IX+0x12)
+ld E,SET 1,(IX+0x12)
+ld H,SET 1,(IX+0x12)
+ld L,SET 1,(IX+0x12)
+SET 1,(IX+0x12)
+ld A,SET 1,(IX+0x12)
+ld B,SET 2,(IX+0x12)
+ld C,SET 2,(IX+0x12)
+ld D,SET 2,(IX+0x12)
+ld E,SET 2,(IX+0x12)
+ld H,SET 2,(IX+0x12)
+ld L,SET 2,(IX+0x12)
+SET 2,(IX+0x12)
+ld A,SET 2,(IX+0x12)
+ld B,SET 3,(IX+0x12)
+ld C,SET 3,(IX+0x12)
+ld D,SET 3,(IX+0x12)
+ld E,SET 3,(IX+0x12)
+ld H,SET 3,(IX+0x12)
+ld L,SET 3,(IX+0x12)
+SET 3,(IX+0x12)
+ld A,SET 3,(IX+0x12)
+ld B,SET 4,(IX+0x12)
+ld C,SET 4,(IX+0x12)
+ld D,SET 4,(IX+0x12)
+ld E,SET 4,(IX+0x12)
+ld H,SET 4,(IX+0x12)
+ld L,SET 4,(IX+0x12)
+SET 4,(IX+0x12)
+ld A,SET 4,(IX+0x12)
+ld B,SET 5,(IX+0x12)
+ld C,SET 5,(IX+0x12)
+ld D,SET 5,(IX+0x12)
+ld E,SET 5,(IX+0x12)
+ld H,SET 5,(IX+0x12)
+ld L,SET 5,(IX+0x12)
+SET 5,(IX+0x12)
+ld A,SET 5,(IX+0x12)
+ld B,SET 6,(IX+0x12)
+ld C,SET 6,(IX+0x12)
+ld D,SET 6,(IX+0x12)
+ld E,SET 6,(IX+0x12)
+ld H,SET 6,(IX+0x12)
+ld L,SET 6,(IX+0x12)
+SET 6,(IX+0x12)
+ld A,SET 6,(IX+0x12)
+ld B,SET 7,(IX+0x12)
+ld C,SET 7,(IX+0x12)
+ld D,SET 7,(IX+0x12)
+ld E,SET 7,(IX+0x12)
+ld H,SET 7,(IX+0x12)
+ld L,SET 7,(IX+0x12)
+SET 7,(IX+0x12)
+ld A,SET 7,(IX+0x12)
+
+opcodes 0xed
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+IN B,(C)
+OUT (C),B
+SBC HL,BC
+LD (0x3412),BC
+NEG
+RETN
+IM 0
+LD I,A
+IN C,(C)
+OUT (C),C
+ADC HL,BC
+LD BC,(0x3412)
+NEG
+RETI
+IM 0
+LD R,A
+IN D,(C)
+OUT (C),D
+SBC HL,DE
+LD (0x3412),DE
+NEG
+RETN
+IM 1
+LD A,I
+IN E,(C)
+OUT (C),E
+ADC HL,DE
+LD DE,(0x3412)
+NEG
+RETI
+IM 2
+LD A,R
+IN H,(C)
+OUT (C),H
+SBC HL,HL
+LD (0x3412),HL
+NEG
+RETN
+IM 0
+RRD
+IN L,(C)
+OUT (C),L
+ADC HL,HL
+LD HL,(0x3412)
+NEG
+RETI
+IM 0
+RLD
+IN F,(C)
+OUT (C),0
+SBC HL,SP
+LD (0x3412),SP
+NEG
+RETN
+IM 1
+NOP
+IN A,(C)
+OUT (C),A
+ADC HL,SP
+LD SP,(0x3412)
+NEG
+RETI
+IM 2
+NOP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+LDI
+CPI
+INI
+OUTI
+
+
+
+
+LDD
+CPD
+IND
+OUTD
+
+
+
+
+LDIR
+CPIR
+INIR
+OTIR
+
+
+
+
+LDDR
+CPDR
+INDR
+OTDR
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+opcodes 0xfd
+NOP
+LD BC,0x3412
+LD (BC),A
+INC BC
+INC B
+DEC B
+LD B,0x12
+RLCA
+EX AF,AF'
+ADD IY,BC
+LD A,(BC)
+DEC BC
+INC C
+DEC C
+LD C,0x12
+RRCA
+DJNZ 0x0015
+LD DE,0x3412
+LD (DE),A
+INC DE
+INC D
+DEC D
+LD D,0x12
+RLA
+JR 0x0015
+ADD IY,DE
+LD A,(DE)
+DEC DE
+INC E
+DEC E
+LD E,0x12
+RRA
+JR nz,0x0015
+LD IY,0x3412
+LD (0x3412),IY
+INC IY
+INC IYH
+DEC IYH
+LD IYH,0x12
+DAA
+JR z,0x0015
+ADD IY,IY
+LD IY,(0x3412)
+DEC IY
+INC IYL
+DEC IYL
+LD IYL,0x12
+CPL
+JR nc,0x0015
+LD SP,0x3412
+LD (0x3412),A
+INC SP
+INC (IY+0x12)
+DEC (IY+0x12)
+LD (IY+0x12),0x34
+SCF
+JR c,0x0015
+ADD IY,SP
+LD A,(0x3412)
+DEC SP
+INC A
+DEC A
+LD A,0x12
+CCF
+LD B,B
+LD B,C
+LD B,D
+LD B,E
+LD B,IYH
+LD B,IYL
+LD B,(IY+0x12)
+LD B,A
+LD C,B
+LD C,C
+LD C,D
+LD C,E
+LD C,IYH
+LD C,IYL
+LD C,(IY+0x12)
+LD C,A
+LD D,B
+LD D,C
+LD D,D
+LD D,E
+LD D,IYH
+LD D,IYL
+LD D,(IY+0x12)
+LD D,A
+LD E,B
+LD E,C
+LD E,D
+LD E,E
+LD E,IYH
+LD E,IYL
+LD E,(IY+0x12)
+LD E,A
+LD IYH,B
+LD IYH,C
+LD IYH,D
+LD IYH,E
+LD IYH,IYH
+LD IYH,IYL
+LD H,(IY+0x12)
+LD IYH,A
+LD IYL,B
+LD IYL,C
+LD IYL,D
+LD IYL,E
+LD IYL,IYH
+LD IYL,IYL
+LD L,(IY+0x12)
+LD IYL,A
+LD (IY+0x12),B
+LD (IY+0x12),C
+LD (IY+0x12),D
+LD (IY+0x12),E
+LD (IY+0x12),H
+LD (IY+0x12),L
+HALT
+LD (IY+0x12),A
+LD A,B
+LD A,C
+LD A,D
+LD A,E
+LD A,IYH
+LD A,IYL
+LD A,(IY+0x12)
+LD A,A
+ADD A,B
+ADD A,C
+ADD A,D
+ADD A,E
+ADD A,IYH
+ADD A,IYL
+ADD A,(IY+0x12)
+ADD A,A
+ADC A,B
+ADC A,C
+ADC A,D
+ADC A,E
+ADC A,IYH
+ADC A,IYL
+ADC A,(IY+0x12)
+ADC A,A
+SUB B
+SUB C
+SUB D
+SUB E
+SUB IYH
+SUB IYL
+SUB (IY+0x12)
+SUB A
+SBC A,B
+SBC A,C
+SBC A,D
+SBC A,E
+SBC A,IYH
+SBC A,IYL
+SBC A,(IY+0x12)
+SBC A,A
+AND B
+AND C
+AND D
+AND E
+AND IYH
+AND IYL
+AND (IY+0x12)
+AND A
+XOR B
+XOR C
+XOR D
+XOR E
+XOR IYH
+XOR IYL
+XOR (IY+0x12)
+XOR A
+OR B
+OR C
+OR D
+OR E
+OR IYH
+OR IYL
+OR (IY+0x12)
+OR A
+CP B
+CP C
+CP D
+CP E
+CP IYH
+CP IYL
+CP (IY+0x12)
+CP A
+RET nz
+POP BC
+JP nz,0x3412
+JP 0x3412
+CALL nz,0x3412
+PUSH BC
+ADD A,0x12
+RST 0
+RET z
+RET
+JP z,0x3412
+ld H,SLL (IY+0x12)
+CALL z,0x3412
+CALL 0x3412
+ADC A,0x12
+RST 8
+RET nc
+POP DE
+JP nc,0x3412
+OUT (0x0012),A
+CALL nc,0x3412
+PUSH DE
+SUB 0x12
+RST 0x10
+RET c
+EXX
+JP c,0x3412
+IN A,(0x0012)
+CALL c,0x3412
+
+SBC A,0x12
+RST 0x18
+RET po
+POP IY
+JP po,0x3412
+EX (SP),IY
+CALL po,0x3412
+PUSH IY
+AND 0x12
+RST 0x20
+RET pe
+JP (IY)
+JP pe,0x3412
+EX DE,HL
+CALL pe,0x3412
+
+XOR 0x12
+RST 0x28
+RET p
+POP AF
+JP p,0x3412
+DI
+CALL p,0x3412
+PUSH AF
+OR 0x12
+RST 0x30
+RET m
+LD SP,IY
+JP m,0x3412
+EI
+CALL m,0x3412
+
+CP 0x12
+RST 0x38
+
+opcodes 0xfd 0xcb
+ld B,RLC (IY+0x12)
+ld C,RLC (IY+0x12)
+ld D,RLC (IY+0x12)
+ld E,RLC (IY+0x12)
+ld H,RLC (IY+0x12)
+ld L,RLC (IY+0x12)
+RLC (IY+0x12)
+ld A,RLC (IY+0x12)
+ld B,RRC (IY+0x12)
+ld C,RRC (IY+0x12)
+ld D,RRC (IY+0x12)
+ld E,RRC (IY+0x12)
+ld H,RRC (IY+0x12)
+ld L,RRC (IY+0x12)
+RRC (IY+0x12)
+ld A,RRC (IY+0x12)
+ld B,RL (IY+0x12)
+ld C,RL (IY+0x12)
+ld D,RL (IY+0x12)
+ld E,RL (IY+0x12)
+ld H,RL (IY+0x12)
+ld L,RL (IY+0x12)
+RL (IY+0x12)
+ld A,RL (IY+0x12)
+ld B,RR (IY+0x12)
+ld C,RR (IY+0x12)
+ld D,RR (IY+0x12)
+ld E,RR (IY+0x12)
+ld H,RR (IY+0x12)
+ld L,RR (IY+0x12)
+RR (IY+0x12)
+ld A,RR (IY+0x12)
+ld B,SLA (IY+0x12)
+ld C,SLA (IY+0x12)
+ld D,SLA (IY+0x12)
+ld E,SLA (IY+0x12)
+ld H,SLA (IY+0x12)
+ld L,SLA (IY+0x12)
+SLA (IY+0x12)
+ld A,SLA (IY+0x12)
+ld B,SRA (IY+0x12)
+ld C,SRA (IY+0x12)
+ld D,SRA (IY+0x12)
+ld E,SRA (IY+0x12)
+ld H,SRA (IY+0x12)
+ld L,SRA (IY+0x12)
+SRA (IY+0x12)
+ld A,SRA (IY+0x12)
+ld B,SLL (IY+0x12)
+ld C,SLL (IY+0x12)
+ld D,SLL (IY+0x12)
+ld E,SLL (IY+0x12)
+ld H,SLL (IY+0x12)
+ld L,SLL (IY+0x12)
+SLL (IY+0x12)
+ld A,SLL (IY+0x12)
+ld B,SRL (IY+0x12)
+ld C,SRL (IY+0x12)
+ld D,SRL (IY+0x12)
+ld E,SRL (IY+0x12)
+ld H,SRL (IY+0x12)
+ld L,SRL (IY+0x12)
+SRL (IY+0x12)
+ld A,SRL (IY+0x12)
+BIT 0,(IY+0x12)
+BIT 0,(IY+0x12)
+BIT 0,(IY+0x12)
+BIT 0,(IY+0x12)
+BIT 0,(IY+0x12)
+BIT 0,(IY+0x12)
+BIT 0,(IY+0x12)
+BIT 0,(IY+0x12)
+BIT 1,(IY+0x12)
+BIT 1,(IY+0x12)
+BIT 1,(IY+0x12)
+BIT 1,(IY+0x12)
+BIT 1,(IY+0x12)
+BIT 1,(IY+0x12)
+BIT 1,(IY+0x12)
+BIT 1,(IY+0x12)
+BIT 2,(IY+0x12)
+BIT 2,(IY+0x12)
+BIT 2,(IY+0x12)
+BIT 2,(IY+0x12)
+BIT 2,(IY+0x12)
+BIT 2,(IY+0x12)
+BIT 2,(IY+0x12)
+BIT 2,(IY+0x12)
+BIT 3,(IY+0x12)
+BIT 3,(IY+0x12)
+BIT 3,(IY+0x12)
+BIT 3,(IY+0x12)
+BIT 3,(IY+0x12)
+BIT 3,(IY+0x12)
+BIT 3,(IY+0x12)
+BIT 3,(IY+0x12)
+BIT 4,(IY+0x12)
+BIT 4,(IY+0x12)
+BIT 4,(IY+0x12)
+BIT 4,(IY+0x12)
+BIT 4,(IY+0x12)
+BIT 4,(IY+0x12)
+BIT 4,(IY+0x12)
+BIT 4,(IY+0x12)
+BIT 5,(IY+0x12)
+BIT 5,(IY+0x12)
+BIT 5,(IY+0x12)
+BIT 5,(IY+0x12)
+BIT 5,(IY+0x12)
+BIT 5,(IY+0x12)
+BIT 5,(IY+0x12)
+BIT 5,(IY+0x12)
+BIT 6,(IY+0x12)
+BIT 6,(IY+0x12)
+BIT 6,(IY+0x12)
+BIT 6,(IY+0x12)
+BIT 6,(IY+0x12)
+BIT 6,(IY+0x12)
+BIT 6,(IY+0x12)
+BIT 6,(IY+0x12)
+BIT 7,(IY+0x12)
+BIT 7,(IY+0x12)
+BIT 7,(IY+0x12)
+BIT 7,(IY+0x12)
+BIT 7,(IY+0x12)
+BIT 7,(IY+0x12)
+BIT 7,(IY+0x12)
+BIT 7,(IY+0x12)
+ld B,RES 0,(IY+0x12)
+ld C,RES 0,(IY+0x12)
+ld D,RES 0,(IY+0x12)
+ld E,RES 0,(IY+0x12)
+ld H,RES 0,(IY+0x12)
+ld L,RES 0,(IY+0x12)
+RES 0,(IY+0x12)
+ld A,RES 0,(IY+0x12)
+ld B,RES 1,(IY+0x12)
+ld C,RES 1,(IY+0x12)
+ld D,RES 1,(IY+0x12)
+ld E,RES 1,(IY+0x12)
+ld H,RES 1,(IY+0x12)
+ld L,RES 1,(IY+0x12)
+RES 1,(IY+0x12)
+ld A,RES 1,(IY+0x12)
+ld B,RES 2,(IY+0x12)
+ld C,RES 2,(IY+0x12)
+ld D,RES 2,(IY+0x12)
+ld E,RES 2,(IY+0x12)
+ld H,RES 2,(IY+0x12)
+ld L,RES 2,(IY+0x12)
+RES 2,(IY+0x12)
+ld A,RES 2,(IY+0x12)
+ld B,RES 3,(IY+0x12)
+ld C,RES 3,(IY+0x12)
+ld D,RES 3,(IY+0x12)
+ld E,RES 3,(IY+0x12)
+ld H,RES 3,(IY+0x12)
+ld L,RES 3,(IY+0x12)
+RES 3,(IY+0x12)
+ld A,RES 3,(IY+0x12)
+ld B,RES 4,(IY+0x12)
+ld C,RES 4,(IY+0x12)
+ld D,RES 4,(IY+0x12)
+ld E,RES 4,(IY+0x12)
+ld H,RES 4,(IY+0x12)
+ld L,RES 4,(IY+0x12)
+RES 4,(IY+0x12)
+ld A,RES 4,(IY+0x12)
+ld B,RES 5,(IY+0x12)
+ld C,RES 5,(IY+0x12)
+ld D,RES 5,(IY+0x12)
+ld E,RES 5,(IY+0x12)
+ld H,RES 5,(IY+0x12)
+ld L,RES 5,(IY+0x12)
+RES 5,(IY+0x12)
+ld A,RES 5,(IY+0x12)
+ld B,RES 6,(IY+0x12)
+ld C,RES 6,(IY+0x12)
+ld D,RES 6,(IY+0x12)
+ld E,RES 6,(IY+0x12)
+ld H,RES 6,(IY+0x12)
+ld L,RES 6,(IY+0x12)
+RES 6,(IY+0x12)
+ld A,RES 6,(IY+0x12)
+ld B,RES 7,(IY+0x12)
+ld C,RES 7,(IY+0x12)
+ld D,RES 7,(IY+0x12)
+ld E,RES 7,(IY+0x12)
+ld H,RES 7,(IY+0x12)
+ld L,RES 7,(IY+0x12)
+RES 7,(IY+0x12)
+ld A,RES 7,(IY+0x12)
+ld B,SET 0,(IY+0x12)
+ld C,SET 0,(IY+0x12)
+ld D,SET 0,(IY+0x12)
+ld E,SET 0,(IY+0x12)
+ld H,SET 0,(IY+0x12)
+ld L,SET 0,(IY+0x12)
+SET 0,(IY+0x12)
+ld A,SET 0,(IY+0x12)
+ld B,SET 1,(IY+0x12)
+ld C,SET 1,(IY+0x12)
+ld D,SET 1,(IY+0x12)
+ld E,SET 1,(IY+0x12)
+ld H,SET 1,(IY+0x12)
+ld L,SET 1,(IY+0x12)
+SET 1,(IY+0x12)
+ld A,SET 1,(IY+0x12)
+ld B,SET 2,(IY+0x12)
+ld C,SET 2,(IY+0x12)
+ld D,SET 2,(IY+0x12)
+ld E,SET 2,(IY+0x12)
+ld H,SET 2,(IY+0x12)
+ld L,SET 2,(IY+0x12)
+SET 2,(IY+0x12)
+ld A,SET 2,(IY+0x12)
+ld B,SET 3,(IY+0x12)
+ld C,SET 3,(IY+0x12)
+ld D,SET 3,(IY+0x12)
+ld E,SET 3,(IY+0x12)
+ld H,SET 3,(IY+0x12)
+ld L,SET 3,(IY+0x12)
+SET 3,(IY+0x12)
+ld A,SET 3,(IY+0x12)
+ld B,SET 4,(IY+0x12)
+ld C,SET 4,(IY+0x12)
+ld D,SET 4,(IY+0x12)
+ld E,SET 4,(IY+0x12)
+ld H,SET 4,(IY+0x12)
+ld L,SET 4,(IY+0x12)
+SET 4,(IY+0x12)
+ld A,SET 4,(IY+0x12)
+ld B,SET 5,(IY+0x12)
+ld C,SET 5,(IY+0x12)
+ld D,SET 5,(IY+0x12)
+ld E,SET 5,(IY+0x12)
+ld H,SET 5,(IY+0x12)
+ld L,SET 5,(IY+0x12)
+SET 5,(IY+0x12)
+ld A,SET 5,(IY+0x12)
+ld B,SET 6,(IY+0x12)
+ld C,SET 6,(IY+0x12)
+ld D,SET 6,(IY+0x12)
+ld E,SET 6,(IY+0x12)
+ld H,SET 6,(IY+0x12)
+ld L,SET 6,(IY+0x12)
+SET 6,(IY+0x12)
+ld A,SET 6,(IY+0x12)
+ld B,SET 7,(IY+0x12)
+ld C,SET 7,(IY+0x12)
+ld D,SET 7,(IY+0x12)
+ld E,SET 7,(IY+0x12)
+ld H,SET 7,(IY+0x12)
+ld L,SET 7,(IY+0x12)
+SET 7,(IY+0x12)
+ld A,SET 7,(IY+0x12)
+