--- /dev/null
+; USART registers\r
+USART_DATA: EQU 00h\r
+USART_CMD: EQU 01h\r
+\r
+START: LXI H,0C000h\r
+ SPHL\r
+ CALL USART_INIT\r
+\r
+; write a banner\r
+ MVI A,38h ; '8'\r
+ MOV C,A\r
+ CALL USART_OUT\r
+ MVI A,30h ; '0'\r
+ MOV C,A\r
+ CALL USART_OUT\r
+ MVI A,38h ; '8'\r
+ MOV C,A\r
+ CALL USART_OUT\r
+ MVI A,35h ; '5'\r
+ MOV C,A\r
+ CALL USART_OUT\r
+ MVI A,0Dh ; CR\r
+ MOV C,A\r
+ CALL USART_OUT\r
+ MVI A,0Ah ; LF\r
+ MOV C,A\r
+ CALL USART_OUT\r
+\r
+LOOP: CALL USART_IN\r
+ MOV C,A\r
+ CALL USART_OUT\r
+ JMP LOOP\r
+\r
+USART_INIT: MVI A,00h\r
+; Set USART to command mode - configure sync operation, write two dummy sync characters\r
+ OUT USART_CMD\r
+ OUT USART_CMD\r
+ OUT USART_CMD\r
+; Issue reset command\r
+ MVI A,40h\r
+ OUT USART_CMD\r
+; Write mode instruction - 1 stop bit, no parity, 8 bits, divide clock by 16\r
+ MVI A,4Eh\r
+ OUT USART_CMD\r
+; Write command instruction - activate RTS, reset error flags, enable RX, activate DTR, enable TX\r
+ MVI A,37h\r
+ OUT USART_CMD\r
+; Clear the data register\r
+ IN USART_DATA\r
+ RET\r
+\r
+; Read character from USART\r
+USART_IN: IN USART_CMD ; Read USART status\r
+ ANI 02h ; Test RxRdy bit\r
+ JZ USART_IN ; Wait for the data\r
+ IN USART_DATA ; Read character\r
+ RET\r
+\r
+; Write character to USART\r
+USART_OUT: IN USART_CMD\r
+ ANI 01h ; Test TxRdy\r
+ JZ USART_OUT ; Wait until USART is ready to transmit\r
+ MOV A,C\r
+ OUT USART_DATA ; Write character\r
+ RET\r