SPLD: Add fusemap without watchdog

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>

diff --git a/SPLD/easy_z80.chp b/SPLD/easy_z80_no_wdog.chp
similarity index 100%
rename from SPLD/easy_z80.chp
rename to SPLD/easy_z80_no_wdog.chp

diff --git a/SPLD/easy_z80_no_wdog.fus b/SPLD/easy_z80_no_wdog.fus
new file mode 100644 (file)
index 0000000..13b7ce6
--- /dev/null
+++ b/SPLD/easy_z80_no_wdog.fus
@@ -0,0 +1,82 @@
+
+
+Pin 19 = RAMCSI       XOR = 0   AC1 = 0
+  0  ---x ---- ---- --x- ---- ---- ---- ---- xxxx xxxx xxxx
+  1  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+  2  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+  3  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+  4  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+  5  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- ----
+  6  x--- ---- ---- ---- ---- ---- xxxx xxxx xxxx xxxx xxxx
+  7  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+
+Pin 18 = WDOG         XOR = 1   AC1 = 0
+  8  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+  9  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 10  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 11  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 12  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 13  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 14  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 15  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+
+Pin 17 = MA19         XOR = 0   AC1 = 1
+ 16  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 17  xxxx xxxx xxxx xxxx xxxx -x-- -x-- x--- x--- x--- x---
+ 18  x--- x--x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 19  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 20  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 21  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 22  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 23  xxxx xxxx xxxx -x-- -x-- x--- -x-- x--- x--- x--- x--x
+
+Pin 16 = PGENWR       XOR = 0   AC1 = 0
+ 24  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 25  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 26  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 27  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 28  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 29  xxxx ---x ---- ---- ---x ---- ---- ---- ---- xxxx xxxx
+ 30  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 31  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+
+Pin 15 = PAGEWR       XOR = 0   AC1 = 0
+ 32  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 33  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 34  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -x--
+ 35  ---- x--- -x-- -x-- -x-- -x-- -xx- xxxx xxxx xxxx xxxx
+ 36  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 37  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 38  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 39  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+
+Pin 14 = ROMCS        XOR = 0   AC1 = 0
+ 40  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -x-- ---- x---
+ 41  -x-- -x-- -x-- x--- -x-x xxxx xxxx xxxx xxxx xxxx xxxx
+ 42  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 43  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 44  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 45  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 46  xxxx xxxx xxxx xxxx xxxx xxxx ---- ---- ---- ---- ----
+ 47  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+
+Pin 13 = SIOCS        XOR = 0   AC1 = 0
+ 48  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 49  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 50  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 51  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 52  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 53  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 54  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 55  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+
+Pin 12 = CTCCS        XOR = 0   AC1 = 0
+ 56  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 57  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 58  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 59  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 60  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 61  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 62  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 63  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
+

diff --git a/SPLD/easy_z80_no_wdog.jed b/SPLD/easy_z80_no_wdog.jed
new file mode 100644 (file)
index 0000000..9828b05
--- /dev/null
+++ b/SPLD/easy_z80_no_wdog.jed
@@ -0,0 +1,24 @@
+\ 2\r
+Used Program:   GALasm 2.1\r
+GAL-Assembler:  GALasm 2.1\r
+Device:         GAL16V8\r
+\r
+*F0\r
+*G0\r
+*QF2194\r
+*L0000 11101111111111011111111111111111\r
+*L0256 11111111011111111111111111111111\r
+*L0768 10111011011101110111011101110110\r
+*L1024 10111011011110110111011101110110\r
+*L1280 11101111111111101111111111111111\r
+*L1536 10111111011110111011101110111001\r
+*L1792 10111111011110111011101101111010\r
+*L2048 01000000\r
+*L2056 0100010101000001010100110101100101011111010110100011100000110000\r
+*L2120 00100000\r
+*L2128 1111111111111111111111111111111111111111111111111111111111111111\r
+*L2192 1\r
+*L2193 0\r
+*C23cf\r
+*\r
+\ 37333\r

diff --git a/SPLD/easy_z80.pin b/SPLD/easy_z80_no_wdog.pin
similarity index 100%
rename from SPLD/easy_z80.pin
rename to SPLD/easy_z80_no_wdog.pin

diff --git a/SPLD/easy_z80_no_wdog.pld b/SPLD/easy_z80_no_wdog.pld
new file mode 100644 (file)
index 0000000..4877124
--- /dev/null
+++ b/SPLD/easy_z80_no_wdog.pld
@@ -0,0 +1,38 @@
+GAL16V8    ;  Works with GAL16V8B and ATF16V8B
+EASY_Z80   ;  Easy Z80
+
+MREQ   IORQ    WR      M1      A2      A3      A4      A5      A6      GND
+A7     CTCCS   SIOCS   ROMCS   PAGEWR  PGENWR  MA19    WDOG    RAMCSI  VCC
+
+/ROMCS  = /MREQ * /MA19
+
+/RAMCSI = /MREQ *  MA19
+
+/CTCCS  = /IORQ * M1 * /A7 * /A6 *  A5 * /A4 * /A3 * /A2
+
+/SIOCS  = /IORQ * M1 *  A7 * /A6 * /A5 * /A4 * /A3 * /A2
+
+/PAGEWR = /IORQ * M1 * /A7 *  A6 *  A5 *  A4 *  A3 * /A2 * /WR 
+
+/PGENWR = /IORQ * M1 * /A7 *  A6 *  A5 *  A4 *  A3 *  A2 * /WR 
+
+WDOG    = M1
+
+DESCRIPTION
+
+This is the address decode logic for Easy Z80 single board.
+It implements the following functions:
+1. ROM chip select - ROMCS. This signal is activated for memory accesses to
+   0x00000 - 0x7FFFF address range
+2. RAM chip select - RAMCSI. This signal is activated for memory accesses to
+   0x80000 - 0xFFFFF address range
+3. CTC chip select - CTCCS. This signal is activated for I/O accesses to
+   ports in 0x20-0x23 range
+4. SIO chip select - SIOCS. This signal is activated for I/O accesses to
+   ports in 0x80-0x83 range
+5. Page register write - PAGEWR. This signal is activated by I/O writes
+   to the ports in 0x78-0x7B range
+6. Page enable register write - PGEN. This signal is activated by I/O writes
+   to the ports in 0x7C-0x7F range
+7. Watchdog signal - WDOG. This signal mirrors CPU /M1 signal, and therefore it is pulsed on every instruction fetch cycle
+

diff --git a/SPLD/easy_z80_wdog.chp b/SPLD/easy_z80_wdog.chp
new file mode 100644 (file)
index 0000000..b99d557
--- /dev/null
+++ b/SPLD/easy_z80_wdog.chp
@@ -0,0 +1,25 @@
+
+
+                                GAL16V8
+
+                          -------\___/-------
+                     MREQ |  1           20 | VCC
+                          |                 |
+                     IORQ |  2           19 | RAMCSI
+                          |                 |
+                       WR |  3           18 | WDOG
+                          |                 |
+                       M1 |  4           17 | MA19
+                          |                 |
+                       A2 |  5           16 | PGENWR
+                          |                 |
+                       A3 |  6           15 | PAGEWR
+                          |                 |
+                       A4 |  7           14 | ROMCS
+                          |                 |
+                       A5 |  8           13 | SIOCS
+                          |                 |
+                       A6 |  9           12 | CTCCS
+                          |                 |
+                      GND | 10           11 | A7
+                          -------------------

diff --git a/SPLD/easy_z80.fus b/SPLD/easy_z80_wdog.fus
similarity index 100%
rename from SPLD/easy_z80.fus
rename to SPLD/easy_z80_wdog.fus

diff --git a/SPLD/easy_z80.jed b/SPLD/easy_z80_wdog.jed
similarity index 100%
rename from SPLD/easy_z80.jed
rename to SPLD/easy_z80_wdog.jed

diff --git a/SPLD/easy_z80_wdog.pin b/SPLD/easy_z80_wdog.pin
new file mode 100644 (file)
index 0000000..b82f7ba
--- /dev/null
+++ b/SPLD/easy_z80_wdog.pin
@@ -0,0 +1,25 @@
+
+
+ Pin # | Name     | Pin Type
+-----------------------------
+   1   | MREQ     | Input
+   2   | IORQ     | Input
+   3   | WR       | Input
+   4   | M1       | Input
+   5   | A2       | Input
+   6   | A3       | Input
+   7   | A4       | Input
+   8   | A5       | Input
+   9   | A6       | Input
+  10   | GND      | GND
+  11   | A7       | Input
+  12   | CTCCS    | Output
+  13   | SIOCS    | Output
+  14   | ROMCS    | Output
+  15   | PAGEWR   | Output
+  16   | PGENWR   | Output
+  17   | MA19     | Input
+  18   | WDOG     | Output
+  19   | RAMCSI   | Output
+  20   | VCC      | VCC
+

diff --git a/SPLD/easy_z80.pld b/SPLD/easy_z80_wdog.pld
similarity index 100%
rename from SPLD/easy_z80.pld
rename to SPLD/easy_z80_wdog.pld