SPLD: Move CTC to 0x88-0x8B

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>

diff --git a/SPLD/easy_z80_no_wdog.fus b/SPLD/easy_z80_no_wdog.fus
index 25188d5..659e69c 100644 (file)
--- a/SPLD/easy_z80_no_wdog.fus
+++ b/SPLD/easy_z80_no_wdog.fus
@@ -1,7 +1,7 @@
 
 
 Pin 19 = CTCCS        XOR = 0   AC1 = 0
-  0  -x-- ---- x--- -x-- -x-- -x-- x--- -x-x xxxx xxxx xxxx
+  0  -x-- ---- x--- -x-- x--- -x-- -x-- -xx- xxxx xxxx xxxx
   1  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
   2  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
   3  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

diff --git a/SPLD/easy_z80_no_wdog.jed b/SPLD/easy_z80_no_wdog.jed
index 4f19d37..685151c 100644 (file)
--- a/SPLD/easy_z80_no_wdog.jed
+++ b/SPLD/easy_z80_no_wdog.jed
@@ -6,7 +6,7 @@ Device:         GAL16V8
 *F0\r
 *G0\r
 *QF2194\r
-*L0000 10111111011110111011101101111010\r
+*L0000 10111111011110110111101110111001\r
 *L0256 10111111011110111011101110111001\r
 *L0512 11101111111111111110111111111111\r
 *L0768 10111011011110110111011101110110\r
@@ -19,6 +19,6 @@ Device:         GAL16V8
 *L2128 1111111111111111111111111111111111111111111111111111111111111111\r
 *L2192 1\r
 *L2193 0\r
-*C24dd\r
+*C251d\r
 *\r
-\ 37330\r
+\ 372fe\r

diff --git a/SPLD/easy_z80_no_wdog.pld b/SPLD/easy_z80_no_wdog.pld
index 822bd51..434d55f 100644 (file)
--- a/SPLD/easy_z80_no_wdog.pld
+++ b/SPLD/easy_z80_no_wdog.pld
@@ -8,7 +8,7 @@ A7      RAMCSI  WDOG    MA19    PGENWR  PAGEWR  ROMCS   SIOCS   CTCCS   VCC
 
 /RAMCSI = /MREQ *  MA19
 
-/CTCCS  = /IORQ * M1 * /A7 * /A6 *  A5 * /A4 * /A3 * /A2
+/CTCCS  = /IORQ * M1 *  A7 * /A6 * /A5 * /A4 *  A3 * /A2
 
 /SIOCS  = /IORQ * M1 *  A7 * /A6 * /A5 * /A4 * /A3 * /A2
 
@@ -27,12 +27,13 @@ It implements the following functions:
 2. RAM chip select - RAMCSI. This signal is activated for memory accesses to
    0x80000 - 0xFFFFF address range
 3. CTC chip select - CTCCS. This signal is activated for I/O accesses to
-   ports in 0x20-0x23 range
+   ports in 0x88-0x8B range
 4. SIO chip select - SIOCS. This signal is activated for I/O accesses to
    ports in 0x80-0x83 range
 5. Page register write - PAGEWR. This signal is activated by I/O writes
    to the ports in 0x78-0x7B range
 6. Page enable register write - PGEN. This signal is activated by I/O writes
    to the ports in 0x7C-0x7F range
-7. Watchdog signal - WDOG. This signal mirrors CPU /M1 signal, and therefore it is pulsed on every instruction fetch cycle
+7. Watchdog signal - WDOG. This signal mirrors CPU /M1 signal, and therefore
+   it is pulsed on every instruction fetch cycle
 

diff --git a/SPLD/easy_z80_wdog.fus b/SPLD/easy_z80_wdog.fus
index 3813626..63712f7 100644 (file)
--- a/SPLD/easy_z80_wdog.fus
+++ b/SPLD/easy_z80_wdog.fus
@@ -1,7 +1,7 @@
 
 
 Pin 19 = CTCCS        XOR = 0   AC1 = 0
-  0  -x-- ---- x--- -x-- -x-- -x-- x--- -x-x xxxx xxxx xxxx
+  0  -x-- ---- x--- -x-- x--- -x-- -x-- -xx- xxxx xxxx xxxx
   1  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
   2  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
   3  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

diff --git a/SPLD/easy_z80_wdog.jed b/SPLD/easy_z80_wdog.jed
index 7299328..b996b2c 100644 (file)
--- a/SPLD/easy_z80_wdog.jed
+++ b/SPLD/easy_z80_wdog.jed
@@ -6,7 +6,7 @@ Device:         GAL16V8
 *F0\r
 *G0\r
 *QF2194\r
-*L0000 10111111011110111011101101111010\r
+*L0000 10111111011110110111101110111001\r
 *L0256 10111111011110111011101110111001\r
 *L0512 11101111111111111110111111111111\r
 *L0768 10111011011110110111011101110110\r
@@ -19,6 +19,6 @@ Device:         GAL16V8
 *L2128 1111111111111111111111111111111111111111111111111111111111111111\r
 *L2192 1\r
 *L2193 0\r
-*C23f9\r
+*C2439\r
 *\r
-\ 372fe\r
+\ 372cc\r

diff --git a/SPLD/easy_z80_wdog.pld b/SPLD/easy_z80_wdog.pld
index e9152a4..29e5095 100644 (file)
--- a/SPLD/easy_z80_wdog.pld
+++ b/SPLD/easy_z80_wdog.pld
@@ -8,7 +8,7 @@ A7      RAMCSI  WDOG    MA19    PGENWR  PAGEWR  ROMCS   SIOCS   CTCCS   VCC
 
 /RAMCSI = /MREQ *  MA19
 
-/CTCCS  = /IORQ * M1 * /A7 * /A6 *  A5 * /A4 * /A3 * /A2
+/CTCCS  = /IORQ * M1 *  A7 * /A6 * /A5 * /A4 *  A3 * /A2
 
 /SIOCS  = /IORQ * M1 *  A7 * /A6 * /A5 * /A4 * /A3 * /A2
 
@@ -27,7 +27,7 @@ It implements the following functions:
 2. RAM chip select - RAMCSI. This signal is activated for memory accesses to
    0x80000 - 0xFFFFF address range
 3. CTC chip select - CTCCS. This signal is activated for I/O accesses to
-   ports in 0x20-0x23 range
+   ports in 0x88-0x8B range
 4. SIO chip select - SIOCS. This signal is activated for I/O accesses to
    ports in 0x80-0x83 range
 5. Page register write - PAGEWR. This signal is activated by I/O writes