*.o
/asxmak/linux/build/aslink
+/asxmak/linux/build/aspdp11
/asxmak/linux/build/asz80
/asxmak/linux/exe/aslink
+/asxmak/linux/exe/aspdp11
/asxmak/linux/exe/asz80
--- /dev/null
+/* pdp11.h */\r
+\r
+/*\r
+ * Copyright (C) 2003-2014 Alan R. Baldwin\r
+ *\r
+ * This program is free software: you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation, either version 3 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.\r
+ *\r
+ *\r
+ * Alan R. Baldwin\r
+ * 721 Berkeley St.\r
+ * Kent, Ohio 44240\r
+ */\r
+\r
+/*)BUILD\r
+ $(PROGRAM) = ASPDP11\r
+ $(INCLUDE) = {\r
+ ASXXXX.H\r
+ PDP11.H\r
+ }\r
+ $(FILES) = {\r
+ PDP11MCH.C\r
+ PDP11ADR.C\r
+ PDP11PST.C\r
+ ASMAIN.C\r
+ ASDBG.C\r
+ ASLEX.C\r
+ ASSYM.C\r
+ ASSUBR.C\r
+ ASEXPR.C\r
+ ASDATA.C\r
+ ASLIST.C\r
+ ASOUT.C\r
+ }\r
+ $(STACK) = 3000\r
+*/\r
+\r
+/*\r
+ * Addressing types\r
+ */\r
+\r
+/* modifier to "or" onto one of the below */\r
+#define S_IND 010\r
+\r
+#define S_REG 000\r
+#define S_INC 020\r
+#define S_DEC 040\r
+#define S_IDX 060\r
+\r
+/* shorthand for 7 | S_INC, or (pc)+ */\r
+#define S_IMM 027\r
+\r
+/* shorthand for 7 | S_IND | S_INC, or *(pc)+ */\r
+#define S_SYM 037\r
+\r
+/*\r
+ * PDP11 Instruction types\r
+ */\r
+#define S_ABS 50\r
+#define S_BRANCH 51\r
+#define S_DOUBLE 52\r
+#define S_FLOP 53\r
+#define S_JBR 54\r
+#define S_JCOND 55\r
+#define S_JSR 56\r
+#define S_MOVF 57\r
+#define S_MOVFO 58\r
+#define S_MULDIV 59\r
+#define S__REG 60\r
+#define S_RTS 61\r
+#define S_SINGLE 62\r
+#define S_SOB 63\r
+#define S_SYSTRAP 63\r
+\r
+/*\r
+ * Extended Addressing Modes\r
+ */\r
+//#define R_JXX 0x0100 /* 10-Bit Jump Addressing Mode */\r
+\r
+/*\r
+ * Variables\r
+ */\r
+extern int aindx;\r
+\r
+struct adsym\r
+{\r
+ char a_str[4]; /* addressing string */\r
+ int a_val; /* addressing mode value */\r
+};\r
+\r
+extern struct adsym reg[];\r
+\r
+\r
+ /* machine dependent functions */\r
+\r
+#ifdef OTHERSYSTEM\r
+ \r
+ /* pdp11adr.c */\r
+extern int addr(struct expr *esp, int indirect);\r
+extern int admode(struct adsym *sp);\r
+extern int any(int c, char *str);\r
+extern int srch(char *str);\r
+\r
+ /* pdp11mch.c */\r
+extern VOID machine(struct mne *mp);\r
+extern int abstype(struct expr *esp);\r
+extern int mchpcr(struct expr *esp);\r
+extern VOID minit(void);\r
+\r
+#else\r
+\r
+ /* pdp11adr.c */\r
+extern int addr();\r
+extern int admode();\r
+extern int any();\r
+extern int srch();\r
+\r
+ /* pdp11mch.c */\r
+extern VOID machine();\r
+extern int abstype();\r
+extern int mchpcr();\r
+extern VOID minit();\r
+\r
+#endif\r
+\r
--- /dev/null
+/* pdp11adr.c */\r
+\r
+/*\r
+ * Copyright (C) 2003-2014 Alan R. Baldwin\r
+ *\r
+ * This program is free software: you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation, either version 3 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.\r
+ *\r
+ *\r
+ * Alan R. Baldwin\r
+ * 721 Berkeley St.\r
+ * Kent, Ohio 44240\r
+ */\r
+\r
+#include "asxxxx.h"\r
+#include "pdp11.h"\r
+\r
+int aindx;\r
+\r
+int\r
+addr(esp, indirect)\r
+struct expr *esp;\r
+int indirect;\r
+{\r
+ int c, d;\r
+ char *ips, *ipd, *ptr;\r
+\r
+ aindx = 0;\r
+ ips = ip;\r
+\r
+ /* Rn */\r
+ if (admode(reg)) {\r
+ esp->e_mode = indirect | S_REG;\r
+ } else\r
+ /* #N */\r
+ if ((c = getnb()) == '#') {\r
+ expr(esp, 0);\r
+ esp->e_mode = indirect | S_IMM;\r
+ } else\r
+ /* *addr */\r
+ if (c == '*') {\r
+ if (indirect) {\r
+ aerr();\r
+ } else {\r
+ addr(esp, S_IND);\r
+ }\r
+ } else\r
+ /* (Rn) / (Rn)+ */\r
+ if ((c == '(') && admode(reg) && (getnb() == ')')) {\r
+ if ((d = getnb()) == '+') {\r
+ esp->e_mode = indirect | S_INC;\r
+ } else {\r
+ unget(d);\r
+ if (indirect) {\r
+ aerr();\r
+ }\r
+ else {\r
+ esp->e_mode = S_REG | S_IND;\r
+ }\r
+ }\r
+ } else {\r
+ /* -(Rn) */\r
+ if (c == '-') {\r
+ if (((d = getnb()) == '(') && admode(reg) && (getnb() == ')')) {\r
+ esp->e_mode = indirect | S_DEC;\r
+ goto done;\r
+ }\r
+ unget(d);\r
+ }\r
+\r
+ ip = ips;\r
+ /*\r
+ * Find next argument seperator or EOL\r
+ *\r
+ * lbl1: mne arg1(Rn) [; comment]\r
+ * lbl2: mne arg1(Rn) , arg2 [; comment]\r
+ * lbl3: mne arg1 , arg2(Rn) [; comment]\r
+ * lbl4: mne arg1(Rn) , arg2(Rn) [; comment]\r
+ */\r
+ while ((c = *ip++) != 0) {\r
+ if ((c == ',') || (c == ';')) {\r
+ break;\r
+ }\r
+ }\r
+ /*\r
+ * ip is at seperator:\r
+ *\r
+ * 1 - save seperator position\r
+ * 2 - save seperator character\r
+ * 3 - set EOL at seperator\r
+ */\r
+ ipd = ip - 1;\r
+ d = *ipd;\r
+ *ipd = 0;\r
+\r
+ /*\r
+ * scan for (Rn) in this argument\r
+ */\r
+ ip = ips;\r
+ ptr = strrchr(ip, '(');\r
+ *ipd = d;\r
+\r
+ if (ptr != NULL) {\r
+ ip = ptr;\r
+ if ((getnb() == '(') && admode(reg) && (getnb() == ')')) {\r
+ /*\r
+ * (Rn) found:\r
+ *\r
+ * 1 - save ip position\r
+ * 2 - set EOL at '(' of (Rn)\r
+ * 3 - evaluate from beginning\r
+ */\r
+ ipd = ip;\r
+ *ptr = 0;\r
+ ip = ips;\r
+ /*\r
+ * evaluate X of X(Rn)\r
+ */\r
+ expr(esp, 0);\r
+ esp->e_mode = indirect | S_IDX;\r
+ /*\r
+ * after evaluation:\r
+ *\r
+ * 1 - restore ip position\r
+ * 2 - restore '(' of (Rn)\r
+ */\r
+ ip = ipd;\r
+ *ptr = '(';\r
+ } else {\r
+ /*\r
+ * (Rn) not found,\r
+ * assume regular argument of form (...)\r
+ */\r
+ ip = ips;\r
+ expr(esp, 0);\r
+ esp->e_mode = S_SYM;\r
+ }\r
+ } else {\r
+ /*\r
+ * regular argument\r
+ */\r
+ expr(esp, 0);\r
+ esp->e_mode = S_SYM;\r
+ }\r
+ }\r
+done:\r
+ return (esp->e_mode);\r
+}\r
+\r
+/*\r
+ * Enter admode() to search a specific addressing mode table\r
+ * for a match. Return (1) for a match, (0) for no match.\r
+ * 'aindx' contains the value of the addressing mode.\r
+ */\r
+int\r
+admode(sp)\r
+struct adsym *sp;\r
+{\r
+ char *ptr;\r
+ int i;\r
+ char *ips;\r
+\r
+ ips = ip;\r
+ unget(getnb());\r
+\r
+ i = 0;\r
+ while ( *(ptr = &sp[i].a_str[0]) ) {\r
+ if (srch(ptr)) {\r
+ aindx = sp[i].a_val;\r
+ return(1);\r
+ }\r
+ i++;\r
+ }\r
+ ip = ips;\r
+ return(0);\r
+}\r
+\r
+/*\r
+ * srch --- does string match ?\r
+ */\r
+int\r
+srch(str)\r
+char *str;\r
+{\r
+ char *ptr;\r
+ ptr = ip;\r
+\r
+ while (*ptr && *str) {\r
+ if (ccase[*ptr & 0x007F] != ccase[*str & 0x007F])\r
+ break;\r
+ ptr++;\r
+ str++;\r
+ }\r
+ if (ccase[*ptr & 0x007F] == ccase[*str & 0x007F]) {\r
+ ip = ptr;\r
+ return(1);\r
+ }\r
+\r
+ if (!*str)\r
+ if (any(*ptr," \t\n,+);")) {\r
+ ip = ptr;\r
+ return(1);\r
+ }\r
+ return(0);\r
+}\r
+\r
+/*\r
+ * any --- does str contain c?\r
+ */\r
+int\r
+any(c,str)\r
+int c;\r
+char *str;\r
+{\r
+ while (*str)\r
+ if(*str++ == c)\r
+ return(1);\r
+ return(0);\r
+}\r
+\r
+struct adsym reg[] = { /* any register */\r
+ { "r0", 0x00 },\r
+ { "r1", 0x01 },\r
+ { "r2", 0x02 },\r
+ { "r3", 0x03 },\r
+ { "r4", 0x04 },\r
+ { "r5", 0x05 },\r
+ { "sp", 0x06 },\r
+ { "pc", 0x07 },\r
+ { "fr0", 0x08 },\r
+ { "fr1", 0x09 },\r
+ { "fr2", 0x0a },\r
+ { "fr3", 0x0b },\r
+ { "fr4", 0x0c },\r
+ { "fr5", 0x0d },\r
+ { "", 0x00 }\r
+};\r
+\r
+\r
--- /dev/null
+/* pdp11mch.c */\r
+\r
+/*\r
+ * Copyright (C) 2003-2014 Alan R. Baldwin\r
+ *\r
+ * This program is free software: you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation, either version 3 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.\r
+ *\r
+ *\r
+ * Alan R. Baldwin\r
+ * 721 Berkeley St.\r
+ * Kent, Ohio 44240\r
+ */\r
+\r
+#include "asxxxx.h"\r
+#include "pdp11.h"\r
+\r
+char *cpu = "Digital Equipment Corp PDP11";\r
+char *dsft = "asm";\r
+\r
+/*\r
+ * Opcode Cycle Definitions\r
+ */\r
+#define OPCY_SDP ((char) (0xFF))\r
+#define OPCY_ERR ((char) (0xFE))\r
+\r
+/* OPCY_NONE ((char) (0x80)) */\r
+/* OPCY_MASK ((char) (0x7F)) */\r
+\r
+#define UN ((char) (OPCY_NONE | 0x00))\r
+\r
+#define OPCY_PC ((char) (0x40))\r
+\r
+/*\r
+ * Process a machine op.\r
+ */\r
+VOID\r
+machine(mp)\r
+struct mne *mp;\r
+{\r
+ int op;\r
+ int rf;\r
+ struct expr e1, e2;\r
+ int t1, t2, v1, v2;\r
+\r
+ clrexpr(&e1);\r
+ clrexpr(&e2);\r
+\r
+ /*\r
+ * Instructions on a Word Boundary\r
+ */\r
+ if (dot.s_addr & 0x0001) {\r
+ outall();\r
+ err('b');\r
+ dot.s_addr += 1;\r
+ }\r
+\r
+ op = (int) mp->m_valu;\r
+ switch (rf = mp->m_type) {\r
+\r
+#if 0\r
+ case S_DOP:\r
+ case S_BRA:\r
+ t1 = addr(&e1);\r
+ v1 = (aindx & 0x000F) << 8;\r
+ t2 = 0;\r
+ v2 = 0;\r
+ switch (rf) {\r
+ case S_DOP:\r
+ /*\r
+ * Special Constant Processing\r
+ */\r
+ if ((t1 == S_IMM) && is_abs(&e1)) {\r
+ switch (e1.e_addr) {\r
+ case (a_uint) 4: t1 = S_REG; op += 0x0020; v1 = 2 << 8; break;\r
+ case (a_uint) 8: t1 = S_REG; op += 0x0030; v1 = 2 << 8; break;\r
+ case (a_uint) 0: t1 = S_REG; op += 0x0000; v1 = 3 << 8; break;\r
+ case (a_uint) 1: t1 = S_REG; op += 0x0010; v1 = 3 << 8; break;\r
+ case (a_uint) 2: t1 = S_REG; op += 0x0020; v1 = 3 << 8; break;\r
+ case (a_uint) ~0: t1 = S_REG; op += 0x0030; v1 = 3 << 8; break;\r
+ default: break;\r
+ }\r
+ }\r
+ comma(1); t2 = addr(&e2); v2 = (aindx & 0x000F); break;\r
+ case S_BRA: t2 = S_REG; v2 = 0; break;\r
+ default: break;\r
+ }\r
+\r
+ /*\r
+ * Opcode Processing\r
+ */\r
+ /* DOPSRC */\r
+ switch(t1) {\r
+ case S_REG: op += 0x0000 + v1; break; /* Rn As=0 */\r
+ case S_RIDX: op += 0x0010 + v1; break; /* X(Rn) As=1 */\r
+ case S_SYM: op += 0x0010; break; /* addr As=1, Sreg=PC */\r
+ case S_ABS: op += 0x0210; break; /* &Addr As=1, Sreg=SR */\r
+ case S_RIN: op += 0x0020 + v1; break; /* @Rn As=2 */\r
+ case S_RIN2: op += 0x0030 + v1; break; /* @Rn+ As=3 */\r
+ case S_IMM: op += 0x0030; break; /* #N As=3, Sreg=PC */\r
+ default: aerr(); break;\r
+ }\r
+\r
+ /* DOPDST */\r
+ switch(t2) {\r
+ case S_REG: op += 0x0000 + v2; break; /* Rn Ad=0 */\r
+ case S_RIDX: op += 0x0080 + v2; break; /* X(Rn) Ad=1 */\r
+ case S_SYM: op += 0x0080; break; /* addr Ad=1, Sreg=PC */\r
+ case S_IMM: /* #N ==>> &Addr */\r
+ case S_ABS: op += 0x0082; break; /* &Addr Ad=1, Sreg=SR */\r
+ case S_RIN: op += 0x0080 + v2; break; /* @Rn Ad=1 */\r
+ case S_RIN2: op += 0x0080 + v2; break; /* @Rn+ Ad=1 */\r
+ default: aerr(); break;\r
+ }\r
+\r
+ outaw(op);\r
+ /*\r
+ * Source Processing\r
+ */\r
+ switch(t1) {\r
+ case S_REG: break; /* Rn As=0 */\r
+ case S_RIDX: outrw(&e1, 0); break; /* X(Rn) As=1 */\r
+ case S_SYM: if (mchpcr(&e1)) {\r
+ e1.e_addr -= dot.s_addr;\r
+ outaw(e1.e_addr);\r
+ } else {\r
+ outrw(&e1, R_PCR0);\r
+ }\r
+ break; /* addr As=1, Sreg=PC */\r
+ case S_ABS: outrw(&e1, 0); break; /* &Addr As=1, Sreg=SR */\r
+ case S_RIN: break; /* @Rn As=2 */\r
+ case S_RIN2: break; /* @Rn+ As=3 */\r
+ case S_IMM: outrw(&e1, 0); break; /* #N As=3, Sreg=PC */\r
+ default: aerr(); break;\r
+ }\r
+ /*\r
+ * Destination Processing\r
+ */\r
+ switch(t2) {\r
+ case S_REG: break; /* Rn Ad=0 */\r
+ case S_RIDX: outrw(&e2, 0); break; /* X(Rn) Ad=1 */\r
+ case S_SYM: if (mchpcr(&e2)) {\r
+ e2.e_addr -= dot.s_addr;\r
+ outaw(e2.e_addr);\r
+ } else {\r
+ outrw(&e2, R_PCR0);\r
+ }\r
+ break; /* addr Ad=1, Sreg=PC */\r
+ case S_IMM: aerr(); /* #N ==>> &Addr */\r
+ case S_ABS: outrw(&e2, 0); break; /* &Addr Ad=1, Sreg=SR */\r
+ case S_RIN: outaw(0); break; /* @Rn Ad=1 */\r
+ case S_RIN2: /* @Rn+ Ad=1 */\r
+ if (rf == S_RLX) {\r
+ if (op & 0x0040) {\r
+ outaw(~0); /* RLX.b @Rn+,-1(Rn) */\r
+ } else {\r
+ outaw(~1); /* RLX.w @Rn+,-2(Rn) */\r
+ }\r
+ } else {\r
+ outaw(0);\r
+ if ((op & 0x0040) && (v2 != 0)) {\r
+ outaw(0x5310 + v2); /* add #1,Rn */\r
+ } else {\r
+ outaw(0x5320 + v2); /* add #2,Rn */\r
+ }\r
+ }\r
+ break;\r
+ default: aerr(); break;\r
+ }\r
+ break;\r
+\r
+ case S_SOP:\r
+ t1 = addr(&e1);\r
+ v1 = aindx & 0x000F;\r
+\r
+ /*\r
+ * Opcode Processing\r
+ */\r
+ /* SRCDST */\r
+ switch(t1) {\r
+ case S_REG: op += 0x0000 + v1; break; /* Rn As=0 */\r
+ case S_RIDX: op += 0x0010 + v1; break; /* X(Rn) As=1 */\r
+ case S_SYM: op += 0x0010; break; /* addr As=1, Sreg=PC */\r
+ case S_IMM: /* #N ==>> &Addr */\r
+ case S_ABS: op += 0x0210; break; /* &Addr As=1, Sreg=SR */\r
+ case S_RIN: op += 0x0020 + v1; break; /* @Rn As=2 */\r
+ case S_RIN2: op += 0x0030 + v1; break; /* @Rn+ As=3 */\r
+ default: aerr(); break;\r
+ }\r
+\r
+ outaw(op);\r
+ /*\r
+ * Source/Destination Processing\r
+ */\r
+ switch(t1) {\r
+ case S_REG: break; /* Rn As=0 */\r
+ case S_RIDX: outrw(&e1, 0); break; /* X(Rn) As=1 */\r
+ case S_SYM: if (mchpcr(&e1)) {\r
+ e1.e_addr -= dot.s_addr;\r
+ outaw(e1.e_addr);\r
+ } else {\r
+ outrw(&e1, R_PCR0);\r
+ }\r
+ break; /* addr As=1, Sreg=PC */\r
+ case S_IMM: aerr(); /* #N ==>> &Addr */\r
+ case S_ABS: outrw(&e1, 0); break; /* &Addr As=1, Sreg=SR */\r
+ case S_RIN: break; /* @Rn As=2 */\r
+ case S_RIN2: break; /* @Rn+ As=3 */\r
+ default: aerr(); break;\r
+ }\r
+ break;\r
+\r
+ case S_PSH:\r
+ t1 = addr(&e1);\r
+ v1 = aindx & 0x000F;\r
+\r
+ /*\r
+ * Special Constant Processing\r
+ */\r
+ if ((t1 == S_IMM) && is_abs(&e1)) {\r
+ switch (e1.e_addr) {\r
+ case (a_uint) 4: t1 = S_REG; op += 0x0020; v1 = 2; break;\r
+ case (a_uint) 8: t1 = S_REG; op += 0x0030; v1 = 2; break;\r
+ case (a_uint) 0: t1 = S_REG; op += 0x0000; v1 = 3; break;\r
+ case (a_uint) 1: t1 = S_REG; op += 0x0010; v1 = 3; break;\r
+ case (a_uint) 2: t1 = S_REG; op += 0x0020; v1 = 3; break;\r
+ case (a_uint) ~0: t1 = S_REG; op += 0x0030; v1 = 3; break;\r
+ default: break;\r
+ }\r
+ }\r
+\r
+ /*\r
+ * Opcode Processing\r
+ */\r
+ /* SRC */\r
+ switch(t1) {\r
+ case S_REG: op += 0x0000 + v1; break; /* Rn As=0 */\r
+ case S_RIDX: op += 0x0010 + v1; break; /* X(Rn) As=1 */\r
+ case S_SYM: op += 0x0010; break; /* addr As=1, Sreg=PC */\r
+ case S_ABS: op += 0x0210; break; /* &Addr As=1, Sreg=SR */\r
+ case S_RIN: op += 0x0020 + v1; break; /* @Rn As=2 */\r
+ case S_RIN2: op += 0x0030 + v1; break; /* @Rn+ As=3 */\r
+ case S_IMM: op += 0x0030; break; /* #N As=3, Sreg=PC */\r
+ default: aerr(); break;\r
+ }\r
+\r
+ outaw(op);\r
+ /*\r
+ * Source Processing\r
+ */\r
+ switch(t1) {\r
+ case S_REG: break; /* Rn As=0 */\r
+ case S_RIDX: outrw(&e1, 0); break; /* X(Rn) As=1 */\r
+ case S_SYM: if (mchpcr(&e1)) {\r
+ e1.e_addr -= dot.s_addr;\r
+ outaw(e1.e_addr);\r
+ } else {\r
+ outrw(&e1, R_PCR0);\r
+ }\r
+ break; /* addr As=1, Sreg=PC */\r
+ case S_ABS: outrw(&e1, 0); break; /* &Addr As=1, Sreg=SR */\r
+ case S_RIN: break; /* @Rn As=2 */\r
+ case S_RIN2: break; /* @Rn+ As=3 */\r
+ case S_IMM: outrw(&e1, 0); break; /* #N As=3, Sreg=PC */\r
+ default: aerr(); break;\r
+ }\r
+ break;\r
+\r
+ case S_DST:\r
+ t1 = addr(&e1);\r
+ v1 = (aindx & 0x000F);\r
+\r
+ /*\r
+ * Opcode Processing\r
+ */\r
+ /* DSTDST */\r
+ switch(t1) {\r
+ case S_REG: op += 0x0000 + v1; break; /* Rn Ad=0 */\r
+ case S_RIDX: op += 0x0080 + v1; break; /* X(Rn) Ad=1 */\r
+ case S_SYM: op += 0x0080; break; /* addr Ad=1, Sreg=PC */\r
+ case S_IMM: /* #N ==>> &Addr */\r
+ case S_ABS: op += 0x0082; break; /* &Addr Ad=1, Sreg=SR */\r
+ case S_RIN: op += 0x0080 + v1; break; /* @Rn Ad=1 */\r
+ case S_RIN2: op += 0x0080 + v1; break; /* @Rn+ Ad=1 */\r
+ default: aerr(); break;\r
+ }\r
+\r
+ outaw(op);\r
+ /*\r
+ * Destination Processing\r
+ */\r
+ switch(t1) {\r
+ case S_REG: break; /* Rn Ad=0 */\r
+ case S_RIDX: outrw(&e1, 0); break; /* X(Rn) Ad=1 */\r
+ case S_SYM: if (mchpcr(&e1)) {\r
+ e1.e_addr -= dot.s_addr;\r
+ outaw(e1.e_addr);\r
+ } else {\r
+ outrw(&e1, R_PCR0);\r
+ }\r
+ break; /* addr Ad=1, Sreg=PC */\r
+ case S_IMM: aerr(); /* #N ==>> &Addr */\r
+ case S_ABS: outrw(&e1, 0); break; /* &Addr Ad=1, Sreg=SR */\r
+ case S_RIN: outaw(0); break; /* @Rn Ad=1 */\r
+ case S_RIN2: outaw(0); /* @Rn+ Ad=1 */\r
+ if ((op & 0x0040) && (v1 != 0)) {\r
+ outaw(0x5310 + v1); /* add #1,Rn */\r
+ } else {\r
+ outaw(0x5320 + v1); ; /* add #2,Rn */\r
+ }\r
+ break;\r
+ default: aerr(); break;\r
+ }\r
+ break;\r
+\r
+ case S_RLX:\r
+ t1 = addr(&e1);\r
+ v1 = (aindx & 0x000F) << 8;\r
+\r
+ /*\r
+ * Duplicate Argument\r
+ */\r
+ e2.e_mode = e1.e_mode;\r
+ e2.e_flag = e1.e_flag;\r
+ e2.e_addr = e1.e_addr;\r
+ e2.e_base.e_sp = e1.e_base.e_sp;\r
+ e2.e_rlcf = e1.e_rlcf;\r
+\r
+ t2 = t1;\r
+ v2 = (aindx & 0x000F);\r
+\r
+ /*\r
+ * Opcode Processing\r
+ */\r
+ /* DOPSRC */\r
+ switch(t1) {\r
+ case S_REG: op += 0x0000 + v1; break; /* Rn As=0 */\r
+ case S_RIDX: op += 0x0010 + v1; break; /* X(Rn) As=1 */\r
+ case S_SYM: op += 0x0010; break; /* addr As=1, Sreg=PC */\r
+ case S_IMM: /* #N ==>> &Addr */\r
+ case S_ABS: op += 0x0210; break; /* &Addr As=1, Sreg=SR */\r
+ case S_RIN: op += 0x0020 + v1; break; /* @Rn As=2 */\r
+ case S_RIN2: op += 0x0030 + v1; break; /* @Rn+ As=3 */\r
+ default: aerr(); break;\r
+ }\r
+\r
+ /* DOPDST */\r
+ switch(t2) {\r
+ case S_REG: op += 0x0000 + v2; break; /* Rn Ad=0 */\r
+ case S_RIDX: op += 0x0080 + v2; break; /* X(Rn) Ad=1 */\r
+ case S_SYM: op += 0x0080; break; /* addr Ad=1, Sreg=PC */\r
+ case S_IMM: /* #N ==>> &Addr */\r
+ case S_ABS: op += 0x0082; break; /* &Addr Ad=1, Sreg=SR */\r
+ case S_RIN: op += 0x0080 + v2; break; /* @Rn Ad=1 */\r
+ case S_RIN2: op += 0x0080 + v2; break; /* @Rn+ Ad=1 */\r
+ default: aerr(); break;\r
+ }\r
+\r
+ outaw(op);\r
+ /*\r
+ * Source Processing\r
+ */\r
+ switch(t1) {\r
+ case S_REG: break; /* Rn As=0 */\r
+ case S_RIDX: outrw(&e1, 0); break; /* X(Rn) As=1 */\r
+ case S_SYM: if (mchpcr(&e1)) {\r
+ e1.e_addr -= dot.s_addr;\r
+ outaw(e1.e_addr);\r
+ } else {\r
+ outrw(&e1, R_PCR0);\r
+ }\r
+ break; /* addr As=1, Sreg=PC */\r
+ case S_IMM: /* #N ==>> &Addr */\r
+ case S_ABS: outrw(&e1, 0); break; /* &Addr As=1, Sreg=SR */\r
+ case S_RIN: break; /* @Rn As=2 */\r
+ case S_RIN2: break; /* @Rn+ As=3 */\r
+ default: aerr(); break;\r
+ }\r
+ /*\r
+ * Destination Processing\r
+ */\r
+ switch(t2) {\r
+ case S_REG: break; /* Rn Ad=0 */\r
+ case S_RIDX: outrw(&e2, 0); break; /* X(Rn) Ad=1 */\r
+ case S_SYM: if (mchpcr(&e2)) {\r
+ e2.e_addr -= dot.s_addr;\r
+ outaw(e2.e_addr);\r
+ } else {\r
+ outrw(&e2, R_PCR0);\r
+ }\r
+ break; /* addr Ad=1, Sreg=PC */\r
+ case S_IMM: aerr(); /* #N ==>> &Addr */\r
+ case S_ABS: outrw(&e2, 0); break; /* &Addr Ad=1, Sreg=SR */\r
+ case S_RIN: outaw(0); break; /* @Rn Ad=1 */\r
+ case S_RIN2: /* @Rn+ Ad=1 */\r
+ if (rf == S_RLX) {\r
+ if (op & 0x0040) {\r
+ outaw(~0); /* RLX.b @Rn+,-1(Rn) */\r
+ } else {\r
+ outaw(~1); /* RLX.w @Rn+,-2(Rn) */\r
+ }\r
+ } else {\r
+ outaw(0);\r
+ if ((op & 0x0040) && (v2 != 0)) {\r
+ outaw(0x5310 + v2); /* add #1,Rn */\r
+ } else {\r
+ outaw(0x5320 + v2); /* add #2,Rn */\r
+ }\r
+ }\r
+ break;\r
+ default: aerr(); break;\r
+ }\r
+ break;\r
+\r
+ case S_INH:\r
+ outaw(op);\r
+ break;\r
+\r
+ case S_JXX:\r
+ expr(&e1, 0);\r
+ if (mchpcr(&e1)) {\r
+ v1 = (int) (e1.e_addr - dot.s_addr - 2);\r
+ v1 >>= 1;\r
+ if ((v1 < -512) || (v1 > 511))\r
+ aerr();\r
+ outaw(op + (v1 & 0x03FF));\r
+ } else {\r
+ outrwm(&e1, R_PCR | R_JXX, op);\r
+ }\r
+ if (e1.e_mode != S_USER)\r
+ rerr();\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ opcycles = OPCY_ERR;\r
+ err('o');\r
+ break;\r
+ }\r
+\r
+ if (opcycles == OPCY_NONE) {\r
+ v1 = cb[0];\r
+ v2 = cb[1];\r
+ if (v2 & 0xC0) { /* Format 1 Instructions */\r
+ /*\r
+ * Check For Internal Constant Modes\r
+ * R3, As=xx\r
+ * R2, AS=10/11\r
+ */\r
+ if (((v2 & 0x0F) == 0x03) ||\r
+ (((v2 & 0x0F) == 0x02) && (v1 & 0x20))) {\r
+ v1 &= 0xCF;\r
+ }\r
+ switch(v1 & 0xB0) {\r
+ default:\r
+ /* Ad=0,As=00 */case 0x00: opcycles = 1 | OPCY_PC; break;\r
+ /* Ad=0,As=01 */case 0x10: opcycles = 3; break;\r
+ /* Ad=0,As=10 */case 0x20: opcycles = 2; break;\r
+ /* Ad=0,As=11 */case 0x30: opcycles = 2 | OPCY_PC; break;\r
+ /* Ad=1,As=00 */case 0x80: opcycles = 4; break;\r
+ /* Ad=1,As=01 */case 0x90: opcycles = 6; break;\r
+ /* Ad=1,As=10 */case 0xA0: opcycles = 5; break;\r
+ /* Ad=1,As=11 */case 0xB0: opcycles = 5; break;\r
+ }\r
+ if (opcycles & OPCY_PC) {\r
+ if ((v1 & 0x0F) == 0) opcycles += 1;\r
+ opcycles &= ~OPCY_PC;\r
+ }\r
+ } else\r
+ if ((v2 & 0xF8) == 0x10) { /* Format 2 Instructions */\r
+ switch(((v2 << 8) + v1) & 0x03C0) {\r
+ case 0x0000: /* RRC */\r
+ case 0x0040: /* RRC.B */\r
+ case 0x0080: /* SWPB */\r
+ case 0x0100: /* RRA */\r
+ case 0x0140: /* RRA.B */\r
+ case 0x0180: /* SXT */\r
+ switch(v1 & 0x30) {\r
+ /* As/Ad=00 */ case 0x00: opcycles = 1; break;\r
+ /* As/Ad=01 */ case 0x10: opcycles = 4; break;\r
+ /* As/Ad=10 */ case 0x20: opcycles = 3; break;\r
+ /* As/Ad=11 */ case 0x30: opcycles = 3; break;\r
+ }\r
+ break;\r
+ case 0x0200: /* PUSH */\r
+ case 0x0240: /* PUSH.B */\r
+ switch(v1 & 0x30) {\r
+ /* As/Ad=00 */ case 0x00: opcycles = 3; break;\r
+ /* As/Ad=01 */ case 0x10: opcycles = 5; break;\r
+ /* As/Ad=10 */ case 0x20: opcycles = 4; break;\r
+ /* As/Ad=11 */ case 0x30: opcycles = 4; break;\r
+ }\r
+ break;\r
+ case 0x280: /* CALL */\r
+ switch(v1 & 0x30) {\r
+ /* As/Ad=00 */ case 0x00: opcycles = 4; break;\r
+ /* As/Ad=01 */ case 0x10: opcycles = 4; break;\r
+ /* As/Ad=10 */ case 0x20: opcycles = 5; break;\r
+ /* As/Ad=11 */ case 0x30: opcycles = 5; break;\r
+ }\r
+ break;\r
+ case 0x0300: /* RETI */\r
+ opcycles = 5;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ } else\r
+ if (v2 & 0x20) { /* Format 3 Instructions */\r
+ opcycles = 2;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Branch/Jump PCR Mode Check\r
+ */\r
+int\r
+mchpcr(esp)\r
+struct expr *esp;\r
+{\r
+ if (esp->e_base.e_ap == dot.s_area) {\r
+ return(1);\r
+ }\r
+ if (esp->e_flag==0 && esp->e_base.e_ap==NULL) {\r
+ /*\r
+ * Absolute Destination\r
+ *\r
+ * Use the global symbol '.__.ABS.'\r
+ * of value zero and force the assembler\r
+ * to use this absolute constant as the\r
+ * base value for the relocation.\r
+ */\r
+ esp->e_flag = 1;\r
+ esp->e_base.e_sp = &sym[1];\r
+ }\r
+ return(0);\r
+}\r
+\r
+/*\r
+ * Machine specific initialization.\r
+ * Set up the bit table.\r
+ * Process any setup code.\r
+ */\r
+VOID\r
+minit()\r
+{\r
+ /*\r
+ * Byte Order\r
+ */\r
+ hilo = 0;\r
+}\r
+\r
+\r
--- /dev/null
+/* pdp11pst.c */\r
+\r
+/*\r
+ * Copyright (C) 2003-2014 Alan R. Baldwin\r
+ *\r
+ * This program is free software: you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation, either version 3 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.\r
+ *\r
+ *\r
+ * Alan R. Baldwin\r
+ * 721 Berkeley St.\r
+ * Kent, Ohio 44240\r
+ */\r
+\r
+#include "asxxxx.h"\r
+#include "pdp11.h"\r
+\r
+/*\r
+ * Coding Banks\r
+ */\r
+struct bank bank[2] = {\r
+ /* The '_CODE' area/bank has a NULL default file suffix. */\r
+ { NULL, "_CSEG", NULL, 0, 0, 0, 0, 0 },\r
+ { &bank[0], "_DSEG", "_DS", 1, 0, 0, 0, B_FSFX }\r
+};\r
+\r
+/*\r
+ * Coding Areas\r
+ */\r
+struct area area[2] = {\r
+ { NULL, &bank[0], "_CODE", 0, 0, 0, A_1BYTE|A_BNK|A_CSEG },\r
+ { &area[0], &bank[1], "_DATA", 1, 0, 0, A_1BYTE|A_BNK|A_DSEG }\r
+};\r
+\r
+/*\r
+ * Basic Relocation Mode Definition\r
+ *\r
+ * #define R_NORM 0000 No Bit Positioning\r
+ */\r
+char mode0[32] = { /* R_NORM */\r
+ '\200', '\201', '\202', '\203', '\204', '\205', '\206', '\207',\r
+ '\210', '\211', '\212', '\213', '\214', '\215', '\216', '\217',\r
+ '\220', '\221', '\222', '\223', '\224', '\225', '\226', '\227',\r
+ '\230', '\231', '\232', '\233', '\234', '\235', '\236', '\237'\r
+};\r
+\r
+/*\r
+ * Additional Relocation Mode Definitions\r
+ *\r
+ * #define R_JXX 0001 No Bit Positioning\r
+ */\r
+char mode1[32] = { /* R_NORM */\r
+ '\000', '\200', '\201', '\202', '\203', '\204', '\205', '\206',\r
+ '\207', '\210', '\211', '\013', '\014', '\015', '\016', '\017',\r
+ '\020', '\021', '\022', '\023', '\024', '\025', '\026', '\027',\r
+ '\030', '\031', '\032', '\033', '\034', '\035', '\036', '\037'\r
+};\r
+\r
+/*\r
+ * *m_def is a pointer to the bit relocation definition.\r
+ * m_flag indicates that bit position swapping is required.\r
+ * m_dbits contains the active bit positions for the output.\r
+ * m_sbits contains the active bit positions for the input.\r
+ *\r
+ * struct mode\r
+ * {\r
+ * char * m_def; Bit Relocation Definition\r
+ * a_uint m_flag; Bit Swapping Flag\r
+ * a_uint m_dbits; Destination Bit Mask\r
+ * a_uint m_sbits; Source Bit Mask\r
+ * };\r
+ */\r
+struct mode mode[2] = {\r
+ { &mode0[0], 0, 0x0000FFFF, 0x0000FFFF },\r
+ { &mode1[0], 1, 0x000003FF, 0x000007FE }\r
+};\r
+\r
+/*\r
+ * Array of Pointers to mode Structures\r
+ */\r
+struct mode *modep[16] = {\r
+ &mode[0], &mode[1], NULL, NULL,\r
+ NULL, NULL, NULL, NULL,\r
+ NULL, NULL, NULL, NULL,\r
+ NULL, NULL, NULL, NULL\r
+};\r
+\r
+/*\r
+ * Mnemonic Structure\r
+ */\r
+struct mne mne[] = {\r
+\r
+ /* machine */\r
+\r
+ { NULL, "CSEG", S_ATYP, 0, A_CSEG|A_1BYTE },\r
+ { NULL, "DSEG", S_ATYP, 0, A_DSEG|A_1BYTE },\r
+\r
+ /* system */\r
+\r
+ { NULL, "BANK", S_ATYP, 0, A_BNK },\r
+ { NULL, "CON", S_ATYP, 0, A_CON },\r
+ { NULL, "OVR", S_ATYP, 0, A_OVR },\r
+ { NULL, "REL", S_ATYP, 0, A_REL },\r
+ { NULL, "ABS", S_ATYP, 0, A_ABS },\r
+ { NULL, "NOPAG", S_ATYP, 0, A_NOPAG },\r
+ { NULL, "PAG", S_ATYP, 0, A_PAG },\r
+\r
+ { NULL, "BASE", S_BTYP, 0, B_BASE },\r
+ { NULL, "SIZE", S_BTYP, 0, B_SIZE },\r
+ { NULL, "FSFX", S_BTYP, 0, B_FSFX },\r
+ { NULL, "MAP", S_BTYP, 0, B_MAP },\r
+\r
+ { NULL, ".page", S_PAGE, 0, 0 },\r
+ { NULL, ".title", S_HEADER, 0, O_TITLE },\r
+ { NULL, ".sbttl", S_HEADER, 0, O_SBTTL },\r
+ { NULL, ".module", S_MODUL, 0, 0 },\r
+ { NULL, ".include", S_INCL, 0, 0 },\r
+ { NULL, ".area", S_AREA, 0, 0 },\r
+ { NULL, ".bank", S_BANK, 0, 0 },\r
+ { NULL, ".org", S_ORG, 0, 0 },\r
+ { NULL, ".radix", S_RADIX, 0, 0 },\r
+ { NULL, ".globl", S_GLOBL, 0, 0 },\r
+ { NULL, ".local", S_LOCAL, 0, 0 },\r
+ { NULL, ".if", S_CONDITIONAL, 0, O_IF },\r
+ { NULL, ".iff", S_CONDITIONAL, 0, O_IFF },\r
+ { NULL, ".ift", S_CONDITIONAL, 0, O_IFT },\r
+ { NULL, ".iftf", S_CONDITIONAL, 0, O_IFTF },\r
+ { NULL, ".ifdef", S_CONDITIONAL, 0, O_IFDEF },\r
+ { NULL, ".ifndef", S_CONDITIONAL, 0, O_IFNDEF},\r
+ { NULL, ".ifgt", S_CONDITIONAL, 0, O_IFGT },\r
+ { NULL, ".iflt", S_CONDITIONAL, 0, O_IFLT },\r
+ { NULL, ".ifge", S_CONDITIONAL, 0, O_IFGE },\r
+ { NULL, ".ifle", S_CONDITIONAL, 0, O_IFLE },\r
+ { NULL, ".ifeq", S_CONDITIONAL, 0, O_IFEQ },\r
+ { NULL, ".ifne", S_CONDITIONAL, 0, O_IFNE },\r
+ { NULL, ".ifb", S_CONDITIONAL, 0, O_IFB },\r
+ { NULL, ".ifnb", S_CONDITIONAL, 0, O_IFNB },\r
+ { NULL, ".ifidn", S_CONDITIONAL, 0, O_IFIDN },\r
+ { NULL, ".ifdif", S_CONDITIONAL, 0, O_IFDIF },\r
+ { NULL, ".iif", S_CONDITIONAL, 0, O_IIF },\r
+ { NULL, ".iiff", S_CONDITIONAL, 0, O_IIFF },\r
+ { NULL, ".iift", S_CONDITIONAL, 0, O_IIFT },\r
+ { NULL, ".iiftf", S_CONDITIONAL, 0, O_IIFTF },\r
+ { NULL, ".iifdef", S_CONDITIONAL, 0, O_IIFDEF},\r
+ { NULL, ".iifndef", S_CONDITIONAL, 0, O_IIFNDEF},\r
+ { NULL, ".iifgt", S_CONDITIONAL, 0, O_IIFGT },\r
+ { NULL, ".iiflt", S_CONDITIONAL, 0, O_IIFLT },\r
+ { NULL, ".iifge", S_CONDITIONAL, 0, O_IIFGE },\r
+ { NULL, ".iifle", S_CONDITIONAL, 0, O_IIFLE },\r
+ { NULL, ".iifeq", S_CONDITIONAL, 0, O_IIFEQ },\r
+ { NULL, ".iifne", S_CONDITIONAL, 0, O_IIFNE },\r
+ { NULL, ".iifb", S_CONDITIONAL, 0, O_IIFB },\r
+ { NULL, ".iifnb", S_CONDITIONAL, 0, O_IIFNB },\r
+ { NULL, ".iifidn", S_CONDITIONAL, 0, O_IIFIDN},\r
+ { NULL, ".iifdif", S_CONDITIONAL, 0, O_IIFDIF},\r
+ { NULL, ".else", S_CONDITIONAL, 0, O_ELSE },\r
+ { NULL, ".endif", S_CONDITIONAL, 0, O_ENDIF },\r
+ { NULL, ".list", S_LISTING, 0, O_LIST },\r
+ { NULL, ".nlist", S_LISTING, 0, O_NLIST },\r
+ { NULL, ".equ", S_EQU, 0, O_EQU },\r
+ { NULL, ".gblequ", S_EQU, 0, O_GBLEQU},\r
+ { NULL, ".lclequ", S_EQU, 0, O_LCLEQU},\r
+ { NULL, ".byte", S_DATA, 0, O_1BYTE },\r
+ { NULL, ".db", S_DATA, 0, O_1BYTE },\r
+ { NULL, ".fcb", S_DATA, 0, O_1BYTE },\r
+ { NULL, ".word", S_DATA, 0, O_2BYTE },\r
+ { NULL, ".dw", S_DATA, 0, O_2BYTE },\r
+ { NULL, ".fdb", S_DATA, 0, O_2BYTE },\r
+/* { NULL, ".3byte", S_DATA, 0, O_3BYTE }, */\r
+/* { NULL, ".triple", S_DATA, 0, O_3BYTE }, */\r
+/* { NULL, ".4byte", S_DATA, 0, O_4BYTE }, */\r
+/* { NULL, ".quad", S_DATA, 0, O_4BYTE }, */\r
+ { NULL, ".blkb", S_BLK, 0, O_1BYTE },\r
+ { NULL, ".ds", S_BLK, 0, O_1BYTE },\r
+ { NULL, ".rmb", S_BLK, 0, O_1BYTE },\r
+ { NULL, ".rs", S_BLK, 0, O_1BYTE },\r
+ { NULL, ".blkw", S_BLK, 0, O_2BYTE },\r
+/* { NULL, ".blk3", S_BLK, 0, O_3BYTE }, */\r
+/* { NULL, ".blk4", S_BLK, 0, O_4BYTE }, */\r
+ { NULL, ".ascii", S_ASCIX, 0, O_ASCII },\r
+ { NULL, ".ascis", S_ASCIX, 0, O_ASCIS },\r
+ { NULL, ".asciz", S_ASCIX, 0, O_ASCIZ },\r
+ { NULL, ".str", S_ASCIX, 0, O_ASCII },\r
+ { NULL, ".strs", S_ASCIX, 0, O_ASCIS },\r
+ { NULL, ".strz", S_ASCIX, 0, O_ASCIZ },\r
+ { NULL, ".fcc", S_ASCIX, 0, O_ASCII },\r
+ { NULL, ".define", S_DEFINE, 0, O_DEF },\r
+ { NULL, ".undefine", S_DEFINE, 0, O_UNDEF },\r
+ { NULL, ".even", S_BOUNDARY, 0, O_EVEN },\r
+ { NULL, ".odd", S_BOUNDARY, 0, O_ODD },\r
+ { NULL, ".bndry", S_BOUNDARY, 0, O_BNDRY },\r
+ { NULL, ".msg" , S_MSG, 0, 0 },\r
+ { NULL, ".assume", S_ERROR, 0, O_ASSUME},\r
+ { NULL, ".error", S_ERROR, 0, O_ERROR },\r
+/* { NULL, ".msb", S_MSB, 0, 0 }, */\r
+/* { NULL, ".lohi", S_MSB, 0, O_LOHI }, */\r
+/* { NULL, ".hilo", S_MSB, 0, O_HILO }, */\r
+/* { NULL, ".8bit", S_BITS, 0, O_1BYTE }, */\r
+/* { NULL, ".16bit", S_BITS, 0, O_2BYTE }, */\r
+/* { NULL, ".24bit", S_BITS, 0, O_3BYTE }, */\r
+/* { NULL, ".32bit", S_BITS, 0, O_4BYTE }, */\r
+ { NULL, ".end", S_END, 0, 0 },\r
+\r
+ /* Macro Processor */\r
+\r
+ { NULL, ".macro", S_MACRO, 0, O_MACRO },\r
+ { NULL, ".endm", S_MACRO, 0, O_ENDM },\r
+ { NULL, ".mexit", S_MACRO, 0, O_MEXIT },\r
+\r
+ { NULL, ".narg", S_MACRO, 0, O_NARG },\r
+ { NULL, ".nchr", S_MACRO, 0, O_NCHR },\r
+ { NULL, ".ntyp", S_MACRO, 0, O_NTYP },\r
+\r
+ { NULL, ".irp", S_MACRO, 0, O_IRP },\r
+ { NULL, ".irpc", S_MACRO, 0, O_IRPC },\r
+ { NULL, ".rept", S_MACRO, 0, O_REPT },\r
+\r
+ { NULL, ".nval", S_MACRO, 0, O_NVAL },\r
+\r
+ { NULL, ".mdelete", S_MACRO, 0, O_MDEL },\r
+\r
+ /* double operand */\r
+\r
+ { NULL, "mov", S_DOUBLE, 0, 0010000 },\r
+ { NULL, "movb", S_DOUBLE, 0, 0110000 },\r
+ { NULL, "cmp", S_DOUBLE, 0, 0020000 },\r
+ { NULL, "cmpb", S_DOUBLE, 0, 0120000 },\r
+ { NULL, "bit", S_DOUBLE, 0, 0030000 },\r
+ { NULL, "bitb", S_DOUBLE, 0, 0130000 },\r
+ { NULL, "bic", S_DOUBLE, 0, 0040000 },\r
+ { NULL, "bicb", S_DOUBLE, 0, 0140000 },\r
+ { NULL, "bis", S_DOUBLE, 0, 0050000 },\r
+ { NULL, "bisb", S_DOUBLE, 0, 0150000 },\r
+ { NULL, "add", S_DOUBLE, 0, 0060000 },\r
+ { NULL, "sub", S_DOUBLE, 0, 0160000 },\r
+\r
+ /* branch */\r
+\r
+ { NULL, "br", S_BRANCH, 0, 0000400 },\r
+ { NULL, "bne", S_BRANCH, 0, 0001000 },\r
+ { NULL, "beq", S_BRANCH, 0, 0001400 },\r
+ { NULL, "bge", S_BRANCH, 0, 0002000 },\r
+ { NULL, "blt", S_BRANCH, 0, 0002400 },\r
+ { NULL, "bgt", S_BRANCH, 0, 0003000 },\r
+ { NULL, "ble", S_BRANCH, 0, 0003400 },\r
+ { NULL, "bpl", S_BRANCH, 0, 0100000 },\r
+ { NULL, "bmi", S_BRANCH, 0, 0100400 },\r
+ { NULL, "bhi", S_BRANCH, 0, 0101000 },\r
+ { NULL, "blos", S_BRANCH, 0, 0101400 },\r
+ { NULL, "bvc", S_BRANCH, 0, 0102000 },\r
+ { NULL, "bvs", S_BRANCH, 0, 0102400 },\r
+ { NULL, "bhis", S_BRANCH, 0, 0103000 },\r
+ { NULL, "bec", S_BRANCH, 0, 0103000 },\r
+ { NULL, "bcc", S_BRANCH, 0, 0103000 },\r
+ { NULL, "blo", S_BRANCH, 0, 0103400 },\r
+ { NULL, "bcs", S_BRANCH, 0, 0103400 },\r
+ { NULL, "bes", S_BRANCH, 0, 0103400 },\r
+\r
+ /* jump/branch type */\r
+\r
+ { NULL, "jbr", S_JBR, 0, 0000400 },\r
+ { NULL, "jne", S_JCOND, 0, 0001000 },\r
+ { NULL, "jeq", S_JCOND, 0, 0001400 },\r
+ { NULL, "jge", S_JCOND, 0, 0002000 },\r
+ { NULL, "jlt", S_JCOND, 0, 0002400 },\r
+ { NULL, "jgt", S_JCOND, 0, 0003000 },\r
+ { NULL, "jle", S_JCOND, 0, 0003400 },\r
+ { NULL, "jpl", S_JCOND, 0, 0100000 },\r
+ { NULL, "jmi", S_JCOND, 0, 0100400 },\r
+ { NULL, "jhi", S_JCOND, 0, 0101000 },\r
+ { NULL, "jlos", S_JCOND, 0, 0101400 },\r
+ { NULL, "jvc", S_JCOND, 0, 0102000 },\r
+ { NULL, "jvs", S_JCOND, 0, 0102400 },\r
+ { NULL, "jhis", S_JCOND, 0, 0103000 },\r
+ { NULL, "jec", S_JCOND, 0, 0103000 },\r
+ { NULL, "jcc", S_JCOND, 0, 0103000 },\r
+ { NULL, "jlo", S_JCOND, 0, 0103400 },\r
+ { NULL, "jcs", S_JCOND, 0, 0103400 },\r
+ { NULL, "jes", S_JCOND, 0, 0103400 },\r
+\r
+ /* single operand */\r
+\r
+ { NULL, "clr", S_SINGLE, 0, 0005000 },\r
+ { NULL, "clrb", S_SINGLE, 0, 0105000 },\r
+ { NULL, "com", S_SINGLE, 0, 0005100 },\r
+ { NULL, "comb", S_SINGLE, 0, 0105100 },\r
+ { NULL, "inc", S_SINGLE, 0, 0005200 },\r
+ { NULL, "incb", S_SINGLE, 0, 0105200 },\r
+ { NULL, "dec", S_SINGLE, 0, 0005300 },\r
+ { NULL, "decb", S_SINGLE, 0, 0105300 },\r
+ { NULL, "neg", S_SINGLE, 0, 0005400 },\r
+ { NULL, "negb", S_SINGLE, 0, 0105400 },\r
+ { NULL, "adc", S_SINGLE, 0, 0005500 },\r
+ { NULL, "adcb", S_SINGLE, 0, 0105500 },\r
+ { NULL, "sbc", S_SINGLE, 0, 0005600 },\r
+ { NULL, "sbcb", S_SINGLE, 0, 0105600 },\r
+ { NULL, "tst", S_SINGLE, 0, 0005700 },\r
+ { NULL, "tstb", S_SINGLE, 0, 0105700 },\r
+ { NULL, "ror", S_SINGLE, 0, 0006000 },\r
+ { NULL, "rorb", S_SINGLE, 0, 0106000 },\r
+ { NULL, "rol", S_SINGLE, 0, 0006100 },\r
+ { NULL, "rolb", S_SINGLE, 0, 0106100 },\r
+ { NULL, "asr", S_SINGLE, 0, 0006200 },\r
+ { NULL, "asrb", S_SINGLE, 0, 0106200 },\r
+ { NULL, "asl", S_SINGLE, 0, 0006300 },\r
+ { NULL, "aslb", S_SINGLE, 0, 0106300 },\r
+ { NULL, "jmp", S_SINGLE, 0, 0000100 },\r
+ { NULL, "swab", S_SINGLE, 0, 0000300 },\r
+ { NULL, "mfpi", S_SINGLE, 0, 0006500 },\r
+ { NULL, "mtpi", S_SINGLE, 0, 0006600 },\r
+ { NULL, "mfpd", S_SINGLE, 0, 0106500 },\r
+ { NULL, "mtpd", S_SINGLE, 0, 0106600 },\r
+ { NULL, "stst", S_SINGLE, 0, 0170300 },\r
+ { NULL, "mfps", S_SINGLE, 0, 0106700 },\r
+ { NULL, "mtps", S_SINGLE, 0, 0106400 },\r
+ { NULL, "csm", S_SINGLE, 0, 0007000 },\r
+ { NULL, "tstset", S_SINGLE, 0, 0007200 },\r
+ { NULL, "wrtlck", S_SINGLE, 0, 0007300 },\r
+\r
+ /* jsr */\r
+\r
+ { NULL, "jsr", S_JSR, 0, 0004000 },\r
+\r
+ /* rts */\r
+\r
+ { NULL, "rts", S_RTS, 0, 0000200 },\r
+\r
+ /* simple operand */\r
+\r
+ { NULL, "sys", S_SYSTRAP, 0, 0104400 },\r
+ { NULL, "spl", S_SYSTRAP, 0, 0000230 },\r
+\r
+ /* flag-setting */\r
+\r
+ { NULL, "nop", S_ABS, 0, 0000240 },\r
+ { NULL, "clc", S_ABS, 0, 0000241 },\r
+ { NULL, "clv", S_ABS, 0, 0000242 },\r
+ { NULL, "clz", S_ABS, 0, 0000244 },\r
+ { NULL, "cln", S_ABS, 0, 0000250 },\r
+ { NULL, "ccc", S_ABS, 0, 0000257 },\r
+ { NULL, "sec", S_ABS, 0, 0000261 },\r
+ { NULL, "sev", S_ABS, 0, 0000262 },\r
+ { NULL, "sez", S_ABS, 0, 0000264 },\r
+ { NULL, "sen", S_ABS, 0, 0000270 },\r
+ { NULL, "scc", S_ABS, 0, 0000277 },\r
+ { NULL, "halt", S_ABS, 0, 0000000 },\r
+ { NULL, "wait", S_ABS, 0, 0000001 },\r
+ { NULL, "rti", S_ABS, 0, 0000002 },\r
+ { NULL, "bpt", S_ABS, 0, 0000003 },\r
+ { NULL, "iot", S_ABS, 0, 0000004 },\r
+ { NULL, "reset", S_ABS, 0, 0000005 },\r
+ { NULL, "rtt", S_ABS, 0, 0000006 },\r
+ { NULL, "mfpt", S_ABS, 0, 0000007 },\r
+\r
+ /* floating point ops */\r
+\r
+ { NULL, "cfcc", S_ABS, 0, 0170000 },\r
+ { NULL, "setf", S_ABS, 0, 0170001 },\r
+ { NULL, "setd", S_ABS, 0, 0170011 },\r
+ { NULL, "seti", S_ABS, 0, 0170002 },\r
+ { NULL, "setl", S_ABS, 0, 0170012 },\r
+ { NULL, "clrf", S_SINGLE, 0, 0170400 },\r
+ { NULL, "negf", S_SINGLE, 0, 0170700 },\r
+ { NULL, "absf", S_SINGLE, 0, 0170600 },\r
+ { NULL, "tstf", S_SINGLE, 0, 0170500 },\r
+ { NULL, "movf", S_MOVF, 0, 0172400 },\r
+ { NULL, "movif", S_FLOP, 0, 0177000 },\r
+ { NULL, "movfi", S_MOVFO, 0, 0175400 },\r
+ { NULL, "movof", S_FLOP, 0, 0177400 },\r
+ { NULL, "movfo", S_MOVFO, 0, 0176000 },\r
+ { NULL, "addf", S_FLOP, 0, 0172000 },\r
+ { NULL, "subf", S_FLOP, 0, 0173000 },\r
+ { NULL, "mulf", S_FLOP, 0, 0171000 },\r
+ { NULL, "divf", S_FLOP, 0, 0174400 },\r
+ { NULL, "cmpf", S_FLOP, 0, 0173400 },\r
+ { NULL, "modf", S_FLOP, 0, 0171400 },\r
+ { NULL, "movie", S_FLOP, 0, 0176400 },\r
+ { NULL, "movei", S_MOVFO, 0, 0175000 },\r
+ { NULL, "ldfps", S_SINGLE, 0, 0170100 },\r
+ { NULL, "stfps", S_SINGLE, 0, 0170200 },\r
+\r
+ { NULL, "mul", S_MULDIV, 0, 0070000 },\r
+ { NULL, "div", S_MULDIV, 0, 0071000 },\r
+ { NULL, "ash", S_MULDIV, 0, 0072000 },\r
+ { NULL, "ashc", S_MULDIV, 0, 0073000 },\r
+ { NULL, "xor", S_JSR, 0, 0074000 },\r
+ { NULL, "sxt", S_SINGLE, 0, 0006700 },\r
+ { NULL, "mark", S_SYSTRAP, 0, 0006400 },\r
+ { NULL, "sob", S_SOB, 0, 0077000 },\r
+\r
+};\r
--- /dev/null
+ .title AS430 Assembler Checks\r
+\r
+ ; Assembler this file:\r
+ ;\r
+ ; as430 -gloaxff t430\r
+ ;\r
+ ;\r
+ ; A Destination Mode of #N is considered\r
+ ; an addressing syntax error. The code generated\r
+ ; defaults to an absolute address of N.\r
+ ;\r
+\r
+ .area AS430 (ABS,OVR)\r
+ .org 0x0000\r
+\r
+\r
+ .sbttl 'DOP' Instruction Tests\r
+\r
+ ; Test Addressing Modes for Dual Operand Instructions\r
+ \r
+ .sbttl Quick WORD DOP Check\r
+\r
+DOP: ; Check all Registers\r
+ mov r0, r15 ; 0F 40\r
+ mov r1, r15 ; 0F 41\r
+ mov r2, r15 ; 0F 42\r
+ mov r3, r15 ; 0F 43\r
+ mov r4, r15 ; 0F 44\r
+ mov r5, r15 ; 0F 45\r
+ mov r6, r15 ; 0F 46\r
+ mov r7, r15 ; 0F 47\r
+ mov r8, r15 ; 0F 48\r
+ mov r9, r15 ; 0F 49\r
+ mov r10, r15 ; 0F 4A\r
+ mov r11, r15 ; 0F 4B\r
+ mov r12, r15 ; 0F 4C\r
+ mov r13, r15 ; 0F 4D\r
+ mov r14, r15 ; 0F 4E\r
+ mov r15, r15 ; 0F 4F\r
+\r
+ mov pc, r15 ; 0F 40\r
+ mov sp, r15 ; 0F 41\r
+ mov sr, r15 ; 0F 42\r
+ mov cg1, r15 ; 0F 42\r
+ mov cg2, r15 ; 0F 43\r
+\r
+ mov r15, r0 ; 00 4F\r
+ mov r15, r1 ; 01 4F\r
+ mov r15, r2 ; 02 4F\r
+ mov r15, r3 ; 03 4F\r
+ mov r15, r4 ; 04 4F\r
+ mov r15, r5 ; 05 4F\r
+ mov r15, r6 ; 06 4F\r
+ mov r15, r7 ; 07 4F\r
+ mov r15, r8 ; 08 4F\r
+ mov r15, r9 ; 09 4F\r
+ mov r15, r10 ; 0A 4F\r
+ mov r15, r11 ; 0B 4F\r
+ mov r15, r12 ; 0C 4F\r
+ mov r15, r13 ; 0D 4F\r
+ mov r15, r14 ; 0E 4F\r
+ mov r15, r15 ; 0F 4F\r
+\r
+ mov r15, pc ; 00 4F\r
+ mov r15, sp ; 01 4F\r
+ mov r15, sr ; 02 4F\r
+ mov r15, cg1 ; 02 4F\r
+ mov r15, cg2 ; 03 4F\r
+\r
+ ; Special Constants Mode to Register R15\r
+1$: mov #4, r15 ; 2F 42\r
+ mov #8, r15 ; 3F 42\r
+ mov #0, r15 ; 0F 43\r
+ mov #1, r15 ; 1F 43\r
+ mov #2, r15 ; 2F 43\r
+ mov #-1, r15 ; 3F 43\r
+\r
+ ; All Addressing Modes to Register r15\r
+ mov r5, r15 ; 0F 45\r
+ mov 0x2(r5),r15 ; 1F 45 02 00\r
+ mov 1$, r15 ; 1F 40 EC FF\r
+ mov &1$, r15 ; 1F 42r54s00\r
+ mov @r5, r15 ; 2F 45\r
+ mov @r5+, r15 ; 3F 45\r
+ mov #0x3412,r15 ; 3F 40 12 34\r
+\r
+ ; Alternate Forms\r
+ mov (r5), r15 ; 2F 45\r
+ mov (r5)+, r15 ; 3F 45\r
+\r
+ mov (pc)+, r15 ; 3F 40\r
+2$: .word 0x3412 ; 12 34\r
+\r
+\r
+ .sbttl All Normal Modes with R4/R8\r
+\r
+ ; Special Constants Mode to Register R4\r
+3$: mov #4, r4 ; 24 42\r
+ mov #8, r4 ; 34 42\r
+ mov #0, r4 ; 04 43\r
+ mov #1, r4 ; 14 43\r
+ mov #2, r4 ; 24 43\r
+ mov #-1, r4 ; 34 43\r
+\r
+ ; All Addressing Modes to Register R4\r
+ mov r5, r4 ; 04 45\r
+ mov 0x2(r5),r4 ; 14 45 02 00\r
+ mov 3$, r4 ; 14 40 EC FF\r
+ mov &3$, r4 ; 14 42r7Es00\r
+ mov @r5, r4 ; 24 45\r
+ mov @r5+, r4 ; 34 45\r
+ mov #0x3412,r4 ; 34 40 12 34\r
+\r
+ ; Special Constants Mode to Register 0x7856(R4)\r
+ mov #4, 0x7856(r4) ; A4 42 56 78\r
+ mov #8, 0x7856(r4) ; B4 42 56 78\r
+ mov #0, 0x7856(r4) ; 84 43 56 78\r
+ mov #1, 0x7856(r4) ; 94 43 56 78\r
+ mov #2, 0x7856(r4) ; A4 43 56 78\r
+ mov #-1, 0x7856(r4) ; B4 43 56 78\r
+\r
+ ; All Addressing Modes to X(r4)\r
+ mov r5, 0x7856(r4) ; 84 45 56 78\r
+ mov 0x2(r5),0x7856(r4) ; 94 45 02 00 56 78\r
+ mov 3$, 0x7856(r4) ; 94 40 BA FF 56 78\r
+ mov &3$, 0x7856(r4) ; 94 42r7Es00 56 78\r
+ mov @r5, 0x7856(r4) ; A4 45 56 78\r
+ mov @r5+, 0x7856(r4) ; B4 45 56 78\r
+ mov #0x3412,0x7856(r4) ; B4 40 12 34 56 78\r
+\r
+ ; Special Constants Mode to Register R8\r
+4$: mov #4, r8 ; 28 42\r
+ mov #8, r8 ; 38 42\r
+ mov #0, r8 ; 08 43\r
+ mov #1, r8 ; 18 43\r
+ mov #2, r8 ; 28 43\r
+ mov #-1, r8 ; 38 43\r
+\r
+ ; All Addressing Modes to Register R8\r
+ mov r5, r8 ; 08 45\r
+ mov 0x2(r5),r8 ; 18 45 02 00\r
+ mov 4$, r8 ; 18 40 EC FF\r
+ mov &4$, r8 ; 18 42rDCs00\r
+ mov @r5, r8 ; 28 45\r
+ mov @r5+, r8 ; 38 45\r
+ mov #0x3412,r8 ; 38 40 12 34\r
+\r
+ ; Special Constants Mode to Register 0x7856(R8)\r
+ mov #4, 0x7856(r8) ; A8 42 56 78\r
+ mov #8, 0x7856(r8) ; B8 42 56 78\r
+ mov #0, 0x7856(r8) ; 88 43 56 78\r
+ mov #1, 0x7856(r8) ; 98 43 56 78\r
+ mov #2, 0x7856(r8) ; A8 43 56 78\r
+ mov #-1, 0x7856(r8) ; B8 43 56 78\r
+\r
+ ; All Addressing Modes to X(r8)\r
+ mov r5, 0x7856(r8) ; 88 45 56 78\r
+ mov 0x2(r5),0x7856(r8) ; 98 45 02 00 56 78\r
+ mov 4$, 0x7856(r8) ; 98 40 BA FF 56 78\r
+ mov &4$, 0x7856(r8) ; 98 42rDCs00 56 78\r
+ mov @r5, 0x7856(r8) ; A8 45 56 78\r
+ mov @r5+, 0x7856(r8) ; B8 45 56 78\r
+ mov #0x3412,0x7856(r8) ; B8 40 12 34 56 78\r
+\r
+ ; Special Constants Mode to 6$\r
+ mov #4, 6$ ; A0 42 78 00\r
+ mov #8, 6$ ; B0 42 74 00\r
+ mov #0, 6$ ; 80 43 70 00\r
+ mov #1, 6$ ; 90 43 6C 00\r
+ mov #2, 6$ ; A0 43 68 00\r
+ mov #-1, 6$ ; B0 43 64 00\r
+\r
+ ; All Addressing Modes to 6$\r
+ mov r5, 6$ ; 80 45 60 00\r
+ mov 0x2(r5),6$ ; 90 45 02 00 5A 00\r
+ mov 5$, 6$ ; 90 40 54 00 54 00\r
+ mov &5$, 6$ ; 90 42rB2s01 4E 00\r
+ mov @r5, 6$ ; A0 45 4A 00\r
+ mov @r5+, 6$ ; B0 45 46 00\r
+ mov #0x3412,6$ ; B0 40 12 34 40 00\r
+\r
+ ; Special Constants Mode to &6$\r
+ mov #4, &6$ ; A2 42rB4s01\r
+ mov #8, &6$ ; B2 42rB4s01\r
+ mov #0, &6$ ; 82 43rB4s01\r
+ mov #1, &6$ ; 92 43rB4s01\r
+ mov #2, &6$ ; A2 43rB4s01\r
+ mov #-1, &6$ ; B2 43rB4s01\r
+\r
+ ; All Addressing Modes to &6$\r
+ mov r5, &6$ ; 82 45rB4s01\r
+ mov 0x2(r5),&6$ ; 92 45 02 00rB4s01\r
+ mov 5$, &6$ ; 92 40 18 00rB4s01\r
+ mov &5$, &6$ ; 92 42rB2s01rB4s01\r
+ mov @r5, &6$ ; A2 45rB4s01\r
+ mov @r5+, &6$ ; B2 45rB4s01\r
+ mov #0x3412,&6$ ; B2 40 12 34rB4s01\r
+\r
+5$: .word 0 ; 00 00\r
+6$: .word 0 ; 00 00\r
+\r
+\r
+ .sbttl Emulated Modes with R4/R8\r
+\r
+ ; Special Constants Mode to @r4\r
+7$: mov #4, @r4 ; A4 42 00 00\r
+ mov #8, @r4 ; B4 42 00 00\r
+ mov #0, @r4 ; 84 43 00 00\r
+ mov #1, @r4 ; 94 43 00 00\r
+ mov #2, @r4 ; A4 43 00 00\r
+ mov #-1, @r4 ; B4 43 00 00\r
+\r
+ ; All Addressing Modes to @r4\r
+ mov r5, @r4 ; 84 45 00 00\r
+ mov 0x2(r5),@r4 ; 94 45 02 00 00 00\r
+ mov 7$, @r4 ; 94 40 DC FF 00 00\r
+ mov &7$, @r4 ; 94 42rB6s01 00 00\r
+ mov @r5, @r4 ; A4 45 00 00\r
+ mov @r5+, @r4 ; B4 45 00 00\r
+ mov #0x3412,@r4 ; B4 40 12 34 00 00\r
+\r
+ ; Special Constants Mode to @r4+\r
+ mov #4, @r4+ ; A4 42 00 00 24 53\r
+ mov #8, @r4+ ; B4 42 00 00 24 53\r
+ mov #0, @r4+ ; 84 43 00 00 24 53\r
+ mov #1, @r4+ ; 94 43 00 00 24 53\r
+ mov #2, @r4+ ; A4 43 00 00 24 53\r
+ mov #-1, @r4+ ; B4 43 00 00 24 53\r
+\r
+ ; All Addressing Modes to @r4+\r
+ mov r5, @r4+ ; 84 45 00 00 24 53\r
+ mov 0x2(r5),@r4+ ; 94 45 02 00 00 00\r
+ mov 7$, @r4+ ; 94 40 90 FF 00 00\r
+ mov &7$, @r4+ ; 94 42rB6s01 00 00\r
+ mov @r5, @r4+ ; A4 45 00 00 24 53\r
+ mov @r5+, @r4+ ; B4 45 00 00 24 53\r
+ mov #0x3412,@r4+ ; B4 40 12 34 00 00\r
+\r
+ ; Special Constants Mode to @r8\r
+8$: mov #4, @r8 ; A8 42 00 00\r
+ mov #8, @r8 ; B8 42 00 00\r
+ mov #0, @r8 ; 88 43 00 00\r
+ mov #1, @r8 ; 98 43 00 00\r
+ mov #2, @r8 ; A8 43 00 00\r
+ mov #-1, @r8 ; B8 43 00 00\r
+\r
+ ; All Addressing Modes to @r8\r
+ mov r5, @r8 ; 88 45 00 00\r
+ mov 0x2(r5),@r8 ; 98 45 02 00 00 00\r
+ mov 8$, @r8 ; 98 40 DC FF 00 00\r
+ mov &8$, @r8 ; 98 42r48s02 00 00\r
+ mov @r5, @r8 ; A8 45 00 00\r
+ mov @r5+, @r8 ; B8 45 00 00\r
+ mov #0x3412,@r8 ; B8 40 12 34 00 00\r
+\r
+ ; Special Constants Mode to @r8+\r
+ mov #4, @r8+ ; A8 42 00 00 28 53\r
+ mov #8, @r8+ ; B8 42 00 00 28 53\r
+ mov #0, @r8+ ; 88 43 00 00 28 53\r
+ mov #1, @r8+ ; 98 43 00 00 28 53\r
+ mov #2, @r8+ ; A8 43 00 00 28 53\r
+ mov #-1, @r8+ ; B8 43 00 00 28 53\r
+\r
+ ; All Addressing Modes to @r8+\r
+ mov r5, @r8+ ; 88 45 00 00 28 53\r
+ mov 0x2(r5),@r8+ ; 98 45 02 00 00 00\r
+ mov 8$, @r8+ ; 98 40 90 FF 00 00\r
+ mov &8$, @r8+ ; 98 42r48s02 00 00\r
+ mov @r5, @r8+ ; A8 45 00 00 28 53\r
+ mov @r5+, @r8+ ; B8 45 00 00 28 53\r
+ mov #0x3412,@r8+ ; B8 40 12 34 00 00\r
+\r
+\r
+ .sbttl Quick BYTE DOP Check\r
+\r
+ ; Check all Registers\r
+ mov.b r0, r15 ; 4F 40\r
+ mov.b r1, r15 ; 4F 41\r
+ mov.b r2, r15 ; 4F 42\r
+ mov.b r3, r15 ; 4F 43\r
+ mov.b r4, r15 ; 4F 44\r
+ mov.b r5, r15 ; 4F 45\r
+ mov.b r6, r15 ; 4F 46\r
+ mov.b r7, r15 ; 4F 47\r
+ mov.b r8, r15 ; 4F 48\r
+ mov.b r9, r15 ; 4F 49\r
+ mov.b r10, r15 ; 4F 4A\r
+ mov.b r11, r15 ; 4F 4B\r
+ mov.b r12, r15 ; 4F 4C\r
+ mov.b r13, r15 ; 4F 4D\r
+ mov.b r14, r15 ; 4F 4E\r
+ mov.b r15, r15 ; 4F 4F\r
+\r
+ mov.b pc, r15 ; 4F 40\r
+ mov.b sp, r15 ; 4F 41\r
+ mov.b sr, r15 ; 4F 42\r
+ mov.b cg1, r15 ; 4F 42\r
+ mov.b cg2, r15 ; 4F 43\r
+\r
+ mov.b r15, r0 ; 40 4F\r
+ mov.b r15, r1 ; 41 4F\r
+ mov.b r15, r2 ; 42 4F\r
+ mov.b r15, r3 ; 43 4F\r
+ mov.b r15, r4 ; 44 4F\r
+ mov.b r15, r5 ; 45 4F\r
+ mov.b r15, r6 ; 46 4F\r
+ mov.b r15, r7 ; 47 4F\r
+ mov.b r15, r8 ; 48 4F\r
+ mov.b r15, r9 ; 49 4F\r
+ mov.b r15, r10 ; 4A 4F\r
+ mov.b r15, r11 ; 4B 4F\r
+ mov.b r15, r12 ; 4C 4F\r
+ mov.b r15, r13 ; 4D 4F\r
+ mov.b r15, r14 ; 4E 4F\r
+ mov.b r15, r15 ; 4F 4F\r
+\r
+ mov.b r15, pc ; 40 4F\r
+ mov.b r15, sp ; 41 4F\r
+ mov.b r15, sr ; 42 4F\r
+ mov.b r15, cg1 ; 42 4F\r
+ mov.b r15, cg2 ; 43 4F\r
+\r
+ ; Special Constants Mode to Register R15\r
+11$: mov.b #4, r15 ; 6F 42\r
+ mov.b #8, r15 ; 7F 42\r
+ mov.b #0, r15 ; 4F 43\r
+ mov.b #1, r15 ; 5F 43\r
+ mov.b #2, r15 ; 6F 43\r
+ mov.b #-1, r15 ; 7F 43\r
+\r
+ ; All Addressing Modes to Register r15\r
+ mov.b r5, r15 ; 4F 45\r
+ mov.b 0x2(r5),r15 ; 5F 45 02 00\r
+ mov.b 11$, r15 ; 5F 40 EC FF\r
+ mov.b &11$, r15 ; 5F 42r2Es03\r
+ mov.b @r5, r15 ; 6F 45\r
+ mov.b @r5+, r15 ; 7F 45\r
+ mov.b #0x3412,r15 ; 7F 40 12 34\r
+\r
+ ; Alternate Forms\r
+ mov.b (r5), r15 ; 6F 45\r
+ mov.b (r5)+, r15 ; 7F 45\r
+\r
+ mov.b (pc)+, r15 ; 7F 40\r
+12$: .word 0x3412 ; 12 34\r
+\r
+\r
+ .sbttl All Normal Modes with R4/R8\r
+\r
+ ; Special Constants Mode to Register R4\r
+13$: mov.b #4, r4 ; 64 42\r
+ mov.b #8, r4 ; 74 42\r
+ mov.b #0, r4 ; 44 43\r
+ mov.b #1, r4 ; 54 43\r
+ mov.b #2, r4 ; 64 43\r
+ mov.b #-1, r4 ; 74 43\r
+\r
+ ; All Addressing Modes to Register R4\r
+ mov.b r5, r4 ; 44 45\r
+ mov.b 0x2(r5),r4 ; 54 45 02 00\r
+ mov.b 13$, r4 ; 54 40 EC FF\r
+ mov.b &13$, r4 ; 54 42r58s03\r
+ mov.b @r5, r4 ; 64 45\r
+ mov.b @r5+, r4 ; 74 45\r
+ mov.b #0x3412,r4 ; 74 40 12 34\r
+\r
+ ; Special Constants Mode to Register 0x7856(R4)\r
+ mov.b #4, 0x7856(r4) ; E4 42 56 78\r
+ mov.b #8, 0x7856(r4) ; F4 42 56 78\r
+ mov.b #0, 0x7856(r4) ; C4 43 56 78\r
+ mov #1, 0x7856(r4) ; 94 43 56 78\r
+ mov.b #2, 0x7856(r4) ; E4 43 56 78\r
+ mov.b #-1, 0x7856(r4) ; F4 43 56 78\r
+\r
+ ; All Addressing Modes to X(r4)\r
+ mov.b r5, 0x7856(r4) ; C4 45 56 78\r
+ mov.b 0x2(r5),0x7856(r4) ; D4 45 02 00 56 78\r
+ mov.b 13$, 0x7856(r4) ; D4 40 BA FF 56 78\r
+ mov.b &13$, 0x7856(r4) ; D4 42r58s03 56 78\r
+ mov.b @r5, 0x7856(r4) ; E4 45 56 78\r
+ mov.b @r5+, 0x7856(r4) ; F4 45 56 78\r
+ mov.b #0x3412,0x7856(r4) ; F4 40 12 34 56 78\r
+\r
+ ; Special Constants Mode to Register R8\r
+14$: mov.b #4, r8 ; 68 42\r
+ mov.b #8, r8 ; 78 42\r
+ mov.b #0, r8 ; 48 43\r
+ mov.b #1, r8 ; 58 43\r
+ mov.b #2, r8 ; 68 43\r
+ mov.b #-1, r8 ; 78 43\r
+\r
+ ; All Addressing Modes to Register R8\r
+ mov.b r5, r8 ; 48 45\r
+ mov.b 0x2(r5),r8 ; 58 45 02 00\r
+ mov.b 14$, r8 ; 58 40 EC FF\r
+ mov.b &14$, r8 ; 58 42rB6s03\r
+ mov.b @r5, r8 ; 68 45\r
+ mov.b @r5+, r8 ; 78 45\r
+ mov.b #0x3412,r8 ; 78 40 12 34\r
+\r
+ ; Special Constants Mode to Register 0x7856(R8)\r
+ mov.b #4, 0x7856(r8) ; E8 42 56 78\r
+ mov.b #8, 0x7856(r8) ; F8 42 56 78\r
+ mov.b #0, 0x7856(r8) ; C8 43 56 78\r
+ mov.b #1, 0x7856(r8) ; D8 43 56 78\r
+ mov.b #2, 0x7856(r8) ; E8 43 56 78\r
+ mov.b #-1, 0x7856(r8) ; F8 43 56 78\r
+\r
+ ; All Addressing Modes to X(r8)\r
+ mov.b r5, 0x7856(r8) ; C8 45 56 78\r
+ mov.b 0x2(r5),0x7856(r8) ; D8 45 02 00 56 78\r
+ mov.b 4$, 0x7856(r8) ; D8 40 E0 FC 56 78\r
+ mov.b &14$, 0x7856(r8) ; D8 42rB6s03 56 78\r
+ mov.b @r5, 0x7856(r8) ; E8 45 56 78\r
+ mov.b @r5+, 0x7856(r8) ; F8 45 56 78\r
+ mov.b #0x3412,0x7856(r8) ; F8 40 12 34 56 78\r
+\r
+ ; Special Constants Mode to 6$\r
+ mov.b #4, 16$ ; E0 42 78 00\r
+ mov.b #8, 16$ ; F0 42 74 00\r
+ mov.b #0, 16$ ; C0 43 70 00\r
+ mov.b #1, 16$ ; D0 43 6C 00\r
+ mov.b #2, 16$ ; E0 43 68 00\r
+ mov.b #-1, 16$ ; F0 43 64 00\r
+\r
+ ; All Addressing Modes to 6$\r
+ mov.b r5, 16$ ; C0 45 60 00\r
+ mov.b 0x2(r5),16$ ; D0 45 02 00 5A 00\r
+ mov.b 15$, 16$ ; D0 40 54 00 54 00\r
+ mov.b &15$, 16$ ; D0 42r8Cs04 4E 00\r
+ mov.b @r5, 16$ ; E0 45 4A 00\r
+ mov.b @r5+, 16$ ; F0 45 46 00\r
+ mov.b #0x3412,16$ ; F0 40 12 34 40 00\r
+\r
+ ; Special Constants Mode to &6$\r
+ mov.b #4, &16$ ; E2 42r8Es04\r
+ mov.b #8, &16$ ; F2 42r8Es04\r
+ mov.b #0, &16$ ; C2 43r8Es04\r
+ mov.b #1, &16$ ; D2 43r8Es04\r
+ mov.b #2, &16$ ; E2 43r8Es04\r
+ mov.b #-1, &16$ ; F2 43r8Es04\r
+\r
+ ; All Addressing Modes to &6$\r
+ mov.b r5, &16$ ; C2 45r8Es04\r
+ mov.b 0x2(r5),&16$ ; D2 45 02 00r8Es04\r
+ mov.b 15$, &16$ ; D2 40 18 00r8Es04\r
+ mov.b &15$, &16$ ; D2 42r8Cs04r8Es04\r
+ mov.b @r5, &16$ ; E2 45r8Es04\r
+ mov.b @r5+, &16$ ; F2 45r8Es04\r
+ mov.b #0x3412,&16$ ; F2 40 12 34r8Es04\r
+\r
+15$: .word 0 ; 00 00\r
+16$: .word 0 ; 00 00\r
+\r
+\r
+ .sbttl Emulated Modes with R4/R8\r
+\r
+ ; Special Constants Mode to @r4\r
+17$: mov.b #4, @r4 ; E4 42 00 00\r
+ mov.b #8, @r4 ; F4 42 00 00\r
+ mov.b #0, @r4 ; C4 43 00 00\r
+ mov.b #1, @r4 ; D4 43 00 00\r
+ mov.b #2, @r4 ; E4 43 00 00\r
+ mov.b #-1, @r4 ; F4 43 00 00\r
+\r
+ ; All Addressing Modes to @r4\r
+ mov.b r5, @r4 ; C4 45 00 00\r
+ mov.b 0x2(r5),@r4 ; D4 45 02 00 00 00\r
+ mov.b 17$, @r4 ; D4 40 DC FF 00 00\r
+ mov.b &17$, @r4 ; D4 42r90s04 00 00\r
+ mov.b @r5, @r4 ; E4 45 00 00\r
+ mov.b @r5+, @r4 ; F4 45 00 00\r
+ mov.b #0x3412,@r4 ; F4 40 12 34 00 00\r
+\r
+ ; Special Constants Mode to @r4+\r
+ mov.b #4, @r4+ ; E4 42 00 00 14 53\r
+ mov.b #8, @r4+ ; F4 42 00 00 14 53\r
+ mov.b #0, @r4+ ; C4 43 00 00 14 53\r
+ mov.b #1, @r4+ ; D4 43 00 00 14 53\r
+ mov.b #2, @r4+ ; E4 43 00 00 14 53\r
+ mov.b #-1, @r4+ ; F4 43 00 00 14 53\r
+\r
+ ; All Addressing Modes to @r4+\r
+ mov.b r5, @r4+ ; C4 45 00 00 14 53\r
+ mov.b 0x2(r5),@r4+ ; D4 45 02 00 00 00\r
+ mov.b 17$, @r4+ ; D4 40 90 FF 00 00\r
+ mov.b &17$, @r4+ ; D4 42r90s04 00 00\r
+ mov.b @r5, @r4+ ; E4 45 00 00 14 53\r
+ mov.b @r5+, @r4+ ; F4 45 00 00 14 53\r
+ mov.b #0x3412,@r4+ ; F4 40 12 34 00 00\r
+\r
+ ; Special Constants Mode to @r8\r
+18$: mov.b #4, @r8 ; E8 42 00 00\r
+ mov.b #8, @r8 ; F8 42 00 00\r
+ mov.b #0, @r8 ; C8 43 00 00\r
+ mov.b #1, @r8 ; D8 43 00 00\r
+ mov.b #2, @r8 ; E8 43 00 00\r
+ mov.b #-1, @r8 ; F8 43 00 00\r
+\r
+ ; All Addressing Modes to @r8\r
+ mov.b r5, @r8 ; C8 45 00 00\r
+ mov.b 0x2(r5),@r8 ; D8 45 02 00 00 00\r
+ mov.b 18$, @r8 ; D8 40 DC FF 00 00\r
+ mov.b &18$, @r8 ; D8 42r22s05 00 00\r
+ mov.b @r5, @r8 ; E8 45 00 00\r
+ mov.b @r5+, @r8 ; F8 45 00 00\r
+ mov.b #0x3412,@r8 ; F8 40 12 34 00 00\r
+\r
+ ; Special Constants Mode to @r8+\r
+ mov.b #4, @r8+ ; E8 42 00 00 18 53\r
+ mov.b #8, @r8+ ; F8 42 00 00 18 53\r
+ mov.b #0, @r8+ ; C8 43 00 00 18 53\r
+ mov.b #1, @r8+ ; D8 43 00 00 18 53\r
+ mov.b #2, @r8+ ; E8 43 00 00 18 53\r
+ mov.b #-1, @r8+ ; F8 43 00 00 18 53\r
+\r
+ ; All Addressing Modes to @r8+\r
+ mov.b r5, @r8+ ; C8 45 00 00 18 53\r
+ mov.b 0x2(r5),@r8+ ; D8 45 02 00 00 00\r
+ mov.b 18$, @r8+ ; D8 40 90 FF 00 00\r
+ mov.b &18$, @r8+ ; D8 42r22s05 00 00\r
+ mov.b @r5, @r8+ ; E8 45 00 00 18 53\r
+ mov.b @r5+, @r8+ ; F8 45 00 00 18 53\r
+ mov.b #0x3412,@r8+ ; F8 40 12 34 00 00\r
+\r
+\r
+\r
+ .sbttl 'RLX' Instruction Tests\r
+\r
+ ; Test Addressing Modes for Single Operand Instructions\r
+\r
+ .sbttl Word RLX Check\r
+ \r
+RLX: ; Check all Registers\r
+ rla r0 ; 00 50\r
+ rla r1 ; 01 51\r
+ rla r2 ; 02 52\r
+ rla r3 ; 03 53\r
+ rla r4 ; 04 54\r
+ rla r5 ; 05 55\r
+ rla r6 ; 06 56\r
+ rla r7 ; 07 57\r
+ rla r8 ; 08 58\r
+ rla r9 ; 09 59\r
+ rla r10 ; 0A 5A\r
+ rla r11 ; 0B 5B\r
+ rla r12 ; 0C 5C\r
+ rla r13 ; 0D 5D\r
+ rla r14 ; 0E 5E\r
+ rla r15 ; 0F 5F\r
+\r
+ rla pc ; 00 50\r
+ rla sp ; 01 51\r
+ rla sr ; 02 52\r
+ rla cg1 ; 02 52\r
+ rla cg2 ; 03 53\r
+\r
+ ; All Addressing Modes\r
+1$: rla r5 ; 05 55\r
+ rla 0x2(r5) ; 95 55 02 00 02 00\r
+ rla 1$ ; 90 50 F6 FF F4 FF\r
+ rla &1$ ; 92 52rDEs05rDEs05\r
+ rla @r5 ; A5 55 00 00\r
+ rla @r5+ ; B5 55 FE FF\r
+; rla #0x3412 ; 92 52 12 34 12 34\r
+\r
+ ; Alternate Forms\r
+ rla (r5) ; A5 55 00 00\r
+ rla (r5)+ ; B5 55 FE FF\r
+\r
+\r
+ .sbttl BYTE RLX Check\r
+\r
+ ; Check all Registers\r
+ rla.b r0 ; 40 50\r
+ rla.b r1 ; 41 51\r
+ rla.b r2 ; 42 52\r
+ rla.b r3 ; 43 53\r
+ rla.b r4 ; 44 54\r
+ rla.b r5 ; 45 55\r
+ rla.b r6 ; 46 56\r
+ rla.b r7 ; 47 57\r
+ rla.b r8 ; 48 58\r
+ rla.b r9 ; 49 59\r
+ rla.b r10 ; 4A 5A\r
+ rla.b r11 ; 4B 5B\r
+ rla.b r12 ; 4C 5C\r
+ rla.b r13 ; 4D 5D\r
+ rla.b r14 ; 4E 5E\r
+ rla.b r15 ; 4F 5F\r
+\r
+ rla.b pc ; 40 50\r
+ rla.b sp ; 41 51\r
+ rla.b sr ; 42 52\r
+ rla.b cg1 ; 42 52\r
+ rla.b cg2 ; 43 53\r
+\r
+ ; All Addressing Modes\r
+11$: rla.b r5 ; 45 55\r
+ rla.b 0x2(r5) ; D5 55 02 00 02 00\r
+ rla.b 11$ ; D0 50 F6 FF F4 FF\r
+ rla.b &11$ ; D2 52r2Cs06r2Cs06\r
+ rla.b @r5 ; E5 55 00 00\r
+ rla.b @r5+ ; F5 55 FF FF\r
+; rla.b #0x3412 ; D2 52 12 34 12 34\r
+\r
+ ; Alternate Forms\r
+ rla.b (r5) ; E5 55 00 00\r
+ rla.b (r5)+ ; F5 55 FF FF\r
+\r
+\r
+\r
+ .sbttl 'BRA' Instruction Tests\r
+\r
+BRA: ; Check all Registers\r
+ bra r0 ; 00 40\r
+ bra r1 ; 00 41\r
+ bra r2 ; 00 42\r
+ bra r3 ; 00 43\r
+ bra r4 ; 00 44\r
+ bra r5 ; 00 45\r
+ bra r6 ; 00 46\r
+ bra r7 ; 00 47\r
+ bra r8 ; 00 48\r
+ bra r9 ; 00 49\r
+ bra r10 ; 00 4A\r
+ bra r11 ; 00 4B\r
+ bra r12 ; 00 4C\r
+ bra r13 ; 00 4D\r
+ bra r14 ; 00 4E\r
+ bra r15 ; 00 4F\r
+\r
+ bra pc ; 00 40\r
+ bra sp ; 00 41\r
+ bra sr ; 00 42\r
+ bra cg1 ; 00 42\r
+ bra cg2 ; 00 43\r
+\r
+ ; All Addressing Modes\r
+1$: bra r5 ; 00 45\r
+ bra 0x2(r5) ; 10 45 02 00\r
+ bra 1$ ; 10 40 F8 FF\r
+ bra &1$ ; 10 42r7As06\r
+ bra @r5 ; 20 45\r
+ bra @r5+ ; 30 45\r
+; bra #0x3412 ; 30 40 12 34\r
+\r
+ ; Alternate Forms\r
+ bra (r5) ; 20 45\r
+ bra (r5)+ ; 30 45\r
+\r
+\r
+\r
+ .sbttl 'SOP' Instruction Tests\r
+\r
+ ; Test Addressing Modes for Single Operand Instructions\r
+\r
+ .sbttl Word SOP Check\r
+\r
+SOP: ; Check all Registers\r
+ rrc r0 ; 00 10\r
+ rrc r1 ; 01 10\r
+ rrc r2 ; 02 10\r
+ rrc r3 ; 03 10\r
+ rrc r4 ; 04 10\r
+ rrc r5 ; 05 10\r
+ rrc r6 ; 06 10\r
+ rrc r7 ; 07 10\r
+ rrc r8 ; 08 10\r
+ rrc r9 ; 09 10\r
+ rrc r10 ; 0A 10\r
+ rrc r11 ; 0B 10\r
+ rrc r12 ; 0C 10\r
+ rrc r13 ; 0D 10\r
+ rrc r14 ; 0E 10\r
+ rrc r15 ; 0F 10\r
+\r
+ rrc pc ; 00 10\r
+ rrc sp ; 01 10\r
+ rrc sr ; 02 10\r
+ rrc cg1 ; 02 10\r
+ rrc cg2 ; 03 10\r
+\r
+ ; All Addressing Modes\r
+1$: rrc r5 ; 05 10\r
+ rrc 0x2(r5) ; 15 10 02 00\r
+ rrc 1$ ; 10 10 F8 FF\r
+ rrc &1$ ; 10 12rBAs06\r
+ rrc @r5 ; 25 10\r
+ rrc @r5+ ; 35 10\r
+; rrc #0x3412 ; 10 12 12 34\r
+\r
+ ; Alternate Forms\r
+ rrc (r5) ; 25 10\r
+ rrc (r5)+ ; 35 10\r
+\r
+ rrc (pc)+ ; 30 10\r
+2$: .word 0x3412 ; 12 34\r
+\r
+\r
+ .sbttl BYTE SOP Check\r
+\r
+ ; Check all Registers\r
+ rrc.b r0 ; 40 10\r
+ rrc.b r1 ; 41 10\r
+ rrc.b r2 ; 42 10\r
+ rrc.b r3 ; 43 10\r
+ rrc.b r4 ; 44 10\r
+ rrc.b r5 ; 45 10\r
+ rrc.b r6 ; 46 10\r
+ rrc.b r7 ; 47 10\r
+ rrc.b r8 ; 48 10\r
+ rrc.b r9 ; 49 10\r
+ rrc.b r10 ; 4A 10\r
+ rrc.b r11 ; 4B 10\r
+ rrc.b r12 ; 4C 10\r
+ rrc.b r13 ; 4D 10\r
+ rrc.b r14 ; 4E 10\r
+ rrc.b r15 ; 4F 10\r
+\r
+ rrc.b pc ; 40 10\r
+ rrc.b sp ; 41 10\r
+ rrc.b sr ; 42 10\r
+ rrc.b cg1 ; 42 10\r
+ rrc.b cg2 ; 43 10\r
+\r
+ ; All Addressing Modes\r
+11$: rrc.b r5 ; 45 10\r
+ rrc.b 0x2(r5) ; 55 10 02 00\r
+ rrc.b 11$ ; 50 10 F8 FF\r
+ rrc.b &11$ ; 50 12rFEs06\r
+ rrc.b @r5 ; 65 10\r
+ rrc.b @r5+ ; 75 10\r
+; rrc.b #0x3412 ; 50 12 12 34\r
+\r
+ ; Alternate Forms\r
+ rrc.b (r5) ; 65 10\r
+ rrc.b (r5)+ ; 75 10\r
+\r
+ rrc.b (pc)+ ; 70 10\r
+12$: .word 0x3412 ; 12 34\r
+\r
+\r
+\r
+ .sbttl 'DST' Instruction Tests\r
+\r
+ ; Test Addressing Modes for Single Operand Instructions\r
+\r
+ .sbttl Word DST Check\r
+\r
+DST: ; Check all Registers\r
+ clr r0 ; 00 43\r
+ clr r1 ; 01 43\r
+ clr r2 ; 02 43\r
+ clr r3 ; 03 43\r
+ clr r4 ; 04 43\r
+ clr r5 ; 05 43\r
+ clr r6 ; 06 43\r
+ clr r7 ; 07 43\r
+ clr r8 ; 08 43\r
+ clr r9 ; 09 43\r
+ clr r10 ; 0A 43\r
+ clr r11 ; 0B 43\r
+ clr r12 ; 0C 43\r
+ clr r13 ; 0D 43\r
+ clr r14 ; 0E 43\r
+ clr r15 ; 0F 43\r
+\r
+ clr pc ; 00 43\r
+ clr sp ; 01 43\r
+ clr sr ; 02 43\r
+ clr cg1 ; 02 43\r
+ clr cg2 ; 03 43\r
+\r
+ ; All Addressing Modes\r
+1$: clr r5 ; 05 43\r
+ clr 0x2(r5) ; 85 43 02 00\r
+ clr 1$ ; 80 43 F8 FF\r
+ clr &1$ ; 82 43r42s07\r
+ clr @r5 ; 85 43 00 00\r
+ clr @r5+ ; 85 43 00 00 25 53\r
+; clr #0x3412 ; 82 43 12 34\r
+\r
+ ; Alternate Forms\r
+ clr (r5) ; 85 43 00 00\r
+ clr (r5)+ ; 85 43 00 00 25 53\r
+\r
+ clr (pc)+ ; 80 43 00 00 20 53\r
+2$: .word 0x3412 ; 12 34\r
+\r
+\r
+ .sbttl Byte DST Check\r
+\r
+ ; Check all Registers\r
+ clr.b r0 ; 40 43\r
+ clr.b r1 ; 41 43\r
+ clr.b r2 ; 42 43\r
+ clr.b r3 ; 43 43\r
+ clr.b r4 ; 44 43\r
+ clr.b r5 ; 45 43\r
+ clr.b r6 ; 46 43\r
+ clr.b r7 ; 47 43\r
+ clr.b r8 ; 48 43\r
+ clr.b r9 ; 49 43\r
+ clr.b r10 ; 4A 43\r
+ clr.b r11 ; 4B 43\r
+ clr.b r12 ; 4C 43\r
+ clr.b r13 ; 4D 43\r
+ clr.b r14 ; 4E 43\r
+ clr.b r15 ; 4F 43\r
+\r
+ clr.b pc ; 40 43\r
+ clr.b sp ; 41 43\r
+ clr.b sr ; 42 43\r
+ clr.b cg1 ; 42 43\r
+ clr.b cg2 ; 43 43\r
+\r
+ ; All Addressing Modes\r
+3$: clr.b r5 ; 45 43\r
+ clr.b 0x2(r5) ; C5 43 02 00\r
+ clr.b 3$ ; C0 43 F8 FF\r
+ clr.b &3$ ; C2 43r96s07\r
+ clr.b @r5 ; C5 43 00 00\r
+ clr.b @r5+ ; C5 43 00 00 15 53\r
+; clr.b #0x3412 ; C2 43 12 34\r
+\r
+ ; Alternate Forms\r
+ clr.b (r5) ; C5 43 00 00\r
+ clr.b (r5)+ ; C5 43 00 00 15 53\r
+\r
+ clr.b (pc)+ ; C0 43 00 00 20 53\r
+4$: .word 0x3412 ; 12 34\r
+\r
+\r
+ .sbttl 'JXX' Instruction Tests\r
+\r
+ .org 0x0800\r
+JXX:\r
+ \r
+1$:\r
+ jne 1$ ; FF 23\r
+ jnz 1$ ; FE 23\r
+ jeq 1$ ; FD 27\r
+ jz 1$ ; FC 27\r
+ jnc 1$ ; FB 2B\r
+ jlo 1$ ; FA 2B\r
+ jc 1$ ; F9 2F\r
+ jhs 1$ ; F8 2F\r
+ jn 1$ ; F7 33\r
+ jge 1$ ; F6 37\r
+ jl 1$ ; F5 3B\r
+ jmp 1$ ; F4 3F\r
+\r
+ jne 2$ ; 0B 20\r
+ jnz 2$ ; 0A 20\r
+ jeq 2$ ; 09 24\r
+ jz 2$ ; 08 24\r
+ jnc 2$ ; 07 28\r
+ jlo 2$ ; 06 28\r
+ jc 2$ ; 05 2C\r
+ jhs 2$ ; 04 2C\r
+ jn 2$ ; 03 30\r
+ jge 2$ ; 02 34\r
+ jl 2$ ; 01 38\r
+ jmp 2$ ; 00 3C\r
+2$:\r
+\r
+ .org 0x0BFE\r
+\r
+ jmp 1$ ; 00 3E\r
+ jmp 3$ ; FF 3D\r
+\r
+ .org 0x1000\r
+\r
+3$:\r
+\r
+\r
+\r
+ .sbttl Basic All Instruction Test\r
+\r
+ALL:\r
+ ; DOP\r
+ mov r0,r0 ; 00 40\r
+ add r0,r0 ; 00 50\r
+ addc r0,r0 ; 00 60\r
+ sbb r0,r0 ; 00 70\r
+ subc r0,r0 ; 00 70\r
+ sub r0,r0 ; 00 80\r
+ cmp r0,r0 ; 00 90\r
+ dadd r0,r0 ; 00 A0\r
+ bit r0,r0 ; 00 B0\r
+ bic r0,r0 ; 00 C0\r
+ bis r0,r0 ; 00 D0\r
+ xor r0,r0 ; 00 E0\r
+ and r0,r0 ; 00 F0\r
+\r
+ mov.b r0,r0 ; 40 40\r
+ add.b r0,r0 ; 40 50\r
+ addc.b r0,r0 ; 40 60\r
+ sbb.b r0,r0 ; 40 70\r
+ subc.b r0,r0 ; 40 70\r
+ sub.b r0,r0 ; 40 80\r
+ cmp.b r0,r0 ; 40 90\r
+ dadd.b r0,r0 ; 40 A0\r
+ bit.b r0,r0 ; 40 B0\r
+ bic.b r0,r0 ; 40 C0\r
+ bis.b r0,r0 ; 40 D0\r
+ xor.b r0,r0 ; 40 E0\r
+ and.b r0,r0 ; 40 F0\r
+\r
+ mov.w r0,r0 ; 00 40\r
+ add.w r0,r0 ; 00 50\r
+ addc.w r0,r0 ; 00 60\r
+ sbb.w r0,r0 ; 00 70\r
+ subc.w r0,r0 ; 00 70\r
+ sub.w r0,r0 ; 00 80\r
+ cmp.w r0,r0 ; 00 90\r
+ dadd.w r0,r0 ; 00 A0\r
+ bit.w r0,r0 ; 00 B0\r
+ bic.w r0,r0 ; 00 C0\r
+ bis.w r0,r0 ; 00 D0\r
+ xor.w r0,r0 ; 00 E0\r
+ and.w r0,r0 ; 00 F0\r
+\r
+ ; SOP\r
+ push r0 ; 00 12\r
+ rra r0 ; 00 11\r
+ rrc r0 ; 00 10\r
+\r
+ push.b r0 ; 40 12\r
+ rra.b r0 ; 40 11\r
+ rrc.b r0 ; 40 10\r
+\r
+ push.w r0 ; 00 12\r
+ rra.w r0 ; 00 11\r
+ rrc.w r0 ; 00 10\r
+\r
+ call r0 ; 80 12\r
+ swpb r0 ; 80 10\r
+ sxt r0 ; 80 11\r
+\r
+ ; JXX\r
+ jne .+2 ; 00 20\r
+ jnz .+2 ; 00 20\r
+ jeq .+2 ; 00 24\r
+ jz .+2 ; 00 24\r
+ jnc .+2 ; 00 28\r
+ jlo .+2 ; 00 28\r
+ jc .+2 ; 00 2C\r
+ jhs .+2 ; 00 2C\r
+ jn .+2 ; 00 30\r
+ jge .+2 ; 00 34\r
+ jl .+2 ; 00 38\r
+ jmp .+2 ; 00 3C\r
+\r
+ ; DST/RLX\r
+ adc r0 ; 00 63\r
+ clr r0 ; 00 43\r
+ dadc r0 ; 00 A3\r
+ dec r0 ; 10 83\r
+ decd r0 ; 20 83\r
+ inc r0 ; 10 53\r
+ incd r0 ; 20 53\r
+ inv r0 ; 30 E3\r
+ pop r0 ; 30 41\r
+ rla r0 ; 00 50\r
+ rlc r0 ; 00 60\r
+ sbc r0 ; 00 73\r
+ tst r0 ; 00 93\r
+\r
+ adc.b r0 ; 40 63\r
+ clr.b r0 ; 40 43\r
+ dadc.b r0 ; 40 A3\r
+ dec.b r0 ; 50 83\r
+ decd.b r0 ; 60 83\r
+ inc.b r0 ; 50 53\r
+ incd.b r0 ; 60 53\r
+ inv.b r0 ; 70 E3\r
+ pop.b r0 ; 70 41\r
+ rla.b r0 ; 40 50\r
+ rlc.b r0 ; 40 60\r
+ sbc.b r0 ; 40 73\r
+ tst.b r0 ; 40 93\r
+\r
+ adc.w r0 ; 00 63\r
+ clr.w r0 ; 00 43\r
+ dadc.w r0 ; 00 A3\r
+ dec.w r0 ; 10 83\r
+ decd.w r0 ; 20 83\r
+ inc.w r0 ; 10 53\r
+ incd.w r0 ; 20 53\r
+ inv.w r0 ; 30 E3\r
+ pop.w r0 ; 30 41\r
+ rla.w r0 ; 00 50\r
+ rlc.w r0 ; 00 60\r
+ sbc.w r0 ; 00 73\r
+ tst.w r0 ; 00 93\r
+\r
+ ; BRA\r
+ bra .+2 ; 10 40 00 00\r
+\r
+ ; INH\r
+ reti ; 00 13\r
+ clrc ; 12 C3\r
+ clrn ; 02 C2\r
+ clrz ; 22 C3\r
+ setc ; 12 D3\r
+ setn ; 02 D2\r
+ setz ; 22 D3\r
+ dint ; 32 C3\r
+ eint ; 32 D3\r
+ nop ; 03 43\r
+ ret ; 30 41\r
+\r
+\r
+\r
+\r
--- /dev/null
+as430 -gloaxff t430\r
+asxscn t430.lst\r
+aslink -nxu t430\r
+asxscn -i t430.rst\r
+\r
--- /dev/null
+ .title AS430 Checks\r
+\r
+ ;\r
+ ; In area relative addressing\r
+ ;\r
+\r
+ .area Code (ABS, OVR)\r
+\r
+ .org 0x0000\r
+ mov 1$,2$ ; 90 40 10 00 10 00\r
+\r
+ .org 0x0000\r
+ mov .+0x0012,.+0x0014 ; 90 40 10 00 10 00\r
+\r
+ .org 0x0012\r
+1$: .word 0 ; 00 00\r
+2$: .word 0 ; 00 00\r
+\r
+ .org 0x0020\r
+ mov 1$,2$ ; 90 40 F0 FF F0 FF\r
+\r
+ .org 0x0020\r
+ mov .-0x000E,.-0x000C ; 90 40 F0 FF F0 FF\r
+\r
+\r
+ ;\r
+ ; Out of area relative addressing\r
+ ;\r
+\r
+ .org 0x0000\r
+ mov srcdat,dstdat ; 90 40p12q00p14q00\r
+\r
+\r
+ .area Code1 (ABS,OVR)\r
+\r
+ .org 0x0012\r
+srcdat: .word 0 ; 00 00\r
+\r
+\r
+ .area Code2 (ABS,OVR)\r
+\r
+ .org 0x0014\r
+dstdat: .word 0 ; 00 00\r
+\r
+\r
+ .area Code (ABS, OVR)\r
+\r
+ .org 0x0020\r
+ mov srcdat,dstdat ; 90 40p12q00p14q00\r
+\r
+\r
+ ;\r
+ ; In area Conditional Jumps (relative)\r
+ ;\r
+\r
+ .org 0x0000\r
+ jmp 3$ ; 08 3C\r
+\r
+ .org 0x0000\r
+ jmp .+0x0012 ; 08 3C\r
+\r
+\r
+ .org 0x0012\r
+3$:\r
+\r
+ .org 0x0020\r
+ jmp 3$ ; F8 3F\r
+\r
+ .org 0x0020\r
+ jmp .-0x000E ; F8 3F\r
+\r
+\r
+ ;\r
+ ; Out of area Conditional Jumps (relative)\r
+ ;\r
+\r
+ .org 0x0000\r
+ jmp label ;p09q3C\r
+\r
+\r
+ .area Code1 (ABS,OVR)\r
+\r
+ .org 0x0012\r
+label:\r
+\r
+\r
+ .area Code (ABS,OVR)\r
+\r
+ .org 0x0020\r
+ jmp label ;p09q3C\r
+\r
+\r
--- /dev/null
+as430 -gloaxff t430chk\r
+asxscn t430chk.lst\r
+aslink -nxu t430chk\r
+rem asxscn -i t430chk.rst\r
+\r
asgb \\r
ash8 \\r
asm8c \\r
+ aspdp11 \\r
aspic \\r
asrab \\r
asscmp \\r
rm -f asgb\r
rm -f ash8\r
rm -f asm8c\r
+ rm -f aspdp11\r
rm -f aspic\r
rm -f asrab\r
rm -f asscmp\r
rm -f asgb\r
rm -f ash8\r
rm -f asm8c\r
+ rm -f aspdp11\r
rm -f aspic\r
rm -f asrab\r
rm -f asscmp\r
SRCGB= $(ASXBAS)asgb/\r
SRCH8= $(ASXBAS)ash8/\r
SRCM8C= $(ASXBAS)asm8c/\r
+SRCPDP11= $(ASXBAS)aspdp11/\r
SRCPIC= $(ASXBAS)aspic/\r
SRCRAB= $(ASXBAS)asrab/\r
SRCSCMP= $(ASXBAS)asscmp/\r
chmod 755 $(DSTEXE)asm8c\r
\r
\r
+####################################################################\r
+# ASPDP11\r
+####################################################################\r
+\r
+ASPDP11 = pdp11adr.o pdp11mch.o pdp11pst.o\r
+\r
+ASPDP11SRC = $(addprefix $(SRCPDP11),$(ASPDP11))\r
+\r
+$(ASPDP11SRC): $(SRCMISC)alloc.h $(SRCASX)asxxxx.h $(SRCPDP11)pdp11.h\r
+\r
+aspdp11: $(ASXXSRC) $(ASPDP11SRC)\r
+ $(LD) $(LDFLAGS) $(ASXXSRC) $(ASPDP11SRC) -o aspdp11\r
+ cp aspdp11 $(DSTEXE)aspdp11\r
+ strip $(DSTEXE)aspdp11\r
+ chmod 755 $(DSTEXE)aspdp11\r
+\r
####################################################################\r
# ASPIC\r
####################################################################\r
#!/bin/sh
-(cd asxmak/linux/build && make asz80 aslink)
+#(cd asxmak/linux/build && make asz80 aslink)
+(cd asxmak/linux/build && make aspdp11 aslink)
cp asxmak/linux/exe/as* $HOME/bin
public / asxv5pxx.git / commitdiff