Add S_JSR, S_RTS, S_SYSTRAP, S_SPL

diff --git a/aspdp11/pdp11.h b/aspdp11/pdp11.h
index 7f229fb..cce31e4 100644 (file)
--- a/aspdp11/pdp11.h
+++ b/aspdp11/pdp11.h
@@ -76,11 +76,11 @@
 #define S_MOVF         57\r
 #define S_MOVFO                58\r
 #define S_MULDIV       59\r
-#define S__REG         60\r
-#define S_RTS          61\r
-#define S_SINGLE       62\r
-#define S_SOB          63\r
+#define S_RTS          60\r
+#define S_SINGLE       61\r
+#define S_SOB          62\r
 #define S_SYSTRAP      63\r
+#define S_SPL          64\r
 \r
 /*\r
  * Extended Addressing Modes\r

diff --git a/aspdp11/pdp11mch.c b/aspdp11/pdp11mch.c
index 2a3247c..bed4d15 100644 (file)
--- a/aspdp11/pdp11mch.c
+++ b/aspdp11/pdp11mch.c
@@ -69,6 +69,7 @@ struct mne *mp;
        switch (rf = mp->m_type) {\r
 \r
        case S_DOUBLE:\r
+       case S_JSR:\r
                t1 = addr(&e1, 0);\r
                v1 = aindx & 7; // check fpreg here\r
                comma(1);\r
@@ -78,7 +79,10 @@ struct mne *mp;
                /*\r
                 * Opcode Processing\r
                 */\r
-               outaw(op + ((t1 + v1) << 6) + t2 + v2);\r
+               if (rf == S_JSR && t1 != S_REG) {\r
+                       aerr();\r
+               }\r
+               outaw(op | ((t1 | v1) << 6) | t2 | v2);\r
 \r
                /*\r
                 * Source Processing\r
@@ -125,13 +129,17 @@ struct mne *mp;
                break;\r
 \r
        case S_SINGLE:\r
+       case S_RTS:\r
                t1 = addr(&e1, 0);\r
                v1 = aindx & 7; // check fpreg here\r
 \r
                /*\r
                 * Opcode Processing\r
                 */\r
-               outaw(op + t1 + v1);\r
+               if (rf == S_RTS && t1 != S_REG) {\r
+                       aerr();\r
+               }\r
+               outaw(op | t1 | v1);\r
 \r
                /*\r
                 * Source/Destination Processing\r
@@ -156,210 +164,6 @@ struct mne *mp;
                }\r
                break;\r
 \r
-#if 0\r
-       case S_PSH:\r
-               t1 = addr(&e1);\r
-               v1 = aindx & 0x000F;\r
-\r
-               /*\r
-                * Special Constant Processing\r
-                */\r
-               if ((t1 == S_IMM) && is_abs(&e1)) {\r
-                       switch (e1.e_addr) {\r
-                       case (a_uint)  4:       t1 = S_REG;     op += 0x0020;   v1 = 2;         break;\r
-                       case (a_uint)  8:       t1 = S_REG;     op += 0x0030;   v1 = 2;         break;\r
-                       case (a_uint)  0:       t1 = S_REG;     op += 0x0000;   v1 = 3;         break;\r
-                       case (a_uint)  1:       t1 = S_REG;     op += 0x0010;   v1 = 3;         break;\r
-                       case (a_uint)  2:       t1 = S_REG;     op += 0x0020;   v1 = 3;         break;\r
-                       case (a_uint) ~0:       t1 = S_REG;     op += 0x0030;   v1 = 3;         break;\r
-                       default:                                                                break;\r
-                       }\r
-               }\r
-\r
-               /*\r
-                * Opcode Processing\r
-                */\r
-               /* SRC */\r
-               switch(t1) {\r
-               case S_REG:     op += 0x0000 + v1;      break;  /*      Rn      As=0            */\r
-               case S_RIDX:    op += 0x0010 + v1;      break;  /*      X(Rn)   As=1            */\r
-               case S_SYM:     op += 0x0010;           break;  /*      addr    As=1, Sreg=PC   */\r
-               case S_ABS:     op += 0x0210;           break;  /*      &Addr   As=1, Sreg=SR   */\r
-               case S_RIN:     op += 0x0020 + v1;      break;  /*      @Rn     As=2            */\r
-               case S_RIN2:    op += 0x0030 + v1;      break;  /*      @Rn+    As=3            */\r
-               case S_IMM:     op += 0x0030;           break;  /*      #N      As=3, Sreg=PC   */\r
-               default:        aerr();                 break;\r
-               }\r
-\r
-               outaw(op);\r
-               /*\r
-                * Source Processing\r
-                */\r
-               switch(t1) {\r
-               case S_REG:                             break;  /*      Rn      As=0            */\r
-               case S_RIDX:    outrw(&e1, 0);          break;  /*      X(Rn)   As=1            */\r
-               case S_SYM:     if (mchpcr(&e1)) {\r
-                                       e1.e_addr -= dot.s_addr;\r
-                                       outaw(e1.e_addr);\r
-                               } else {\r
-                                       outrw(&e1, R_PCR0);\r
-                               }\r
-                                                       break;  /*      addr    As=1, Sreg=PC   */\r
-               case S_ABS:     outrw(&e1, 0);          break;  /*      &Addr   As=1, Sreg=SR   */\r
-               case S_RIN:                             break;  /*      @Rn     As=2            */\r
-               case S_RIN2:                            break;  /*      @Rn+    As=3            */\r
-               case S_IMM:     outrw(&e1, 0);          break;  /*      #N      As=3, Sreg=PC   */\r
-               default:        aerr();                 break;\r
-               }\r
-               break;\r
-\r
-       case S_DST:\r
-               t1 = addr(&e1);\r
-               v1 = (aindx & 0x000F);\r
-\r
-               /*\r
-                * Opcode Processing\r
-                */\r
-               /* DSTDST */\r
-               switch(t1) {\r
-               case S_REG:     op += 0x0000 + v1;      break;  /*      Rn      Ad=0            */\r
-               case S_RIDX:    op += 0x0080 + v1;      break;  /*      X(Rn)   Ad=1            */\r
-               case S_SYM:     op += 0x0080;           break;  /*      addr    Ad=1, Sreg=PC   */\r
-               case S_IMM:                                     /*      #N      ==>> &Addr      */\r
-               case S_ABS:     op += 0x0082;           break;  /*      &Addr   Ad=1, Sreg=SR   */\r
-               case S_RIN:     op += 0x0080 + v1;      break;  /*      @Rn     Ad=1            */\r
-               case S_RIN2:    op += 0x0080 + v1;      break;  /*      @Rn+    Ad=1            */\r
-               default:        aerr();                 break;\r
-               }\r
-\r
-               outaw(op);\r
-               /*\r
-                * Destination Processing\r
-                */\r
-               switch(t1) {\r
-               case S_REG:                             break;  /*      Rn      Ad=0            */\r
-               case S_RIDX:    outrw(&e1, 0);          break;  /*      X(Rn)   Ad=1            */\r
-               case S_SYM:     if (mchpcr(&e1)) {\r
-                                       e1.e_addr -= dot.s_addr;\r
-                                       outaw(e1.e_addr);\r
-                               } else {\r
-                                       outrw(&e1, R_PCR0);\r
-                               }\r
-                                                       break;  /*      addr    Ad=1, Sreg=PC   */\r
-               case S_IMM:     aerr();                         /*      #N      ==>> &Addr      */\r
-               case S_ABS:     outrw(&e1, 0);          break;  /*      &Addr   Ad=1, Sreg=SR   */\r
-               case S_RIN:     outaw(0);               break;  /*      @Rn     Ad=1            */\r
-               case S_RIN2:    outaw(0);                       /*      @Rn+    Ad=1            */\r
-                               if ((op & 0x0040) && (v1 != 0)) {\r
-                                       outaw(0x5310 + v1);             /*      add     #1,Rn           */\r
-                               } else {\r
-                                       outaw(0x5320 + v1);     ;       /*      add     #2,Rn           */\r
-                               }\r
-                                                       break;\r
-               default:        aerr();                 break;\r
-               }\r
-               break;\r
-\r
-       case S_RLX:\r
-               t1 = addr(&e1);\r
-               v1 = (aindx & 0x000F) << 8;\r
-\r
-               /*\r
-                * Duplicate Argument\r
-                */\r
-               e2.e_mode = e1.e_mode;\r
-               e2.e_flag = e1.e_flag;\r
-               e2.e_addr = e1.e_addr;\r
-               e2.e_base.e_sp = e1.e_base.e_sp;\r
-               e2.e_rlcf = e1.e_rlcf;\r
-\r
-               t2 = t1;\r
-               v2 = (aindx & 0x000F);\r
-\r
-               /*\r
-                * Opcode Processing\r
-                */\r
-               /* DOPSRC */\r
-               switch(t1) {\r
-               case S_REG:     op += 0x0000 + v1;      break;  /*      Rn      As=0            */\r
-               case S_RIDX:    op += 0x0010 + v1;      break;  /*      X(Rn)   As=1            */\r
-               case S_SYM:     op += 0x0010;           break;  /*      addr    As=1, Sreg=PC   */\r
-               case S_IMM:                                     /*      #N      ==>> &Addr      */\r
-               case S_ABS:     op += 0x0210;           break;  /*      &Addr   As=1, Sreg=SR   */\r
-               case S_RIN:     op += 0x0020 + v1;      break;  /*      @Rn     As=2            */\r
-               case S_RIN2:    op += 0x0030 + v1;      break;  /*      @Rn+    As=3            */\r
-               default:        aerr();                 break;\r
-               }\r
-\r
-               /* DOPDST */\r
-               switch(t2) {\r
-               case S_REG:     op += 0x0000 + v2;      break;  /*      Rn      Ad=0            */\r
-               case S_RIDX:    op += 0x0080 + v2;      break;  /*      X(Rn)   Ad=1            */\r
-               case S_SYM:     op += 0x0080;           break;  /*      addr    Ad=1, Sreg=PC   */\r
-               case S_IMM:                                     /*      #N      ==>> &Addr      */\r
-               case S_ABS:     op += 0x0082;           break;  /*      &Addr   Ad=1, Sreg=SR   */\r
-               case S_RIN:     op += 0x0080 + v2;      break;  /*      @Rn     Ad=1            */\r
-               case S_RIN2:    op += 0x0080 + v2;      break;  /*      @Rn+    Ad=1            */\r
-               default:        aerr();                 break;\r
-               }\r
-\r
-               outaw(op);\r
-               /*\r
-                * Source Processing\r
-                */\r
-               switch(t1) {\r
-               case S_REG:                             break;  /*      Rn      As=0            */\r
-               case S_RIDX:    outrw(&e1, 0);          break;  /*      X(Rn)   As=1            */\r
-               case S_SYM:     if (mchpcr(&e1)) {\r
-                                       e1.e_addr -= dot.s_addr;\r
-                                       outaw(e1.e_addr);\r
-                               } else {\r
-                                       outrw(&e1, R_PCR0);\r
-                               }\r
-                                                       break;  /*      addr    As=1, Sreg=PC   */\r
-               case S_IMM:                                     /*      #N      ==>> &Addr      */\r
-               case S_ABS:     outrw(&e1, 0);          break;  /*      &Addr   As=1, Sreg=SR   */\r
-               case S_RIN:                             break;  /*      @Rn     As=2            */\r
-               case S_RIN2:                            break;  /*      @Rn+    As=3            */\r
-               default:        aerr();                 break;\r
-               }\r
-               /*\r
-                * Destination Processing\r
-                */\r
-               switch(t2) {\r
-               case S_REG:                             break;  /*      Rn      Ad=0            */\r
-               case S_RIDX:    outrw(&e2, 0);          break;  /*      X(Rn)   Ad=1            */\r
-               case S_SYM:     if (mchpcr(&e2)) {\r
-                                       e2.e_addr -= dot.s_addr;\r
-                                       outaw(e2.e_addr);\r
-                               } else {\r
-                                       outrw(&e2, R_PCR0);\r
-                               }\r
-                                                       break;  /*      addr    Ad=1, Sreg=PC   */\r
-               case S_IMM:     aerr();                         /*      #N      ==>> &Addr      */\r
-               case S_ABS:     outrw(&e2, 0);          break;  /*      &Addr   Ad=1, Sreg=SR   */\r
-               case S_RIN:     outaw(0);               break;  /*      @Rn     Ad=1            */\r
-               case S_RIN2:                                    /*      @Rn+    Ad=1            */\r
-                               if (rf == S_RLX) {\r
-                                       if (op & 0x0040) {\r
-                                               outaw(~0);      /*      RLX.b   @Rn+,-1(Rn)     */\r
-                                       } else {\r
-                                               outaw(~1);      /*      RLX.w   @Rn+,-2(Rn)     */\r
-                                       }\r
-                               } else {\r
-                                       outaw(0);\r
-                                       if ((op & 0x0040) && (v2 != 0)) {\r
-                                               outaw(0x5310 + v2);     /*      add     #1,Rn           */\r
-                                       } else {\r
-                                               outaw(0x5320 + v2);     /*      add     #2,Rn           */\r
-                                       }\r
-                               }\r
-                                                       break;\r
-               default:        aerr();                 break;\r
-               }\r
-               break;\r
-#endif\r
-\r
        case S_INH:\r
                outaw(op);\r
                break;\r
@@ -371,7 +175,7 @@ struct mne *mp;
                        v1 >>= 1;\r
                        if ((v1 < -128) || (v1 > 127))\r
                                aerr();\r
-                       outaw(op + (v1 & 0x00FF));\r
+                       outaw(op | (v1 & 0x00FF));\r
                } else {\r
                        outrb(&e1, R_PCR);\r
                        outab(op >> 8);\r
@@ -380,6 +184,16 @@ struct mne *mp;
                        rerr();\r
                break;\r
 \r
+       case S_SYSTRAP:\r
+       case S_SPL:\r
+               v1 = (int) absexpr();\r
+               if (v1 & (rf == S_SPL ? ~7 : ~0xff)) {\r
+                       aerr();\r
+                       v1 = 0;\r
+               }\r
+               outaw(op | v1);\r
+               break;\r
+\r
        default:\r
                opcycles = OPCY_ERR;\r
                err('o');\r

diff --git a/aspdp11/pdp11pst.c b/aspdp11/pdp11pst.c
index 5a78497..90ce68c 100644 (file)
--- a/aspdp11/pdp11pst.c
+++ b/aspdp11/pdp11pst.c
@@ -338,7 +338,7 @@ struct      mne     mne[] = {
        /* simple operand */\r
 \r
     {  NULL,   "sys",          S_SYSTRAP,      0,      0104400 },\r
-    {  NULL,   "spl",          S_SYSTRAP,      0,      0000230 },\r
+    {  NULL,   "spl",          S_SPL,          0,      0000230 },\r
 \r
        /* flag-setting */\r
 \r

diff --git a/aspdp11/test/crt0.asm b/aspdp11/test/crt0.asm
index 8c14136..0717e1d 100644 (file)
--- a/aspdp11/test/crt0.asm
+++ b/aspdp11/test/crt0.asm
@@ -23,11 +23,11 @@ start:
 2$: ;1:
        mov     r0,4(sp)
        mov     r0,_environ
-;      jsr     pc,_main
+       jsr     pc,_main
        cmp     (sp)+,(sp)+
        mov     r0,(sp)
-;      jsr     pc,*$_exit
-;      sys     exit
+       jsr     pc,*#_exit
+       sys     exit
 
 .area BSS ;.bss
 _environ: