/*\r
* Symbol types.\r
*/\r
-#define S_INH 50 /* One byte */\r
-#define S_RST 51 /* Restart */\r
-#define S_ADI 52 /* One byte immediate */\r
-#define S_ADD 53 /* One reg. */\r
-#define S_JMP 54 /* Jumps, calls, etc. */\r
-#define S_INR 55 /* Reg. dest. */\r
-#define S_LXI 56 /* Word immediate */\r
-#define S_LDAX 57 /* B or D */\r
-#define S_INX 58 /* Word reg. dest. */\r
-#define S_PUSH 59 /* Push, pop */\r
-#define S_MOV 60 /* Mov */\r
-#define S_MVI 61 /* Mvi */\r
-#define S_REG 62 /* Registers */\r
+#define S_ANDSZ 50\r
+#define S_ACC 51\r
+#define S_ACCMEM 52\r
+#define S_BIT 53\r
+#define S_CPU 54\r
+#define S_DRSZ 55\r
+#define S_FIXED 56\r
+#define S_IFBNE 57\r
+#define S_IFEQ 58\r
+#define S_IFNE 59\r
+#define S_JMPL_JSRL 60\r
+#define S_JMP_JSR 61\r
+#define S_JP 62\r
+#define S_LD 63\r
+#define S_X 64\r
\r
/*\r
* Other\r
*/\r
-#define S_FLAG 70\r
+//#define S_FLAG 70\r
\r
/*\r
* Registers.\r
*/\r
-#define B 0\r
-#define C 1\r
-#define D 2\r
-#define E 3\r
-#define H 4\r
-#define L 5\r
-#define M 6\r
-#define A 7\r
-#define SP 8\r
-#define PSW 9\r
+//#define B 0\r
+//#define C 1\r
+//#define D 2\r
+//#define E 3\r
+//#define H 4\r
+//#define L 5\r
+//#define M 6\r
+//#define A 7\r
+//#define SP 8\r
+//#define PSW 9\r
\r
/* machine dependent functions */\r
\r
#include "asxxxx.h"\r
#include "lcop8.h"\r
\r
-char *cpu = "Intel 8085";\r
-char *dsft = "asm";\r
-\r
-/*\r
- * Opcode Cycle Definitions\r
- */\r
-#define OPCY_SDP ((char) (0xFF))\r
-#define OPCY_ERR ((char) (0xFE))\r
+// asl includes\r
+#include "asmdef.h"\r
+#include "codecop8.h"\r
\r
-/* OPCY_NONE ((char) (0x80)) */\r
-/* OPCY_MASK ((char) (0x7F)) */\r
-\r
-#define UN ((char) (OPCY_NONE | 0x00))\r
-\r
-/*\r
- * 8085 Cycle Count\r
- *\r
- * opcycles = i85pg1[opcode]\r
- */\r
-static char i85pg1[256] = {\r
-/*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */\r
-/*--*--* - - - - - - - - - - - - - - - - */\r
-/*00*/ 4,10, 7, 6, 4, 4, 7, 4,10,10, 7, 6, 4, 4, 7, 4,\r
-/*10*/ 7,10, 7, 6, 4, 4, 7, 4,10,10, 7, 6, 4, 4, 7, 4,\r
-/*20*/ 4,10,16, 6, 4, 4, 7, 4,10,10,16, 6, 4, 4, 7, 4,\r
-/*30*/ 4,10,13, 6,10,10,10, 4,10,10,13, 6, 4, 4, 7, 4,\r
-/*40*/ 4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,\r
-/*50*/ 4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,\r
-/*60*/ 4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,\r
-/*70*/ 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,\r
-/*80*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\r
-/*90*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\r
-/*A0*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\r
-/*B0*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\r
-/*C0*/ 12,10,10,10,18,12, 7,12,12,10,10,12,18,18, 7,12,\r
-/*D0*/ 12,10,10,10,18,12, 7,12,12,10,10,10,18,10, 7,12,\r
-/*E0*/ 12,10,10,16,18,12, 7,12,12, 6,10, 4,18,10, 7,12,\r
-/*F0*/ 12,10,10, 4,18,12, 7,12,12, 6,10, 4,18,10, 7,12\r
-};\r
+char *cpu = "asl-cop8";\r
+char *dsft = "asm";\r
\r
/*\r
* Process machine ops.\r
machine(mp)\r
struct mne *mp;\r
{\r
+#if 1\r
+ abort();\r
+#else\r
unsigned op, rd, rs;\r
struct expr e;\r
\r
if (opcycles == OPCY_NONE) {\r
opcycles = i85pg1[cb[0] & 0xFF];\r
}\r
-}\r
-\r
-/*\r
- * Output a | (b<<3);\r
- */\r
-VOID\r
-out3(a, b)\r
-int a;\r
-int b;\r
-{\r
- outab(a | (b<<3));\r
-}\r
-\r
-/*\r
- * Make sure that `r' is usable as a\r
- * register pair specifier. The extra\r
- * register (code 3) is `s'.\r
- */\r
-int\r
-regpair(r, s)\r
-int r;\r
-int s;\r
-{\r
- if (r < M) {\r
- if (r&01)\r
- aerr();\r
- } else if (r == s)\r
- r = 6;\r
- else\r
- aerr();\r
- return (r);\r
-}\r
-\r
-/*\r
- * Read a register name.\r
- */\r
-int\r
-reg()\r
-{\r
- struct mne *mp;\r
- char id[NCPS];\r
-\r
- getid(id, -1);\r
- if ((mp = mlookup(id))==NULL || mp->m_type!=S_REG) {\r
- aerr();\r
- return (0);\r
- }\r
- return ((int) mp->m_valu);\r
+#endif\r
}\r
\r
/*\r
* Byte Order\r
*/\r
hilo = 0;\r
+ asmdef_init();\r
+ codecop8_init();\r
}\r
\r
/* 8080/8085 */\r
\r
- { NULL, "b", S_REG, 0, B },\r
- { NULL, "c", S_REG, 0, C },\r
- { NULL, "bc", S_REG, 0, B },\r
- { NULL, "d", S_REG, 0, D },\r
- { NULL, "e", S_REG, 0, E },\r
- { NULL, "de", S_REG, 0, D },\r
- { NULL, "h", S_REG, 0, H },\r
- { NULL, "l", S_REG, 0, L },\r
- { NULL, "hl", S_REG, 0, H },\r
- { NULL, "m", S_REG, 0, M },\r
- { NULL, "psw", S_REG, 0, PSW },\r
- { NULL, "a", S_REG, 0, A },\r
- { NULL, "af", S_REG, 0, PSW },\r
- { NULL, "sp", S_REG, 0, SP },\r
-\r
- { NULL, "xthl", S_INH, 0, 0343 },\r
- { NULL, "sphl", S_INH, 0, 0371 },\r
- { NULL, "pchl", S_INH, 0, 0351 },\r
- { NULL, "xchg", S_INH, 0, 0353 },\r
- { NULL, "ret", S_INH, 0, 0311 },\r
- { NULL, "rc", S_INH, 0, 0330 },\r
- { NULL, "rnc", S_INH, 0, 0320 },\r
- { NULL, "rz", S_INH, 0, 0310 },\r
- { NULL, "rnz", S_INH, 0, 0300 },\r
- { NULL, "rp", S_INH, 0, 0360 },\r
- { NULL, "rm", S_INH, 0, 0370 },\r
- { NULL, "rpe", S_INH, 0, 0350 },\r
- { NULL, "rpo", S_INH, 0, 0340 },\r
- { NULL, "rim", S_INH, 0, 0040 },\r
- { NULL, "rlc", S_INH, 0, 0007 },\r
- { NULL, "rrc", S_INH, 0, 0017 },\r
- { NULL, "ral", S_INH, 0, 0027 },\r
- { NULL, "rar", S_INH, 0, 0037 },\r
- { NULL, "cma", S_INH, 0, 0057 },\r
- { NULL, "stc", S_INH, 0, 0067 },\r
- { NULL, "cmc", S_INH, 0, 0077 },\r
- { NULL, "daa", S_INH, 0, 0047 },\r
- { NULL, "ei", S_INH, 0, 0373 },\r
- { NULL, "di", S_INH, 0, 0363 },\r
- { NULL, "nop", S_INH, 0, 0000 },\r
- { NULL, "hlt", S_INH, 0, 0166 },\r
- { NULL, "sim", S_INH, 0, 0060 },\r
-\r
- { NULL, "rst", S_RST, 0, 0307 },\r
-\r
- { NULL, "in", S_ADI, 0, 0333 },\r
- { NULL, "out", S_ADI, 0, 0323 },\r
- { NULL, "adi", S_ADI, 0, 0306 },\r
- { NULL, "aci", S_ADI, 0, 0316 },\r
- { NULL, "sui", S_ADI, 0, 0326 },\r
- { NULL, "sbi", S_ADI, 0, 0336 },\r
- { NULL, "ani", S_ADI, 0, 0346 },\r
- { NULL, "xri", S_ADI, 0, 0356 },\r
- { NULL, "ori", S_ADI, 0, 0366 },\r
- { NULL, "cpi", S_ADI, 0, 0376 },\r
-\r
- { NULL, "add", S_ADD, 0, 0200 },\r
- { NULL, "adc", S_ADD, 0, 0210 },\r
- { NULL, "sub", S_ADD, 0, 0220 },\r
- { NULL, "sbb", S_ADD, 0, 0230 },\r
- { NULL, "ana", S_ADD, 0, 0240 },\r
- { NULL, "xra", S_ADD, 0, 0250 },\r
- { NULL, "ora", S_ADD, 0, 0260 },\r
- { NULL, "cmp", S_ADD, 0, 0270 },\r
-\r
- { NULL, "sta", S_JMP, 0, 0062 },\r
- { NULL, "lda", S_JMP, 0, 0072 },\r
- { NULL, "shld", S_JMP, 0, 0042 },\r
- { NULL, "lhld", S_JMP, 0, 0052 },\r
- { NULL, "jmp", S_JMP, 0, 0303 },\r
- { NULL, "jc", S_JMP, 0, 0332 },\r
- { NULL, "jnc", S_JMP, 0, 0322 },\r
- { NULL, "jz", S_JMP, 0, 0312 },\r
- { NULL, "jnz", S_JMP, 0, 0302 },\r
- { NULL, "jp", S_JMP, 0, 0362 },\r
- { NULL, "jm", S_JMP, 0, 0372 },\r
- { NULL, "jpe", S_JMP, 0, 0352 },\r
- { NULL, "jpo", S_JMP, 0, 0342 },\r
- { NULL, "call", S_JMP, 0, 0315 },\r
- { NULL, "cc", S_JMP, 0, 0334 },\r
- { NULL, "cnc", S_JMP, 0, 0324 },\r
- { NULL, "cz", S_JMP, 0, 0314 },\r
- { NULL, "cnz", S_JMP, 0, 0304 },\r
- { NULL, "cp", S_JMP, 0, 0364 },\r
- { NULL, "cm", S_JMP, 0, 0374 },\r
- { NULL, "cpe", S_JMP, 0, 0354 },\r
- { NULL, "cpo", S_JMP, 0, 0344 },\r
-\r
- { NULL, "inr", S_INR, 0, 0004 },\r
- { NULL, "dcr", S_INR, 0, 0005 },\r
-\r
- { NULL, "lxi", S_LXI, 0, 0001 },\r
-\r
- { NULL, "ldax", S_LDAX, 0, 0012 },\r
- { NULL, "stax", S_LDAX, 0, 0002 },\r
-\r
- { NULL, "inx", S_INX, 0, 0003 },\r
- { NULL, "dcx", S_INX, 0, 0013 },\r
- { NULL, "dad", S_INX, 0, 0011 },\r
-\r
- { NULL, "push", S_PUSH, 0, 0305 },\r
- { NULL, "pop", S_PUSH, 0, 0301 },\r
-\r
- { NULL, "mov", S_MOV, 0, 0100 },\r
-\r
- { NULL, "mvi", S_MVI, 0, 0006 },\r
-\r
- /* Undocumented 8085 Opcodes */\r
-\r
- { NULL, "dsub", S_INH, 0, 0010 },\r
- { NULL, "arhl", S_INH, 0, 0020 },\r
- { NULL, "rdel", S_INH, 0, 0030 },\r
- { NULL, "rstv", S_INH, 0, 0313 },\r
- { NULL, "shlx", S_INH, 0, 0331 },\r
- { NULL, "lhlx", S_INH, 0, 0355 },\r
-\r
- { NULL, "ldhi", S_ADI, 0, 0050 },\r
- { NULL, "ldsi", S_ADI, 0, 0070 },\r
-\r
- { NULL, "jnx5", S_JMP, 0, 0335 },\r
- { NULL, "jx5", S_JMP, S_EOL, 0375 }\r
+ //{ NULL, "b", S_REG, 0, B },\r
+ //{ NULL, "c", S_REG, 0, C },\r
+ //{ NULL, "bc", S_REG, 0, B },\r
+ //{ NULL, "d", S_REG, 0, D },\r
+ //{ NULL, "e", S_REG, 0, E },\r
+ //{ NULL, "de", S_REG, 0, D },\r
+ //{ NULL, "h", S_REG, 0, H },\r
+ //{ NULL, "l", S_REG, 0, L },\r
+ //{ NULL, "hl", S_REG, 0, H },\r
+ //{ NULL, "m", S_REG, 0, M },\r
+ //{ NULL, "psw", S_REG, 0, PSW },\r
+ //{ NULL, "a", S_REG, 0, A },\r
+ //{ NULL, "af", S_REG, 0, PSW },\r
+ //{ NULL, "sp", S_REG, 0, SP },\r
+\r
+ { NULL, "ld", S_LD, 0, 0 },\r
+ { NULL, "x", S_X, 0, 0 },\r
+ { NULL, "andsz", S_ANDSZ, 0, 0 },\r
+ { NULL, "ifeq", S_IFEQ, 0, 0 },\r
+ { NULL, "ifne", S_IFNE, 0, 0 },\r
+ { NULL, "ifbne", S_IFBNE, 0, 0 },\r
+ { NULL, "jmp", S_JMP_JSR, 0, 0 },\r
+ { NULL, "jsr", S_JMP_JSR, 0, 0x10 },\r
+ { NULL, "jmpl", S_JMPL_JSRL, 0, 0xac },\r
+ { NULL, "jsrl", S_JMPL_JSRL, 0, 0xad },\r
+ { NULL, "jp", S_JP, 0, 0 },\r
+ { NULL, "drsz", S_DRSZ, 0, 0 },\r
+ { NULL, "rc", S_FIXED, 0, 0xa0 },\r
+ { NULL, "vis", S_FIXED, 0, 0xb4 },\r
+ { NULL, "retsk", S_FIXED, 0, 0x8d },\r
+ { NULL, "nop", S_FIXED, 0, 0xb8 },\r
+ { NULL, "rpnd", S_FIXED, 0, 0xb5 },\r
+ { NULL, "dec", S_ACC, 0, 0x8b },\r
+ { NULL, "rlc", S_ACC, 0, 0xa8 },\r
+ { NULL, "push", S_ACC, 0, 0x67 },\r
+ { NULL, "subc", S_ACCMEM, 0, 0x81 },\r
+ { NULL, "xor", S_ACCMEM, 0, 0x86 },\r
+ { NULL, "ifgt", S_ACCMEM, 0, 0x83 },\r
+ { NULL, "rbit", S_BIT, 0, 0x68 },\r
+ { NULL, "cop87l84", S_CPU, S_EOL, 0/*switchto_cop8*/ },\r
};\r
--- /dev/null
+#!/bin/sh
+sed -e 's/[ \t]\+/ /g' codecop8.c |\
+sed -ne 's/^.*Add\([0-9A-Za-z_]*\)(.*\("[^"]*"\) *\(.*\));.*$/ {NULL, \2, S_\1, 0\3 },/p' |\
+sed -e 's/, S_\([^,]*\), 0, \([^,]*\), Decode\(.*\) }/, S_\3, F_\1, \2 }/' |\
+sed -e 's/, 0, *CPU/, F_CPU/' |\
+sed -e 's/,0x/, 0x/' |\
+sed -e 's/, F_InstTable,/, 0,/' >a
+
+sed -ne 's/^.*, \(S_[^,]*\),.*$/\1/p' <a |LC_ALL=C sort |uniq >b
+tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' <b >b0
+tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' <b >b1
+paste b0 b1 |sed -e 's/\(.*\)\t\(.*\)/s\/, \1, \/, \2, \//' >b2
+
+sed -ne 's/^.*, \(F_[^,]*\),.*$/\1/p' <a |LC_ALL=C sort |uniq >c
+tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' <c >c0
+tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' <c >c1
+paste c0 c1 |sed -e 's/\(.*\)\t\(.*\)/s\/, \1, \/, \2, \//' >c2
+
+tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' <a >a0
+sed -f b2 <a0 |sed -f c2 |sed -e 's/ /\t/g; s/^\t\t\t\t{null,/ {\tNULL,/; s/"[0-9a-z_]\{1,4\}",/&\t/; s/\tS_[0-9A-Z_]\{1,4\},/&\t/; s/\tF_[0-9A-Z_]\{1,4\},/&\t/' >a1
--- /dev/null
+ ifndef regcop8inc ; avoid multiple inclusion
+regcop8inc equ 1
+
+ save
+ listing off ; no listing over this file
+;****************************************************************************
+;* *
+;* AS 1.42 - File REGCOP8.INC *
+;* *
+;* Contains Register Definitions for COP8 Controllers *
+;* *
+;****************************************************************************
+
+ if MOMPASS=1
+ switch MOMCPUNAME
+ case "COP87L84"
+ message "including COP87L84-registers"
+ elsecase
+ fatal "invalid processor type: only COP87L84 allowed"
+ endcase
+ endif
+
+;----------------------------------------------------------------------------
+; Processor Core
+
+__REG set 0
+ rept 10
+R{"\{__REG}"} equ __REG+0xf0
+__REG set __REG+1,data
+ endm
+ rept 6
+R1{"\{__REG-10}"} equ __REG+0xf0
+__REG set __REG+1,data
+ endm
+
+psw sfr 0xef ; Flags
+gie equ 0 ; Global Interrupt Enable
+exen equ 1 ; External Interrupt Enable
+busy equ 2 ; Microwire Busy
+expnd equ 3 ; External Interrupt Pending
+t1ena equ 4 ; Timer 1 Interrupt Enable
+t1pnda equ 5 ; Timer 1 Interrupt Pending
+c equ 6 ; Carry
+hc equ 7 ; Half Carry
+x sfr 0xfc ; X-Register
+sp sfr 0xfd ; Stack Pointer
+b sfr 0xfe ; B Register
+
+;----------------------------------------------------------------------------
+; Peripheral Control Registers
+
+cntrl sfr 0xee ; Globale Control
+sl0 equ 0 ; Microwire Clock Divider
+sl1 equ 1
+iedg equ 2 ; External Interrupt Edge Select
+msel equ 3 ; Microwire use G4/G5
+t1c0 equ 4 ; Timer 1 Interrupt/Start-Stop
+t1c1 equ 5 ; Timer 1 Mode Select
+t1c2 equ 6
+t1c3 equ 7
+
+icntrl sfr 0xe8 ; Continuation...
+t1enb equ 0 ; Timer 1 Capture Interrupt Enable
+t1pndb equ 1 ; Timer 1 Capture Interrupt Pending
+uwen equ 2 ; MicroWire-Interrupt Enable
+uwpnd equ 3 ; MicroWire-Interrupt Pending
+t0en equ 4 ; Timer 0 Interrupt Enable
+t0pndb equ 5 ; Timer 0 Interrupt Pending
+lpen equ 6 ; Port L-Interrupt Enable
+
+;----------------------------------------------------------------------------
+; Timer
+
+t1rblo sfr 0xe6 ; Timer 1 Reload Value B
+t1rbhi sfr 0xe7
+
+tmr1lo sfr 0xea ; Timer 1 Count Value
+tmr1hi sfr 0xeb
+
+t1ralo sfr 0xec ; Timer 1 Reload Value B
+t1rahi sfr 0xed
+
+;----------------------------------------------------------------------------
+; PWM
+
+pscal sfr 0xa0 ; PWM Prescaler
+
+rlon sfr 0xa1 ; PWM Duty Cycle
+
+pwmcon sfr 0xa2 ; PWM Control
+pwen0 equ 0 ; PWM0 Output to I/O Port
+pwen1 equ 1 ; PWM1 Output to I/O Port
+pwon equ 2 ; PWM Start/Stop
+pwmd equ 3 ; PWM Mode
+pwie equ 4 ; PWM Interrupt Enable
+pwpnd equ 5 ; PWM Interrupt Pending
+esel equ 6 ; PWM Edge Select
+
+;----------------------------------------------------------------------------
+; MicroWire Interface
+
+wkedg sfr 0xc8
+wken sfr 0xc9
+wkpnd sfr 0xca
+
+sior sfr 0xe9 ; Shift register
+
+;----------------------------------------------------------------------------
+; CAN Interface
+
+txd1 sfr 0xb0 ; Transmit Data (Byte 1,3,5,7,...)
+txd2 sfr 0xb1 ; Transmit Data (Byte 2,4,6,8,...)
+
+tdlc sfr 0xb2 ; Transmit Length/Identifier(L) Register
+tdlc0 equ 0 ; Transmit Length
+tdlc1 equ 1
+tdlc2 equ 2
+tdlc3 equ 3
+tid0 equ 4 ; Transmit Identification (Bits 0..3)
+tid1 equ 5
+tid2 equ 6
+tid3 equ 7
+
+tid sfr 0xb3 ; Transmit Identification Register
+tid4 equ 0 ; Transmit Identification (Bits 4..10)
+tid5 equ 1
+tid6 equ 2
+tid7 equ 3
+tid8 equ 4
+tid9 equ 5
+tid10 equ 6
+trtr equ 7 ; Transmit Frame Remote
+
+rxd1 sfr 0xb4 ; Receive Data (Byte 1,3,5,7,...)
+rxd2 sfr 0xb5 ; Receive Data (Byte 2,4,6,8,...)
+
+ridl sfr 0xb6 ; Receive Length/Identifier(L) Register
+rdlc0 equ 0 ; Receive Length
+rdlc1 equ 1
+rdlc2 equ 2
+rdlc3 equ 3
+rid0 equ 4 ; Receive Identification (Bits 0..3)
+rid1 equ 5
+rid2 equ 6
+rid3 equ 7
+
+rid sfr 0xb7 ; Receive Identification Register
+rid4 equ 0 ; Receive Identification (Bits 4..10)
+rid5 equ 1
+rid6 equ 2
+rid7 equ 3
+rid8 equ 4
+rid9 equ 5
+rid10 equ 6
+
+cscal sfr 0xb8 ; CAN Clock Prescaler
+
+ctim sfr 0xb9 ; CAN Bus Timing Register
+ps0 equ 2 ; Phase Segment
+ps1 equ 3
+ps2 equ 4
+pps0 equ 5 ; Propagation Segment
+pps1 equ 6
+pps2 equ 7
+
+cbus sfr 0xba ; CAN Bus Timing Register
+fmod equ 1 ; Fault Confinement Mode
+rxred0 equ 2 ; Apply Reference Voltage to Rx0
+rxref1 equ 3 ; Apply Reference Voltage to Tx0
+txen0 equ 4 ; Enable TxD Output Drivers
+txen1 equ 5
+riaf equ 6 ; Receive Filter Enable
+
+tcntl sfr 0xbb ; CAN Bus Control/Status Register
+txss equ 0 ; Transmitter Start/Stop
+rie equ 1 ; Receive Interrupt Enable
+tie equ 2 ; Transmit Interrupt Enable
+ceie equ 3 ; CAN Interrupt Enable
+rerr equ 4 ; Receive Error
+terr equ 5 ; Transmit Error
+ns0 equ 6 ; Node State
+ns1 equ 7
+
+rtstat sfr 0xbc ; CAN Bus Transmitter/Receiver State
+rbf equ 0 ; Receive Buffer Full
+rcv equ 1 ; Reception Running
+rfv equ 2 ; Received Frame Valid
+rorn equ 3 ; Receiver Overflow
+rold equ 4 ; Receiver Frame Overflow
+rrtr equ 5 ; Remote-Bit Set in Received Frame
+txpnd equ 6 ; Transmission Pending
+tbe equ 7 ; Transmit Buffer Empty
+
+tec sfr 0xbd ; Transmit Error Counter
+rec sfr 0xbe ; Receive Error Counter
+
+;----------------------------------------------------------------------------
+; Comparators
+
+cmpsl sfr 0xd3 ; Comparator Control Register
+cmp1en equ 1 ; Comparator 1 Enable
+cmp1rd equ 2 ; Comparator 1 Output Value
+cmp1oe equ 3 ; Comparator 1 Output Enable
+cmp2en equ 4 ; Comparator 2 Enable
+cmp2rd equ 5 ; Comparator 2 Output Value
+cmp2oe equ 6 ; Comparator 2 Output Enable
+cmp2sel equ 7 ; Comparator 2 Output on L3/L5
+
+;----------------------------------------------------------------------------
+; Ports
+
+portld sfr 0xd0 ; Port L Output Register
+portlc sfr 0xd1 ; Port L Configuration Register
+portlp sfr 0xd2 ; Port L Input Register
+
+portgd sfr 0xd4 ; Port G Output Register
+portgc sfr 0xd5 ; Port G Configuration Register
+portgp sfr 0xd6 ; Port G Input Register
+
+portd sfr 0xdc ; Port D Output Register
+
+;----------------------------------------------------------------------------
+; Vector Addresses
+
+;----------------------------------------------------------------------------
+; Memory Addresses
+
+iram sfr 0x00 ; Internal RAM Area
+iramend sfr 0x2f
+
+;----------------------------------------------------------------------------
+
+ restore ; re-enable listing
+
+ endif ; regcop8inc
+
+
--- /dev/null
+ cpu cop87l84
+
+ macexp off
+
+ include regcop8.inc
+
+ nop
+ ret
+ reti
+ retsk
+ sc
+ rc
+ ifc
+ ifnc
+ vis
+ jid
+ intr
+ laid
+ rpnd
+
+ clr a
+ inc a
+ dec a
+ dcor a
+ rrc a
+ rlc a
+ swap a
+ pop a
+ push a
+
+ adc a,[b]
+ adc a,0x12
+ adc a,#0x12
+
+ subc a,[b]
+ subc a,0x12
+ subc a,#0x12
+
+ add a,[b]
+ add a,0x12
+ add a,#0x12
+
+ ifgt a,[b]
+ ifgt a,0x12
+ ifgt a,#0x12
+
+ and a,[b]
+ and a,0x12
+ and a,#0x12
+
+ xor a,[b]
+ xor a,0x12
+ xor a,#0x12
+
+ or a,[b]
+ or a,0x12
+ or a,#0x12
+
+ ld a,[b]
+ ld a,0x12
+ ld a,#0x12
+ ld a,[x]
+ ld r4,#0x12
+ ld b,#12
+ ld b,#0x12
+ ld a,[b+]
+ ld a,[x+]
+ ld a,[b-]
+ ld a,[x-]
+ ld [b],#0x12
+ ld [b+],#0x12
+ ld [b-],#0x12
+ ld 0x12,#0x12
+
+ x a,[b]
+ x [x],a
+ x a,[b+]
+ x [x+],a
+ x a,[b-]
+ x [x-],a
+ x a,0x12
+
+ andsz a,#0x12
+
+ ifeq a,[b]
+ ifeq a,0x12
+ ifeq a,#0x12
+ ifeq 0x12,#0x12
+
+ ifne a,[b]
+ ifne a,0x12
+ ifne a,#0x12
+
+ ifbit 3,[b]
+ ifbit 5,0x12
+ sbit 3,[b]
+ sbit 5,0x12
+ rbit 3,[b]
+ rbit 5,0x12
+
+ ifbne #7
+ ifbne #0xc
+
+ jmp 0x123
+ jsr 0x987
+
+ jmpl 0x1234
+ jsrl 0x3456
+
+ jp .+6
+ jp .-20
+ expect 60
+ jp .+1
+ endexpect
+
+ drsz r12
+ drsz r8
+
+reg sfr 10
+
+ addr 1,2,3,4,5
+ addrw 1,2,3,4,5
+ byte 1,2,3,4,5
+ word 1,2,3,4,5
+ dsb 20
+ dsw 20
+ fb 10,20
+ fw 10,20
+
+
static char *GetString(void)
{
-#if 1
- abort();
-#else
return (char*)malloc(STRINGSIZE * sizeof(char));
-#endif
}
int SetMaxCodeLen(LongWord NewMaxCodeLen)
{
-#if 1
- abort();
-#else
if (NewMaxCodeLen > MaxCodeLen_Max)
return ENOMEM;
if (NewMaxCodeLen > MaxCodeLen)
MaxCodeLen = NewMaxCodeLen;
}
return 0;
-#endif
}
/*!------------------------------------------------------------------------
void asmdef_init(void)
{
-#if 1
- abort();
-#else
SwitchFrom = NullProc;
InternSymbol = Default_InternSymbol;
DissectBit = Default_DissectBit;
SegLimits = (LargeWord*)calloc(SegCount, sizeof(*SegLimits));
Phases = (LargeWord*)calloc(SegCountPlusStruct, sizeof(*Phases));
PCs = (LargeWord*)calloc(SegCountPlusStruct, sizeof(*PCs));
-#endif
}
static Boolean AddSingle(PInstTreeNode *Node, char *NName, InstProc NProc, Word NIndex)
{
-#if 1
- abort();
-#else
PInstTreeNode p1, p2;
Boolean Result = False;
}
}
return Result;
-#endif
}
void AddInstTree(PInstTreeNode *Root, char *NName, InstProc NProc, Word NIndex)
{
-#if 1
- abort();
-#else
AddSingle(Root, NName, NProc, NIndex);
-#endif
}
static void ClearSingle(PInstTreeNode *Node)
{
-#if 1
- abort();
-#else
ChkStack();
if (*Node)
free(*Node);
*Node = NULL;
}
-#endif
}
void ClearInstTree(PInstTreeNode *Root)
{
-#if 1
- abort();
-#else
ClearSingle(Root);
-#endif
}
Boolean SearchInstTree(PInstTreeNode Root, char *OpPart)
{
-#if 1
- abort();
-#else
int z;
z = 0;
Root->Proc(Root->Index);
return True;
}
-#endif
}
static void PNode(PInstTreeNode Node, Word Lev)
{
-#if 1
- abort();
-#else
ChkStack();
if (Node)
{
printf("%*s %s %p %p %d\n", 5 * Lev, "", Node->Name, (void*)Node->Left, (void*)Node->Right, Node->Balance);
PNode(Node->Right, Lev + 1);
}
-#endif
}
void PrintInstTree(PInstTreeNode Root)
{
-#if 1
- abort();
-#else
PNode(Root, 0);
-#endif
}
/*----------------------------------------------------------------------------*/
static int GetKey(const char *Name, LongWord TableSize)
{
-#if 1
- abort();
-#else
register unsigned char *p;
LongWord tmp = 0;
for (p = (unsigned char *)Name; *p != '\0'; p++)
tmp = (tmp << 2) + ((LongWord)*p);
return tmp % TableSize;
-#endif
}
PInstTable CreateInstTable(int TableSize)
{
-#if 1
- abort();
-#else
int z;
PInstTableEntry tmp;
PInstTable tab;
tab->Entries = tmp;
tab->Dynamic = FALSE;
return tab;
-#endif
}
void SetDynamicInstTable(PInstTable Table)
{
-#if 1
- abort();
-#else
Table->Dynamic = TRUE;
-#endif
}
void DestroyInstTable(PInstTable tab)
{
-#if 1
- abort();
-#else
int z;
if (tab->Dynamic)
free(tab->Entries);
free(tab);
-#endif
}
void AddInstTable(PInstTable tab, const char *Name, Word Index, InstProc Proc)
{
-#if 1
- abort();
-#else
LongWord h0 = GetKey(Name, tab->Size), z = 0;
/* mindestens ein freies Element lassen, damit der Sucher garantiert terminiert */
if ((LongInt)(++h0) == tab->Size)
h0 = 0;
}
-#endif
}
void RemoveInstTable(PInstTable tab, const char *Name)
{
-#if 1
- abort();
-#else
LongWord h0 = GetKey(Name, tab->Size);
while (1)
if ((LongInt)(++h0) == tab->Size)
h0 = 0;
}
-#endif
}
Boolean LookupInstTable(PInstTable tab, const char *Name)
{
-#if 1
- abort();
-#else
LongWord h0 = GetKey(Name, tab->Size);
while (1)
if ((LongInt)(++h0) == tab->Size)
h0 = 0;
}
-#endif
}
void PrintInstTable(FILE *stream, PInstTable tab)
{
-#if 1
- abort();
-#else
int z;
for (z = 0; z < tab->Size; z++)
if (tab->Entries[z].Name)
fprintf(stream, "[%3d]: %-10s Index %4d Coll %2d\n", z,
tab->Entries[z].Name, tab->Entries[z].Index, tab->Entries[z].Coll);
-#endif
}
/*----------------------------------------------------------------------------*/
void asmitree_init(void)
{
-#if 1
- abort();
-#else
-#endif
}
/* */
/*****************************************************************************/
+#include <assert.h> // Nick
+#include <stdbool.h> // Nick
#include "stdinc.h"
#include <string.h>
#include <ctype.h>
CPUVar AddCPUWithArgs(const char *NewName, tCPUSwitchProc Switcher, const tCPUArg *pArgs)
{
#if 1
- abort();
+ static bool flag = false;
+ assert(!flag);
+ flag = true;
+ Switcher();
#else
tNoUserData *pData = (tNoUserData*)malloc(sizeof(*pData));
static void check_dynamic(const as_dynstr_t *p_str)
{
-#if 1
- abort();
-#else
if (!p_str->dynamic)
{
fprintf(stderr, "attemt to resize non-dynamic string\n");
abort();
}
-#endif
}
/*!------------------------------------------------------------------------
void as_dynstr_ini(as_dynstr_t *p_str, size_t ini_capacity)
{
-#if 1
- abort();
-#else
p_str->p_str = (char*)malloc(ini_capacity);
p_str->capacity = p_str->p_str ? ini_capacity : 0;
p_str->dynamic = !!p_str->p_str;
memset(p_str->p_str, 0, p_str->capacity);
-#endif
}
/*!------------------------------------------------------------------------
void as_dynstr_ini_clone(as_dynstr_t *p_str, const as_dynstr_t *p_src)
{
-#if 1
- abort();
-#else
p_str->p_str = (char*)malloc(p_src->capacity);
if (p_str->p_str)
{
p_str->capacity = 0;
p_str->dynamic = 0;
}
-#endif
}
/*!------------------------------------------------------------------------
void as_dynstr_ini_c_str(as_dynstr_t *p_str, const char *p_src)
{
-#if 1
- abort();
-#else
size_t capacity = as_dynstr_roundup_len(strlen(p_src));
p_str->p_str = (char*)malloc(capacity);
p_str->capacity = 0;
p_str->dynamic = 0;
}
-#endif
}
/*!------------------------------------------------------------------------
int as_dynstr_realloc(as_dynstr_t *p_str, size_t new_capacity)
{
-#if 1
- abort();
-#else
char *p_new;
size_t old_capacity;
}
else
return ENOMEM;
-#endif
}
/*!------------------------------------------------------------------------
void as_dynstr_free(as_dynstr_t *p_str)
{
-#if 1
- abort();
-#else
if (p_str->dynamic && p_str->p_str)
free(p_str->p_str);
p_str->p_str = NULL;
p_str->capacity = 0;
p_str->dynamic = 0;
-#endif
}
/*!------------------------------------------------------------------------
size_t as_dynstr_copy(as_dynstr_t *p_dest, const as_dynstr_t *p_src)
{
-#if 1
- abort();
-#else
return as_dynstr_copy_c_str(p_dest, p_src->p_str);
-#endif
}
/*!------------------------------------------------------------------------
size_t as_dynstr_copy_c_str(as_dynstr_t *p_dest, const char *p_src)
{
-#if 1
- abort();
-#else
size_t len = strlen(p_src);
if ((len >= p_dest->capacity) && p_dest->dynamic)
memcpy(p_dest->p_str, p_src, len);
p_dest->p_str[len] = '\0';
return len;
-#endif
}
/*!------------------------------------------------------------------------
size_t as_dynstr_append_c_str(as_dynstr_t *p_dest, const char *p_src)
{
-#if 1
- abort();
-#else
size_t src_len = strlen(p_src),
dest_len = strlen(p_dest->p_str);
memcpy(p_dest->p_str + dest_len, p_src, src_len);
p_dest->p_str[dest_len + src_len] = '\0';
return src_len;
-#endif
}
/*!------------------------------------------------------------------------
void as_dynstr_dump_hex(FILE *p_file, const as_dynstr_t *p_str)
{
-#if 1
- abort();
-#else
const char *p_run;
fprintf(p_file, "[%u]", (unsigned)p_str->capacity);
for (p_run = p_str->p_str; *p_run; p_run++) fprintf(p_file, " %02x", *p_run & 0xff);
fprintf(p_file, "\n");
-#endif
}
void SetIntConstMode(tIntConstMode Mode)
{
#if 1
- abort();
+ fprintf(stderr, "SetIntConstMode()\n");
#else
IntConstMode = Mode;
switch (Mode)
void StrCompAlloc(tStrComp *pComp, size_t capacity)
{
-#if 1
- abort();
-#else
as_dynstr_ini(&pComp->str, capacity);
StrCompReset(pComp);
-#endif
}
/*!------------------------------------------------------------------------
void StrCompReset(tStrComp *pComp)
{
-#if 1
- abort();
-#else
LineCompReset(&pComp->Pos);
*pComp->str.p_str = '\0';
-#endif
}
/*!------------------------------------------------------------------------
void LineCompReset(tLineComp *pComp)
{
-#if 1
- abort();
-#else
pComp->StartCol = -1;
pComp->Len = 0;
-#endif
}
/*!------------------------------------------------------------------------
\r
\r
CC= gcc\r
-CCOPT= -O3\r
+#CCOPT= -O3\r
+CCOPT= -Og\r
CCFLAGS= -Wall -funsigned-char $(CCOPT) -g\r
# Nick -g\r
\r
public / asxv5pxx.git / commitdiff