Add aslcop8 which is just a copy of as8085 so far

diff --git a/.gitignore b/.gitignore
index 52697f2..5ed29b2 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -7,9 +7,11 @@
 /aspdp11/ref/aslist
 /aspdp11/ref/asxlat
 /aspdp11/test/*.lst
+/asxmak/linux/build/aslcop8
 /asxmak/linux/build/aslink
 /asxmak/linux/build/aspdp11
 /asxmak/linux/build/asz80
+/asxmak/linux/exe/aslcop8
 /asxmak/linux/exe/aslink
 /asxmak/linux/exe/aspdp11
 /asxmak/linux/exe/asz80

diff --git a/aslcop8/lcop8.h b/aslcop8/lcop8.h
new file mode 100644 (file)
index 0000000..47bd833
--- /dev/null
+++ b/aslcop8/lcop8.h
@@ -0,0 +1,104 @@
+/* i8085.h */\r
+\r
+/*\r
+ *  Copyright (C) 1989-2014  Alan R. Baldwin\r
+ *\r
+ *  This program is free software: you can redistribute it and/or modify\r
+ *  it under the terms of the GNU General Public License as published by\r
+ *  the Free Software Foundation, either version 3 of the License, or\r
+ *  (at your option) any later version.\r
+ *\r
+ *  This program is distributed in the hope that it will be useful,\r
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+ *  GNU General Public License for more details.\r
+ *\r
+ *  You should have received a copy of the GNU General Public License\r
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+ *\r
+ *\r
+ * Alan R. Baldwin\r
+ * 721 Berkeley St.\r
+ * Kent, Ohio  44240\r
+ */\r
+\r
+/*)BUILD\r
+       $(PROGRAM) =    AS8085\r
+       $(INCLUDE) = {\r
+               ASXXXX.H\r
+               I8085.H\r
+       }\r
+       $(FILES) = {\r
+               I85MCH.C\r
+               I85PST.C\r
+               ASMAIN.C\r
+               ASDBG.C\r
+               ASLEX.C\r
+               ASSYM.C\r
+               ASSUBR.C\r
+               ASEXPR.C\r
+               ASDATA.C\r
+               ASLIST.C\r
+               ASOUT.C\r
+       }\r
+       $(STACK) = 3000\r
+*/\r
+\r
+/*\r
+ * Symbol types.\r
+ */\r
+#define        S_INH   50              /* One byte */\r
+#define        S_RST   51              /* Restart */\r
+#define        S_ADI   52              /* One byte immediate */\r
+#define        S_ADD   53              /* One reg. */\r
+#define        S_JMP   54              /* Jumps, calls, etc. */\r
+#define        S_INR   55              /* Reg. dest. */\r
+#define        S_LXI   56              /* Word immediate */\r
+#define        S_LDAX  57              /* B or D */\r
+#define        S_INX   58              /* Word reg. dest. */\r
+#define        S_PUSH  59              /* Push, pop */\r
+#define        S_MOV   60              /* Mov */\r
+#define        S_MVI   61              /* Mvi */\r
+#define        S_REG   62              /* Registers */\r
+\r
+/*\r
+ * Other\r
+ */\r
+#define        S_FLAG  70\r
+\r
+/*\r
+ * Registers.\r
+ */\r
+#define        B       0\r
+#define        C       1\r
+#define        D       2\r
+#define        E       3\r
+#define        H       4\r
+#define        L       5\r
+#define        M       6\r
+#define        A       7\r
+#define        SP      8\r
+#define        PSW     9\r
+\r
+       /* machine dependent functions */\r
+\r
+#ifdef OTHERSYSTEM\r
+       \r
+       /* 85mch.c */\r
+extern VOID            machine(struct mne *mp);\r
+extern VOID            minit(void);\r
+extern VOID            out3(int a, int b);\r
+extern int             reg(void);\r
+extern int             regpair(int r, int s);\r
+\r
+#else\r
+\r
+       /* 85mch.c */\r
+extern VOID            machine();\r
+extern VOID            minit();\r
+extern VOID            out3();\r
+extern int             reg();\r
+extern int             regpair();\r
+\r
+#endif\r
+\r

diff --git a/aslcop8/lcop8mch.c b/aslcop8/lcop8mch.c
new file mode 100644 (file)
index 0000000..de3ab2a
--- /dev/null
+++ b/aslcop8/lcop8mch.c
@@ -0,0 +1,231 @@
+/* i85mch.c */\r
+\r
+/*\r
+ *  Copyright (C) 1989-2014  Alan R. Baldwin\r
+ *\r
+ *  This program is free software: you can redistribute it and/or modify\r
+ *  it under the terms of the GNU General Public License as published by\r
+ *  the Free Software Foundation, either version 3 of the License, or\r
+ *  (at your option) any later version.\r
+ *\r
+ *  This program is distributed in the hope that it will be useful,\r
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+ *  GNU General Public License for more details.\r
+ *\r
+ *  You should have received a copy of the GNU General Public License\r
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+ *\r
+ *\r
+ * Alan R. Baldwin\r
+ * 721 Berkeley St.\r
+ * Kent, Ohio  44240\r
+ */\r
+\r
+#include "asxxxx.h"\r
+#include "lcop8.h"\r
+\r
+char   *cpu    = "Intel 8085";\r
+char   *dsft   = "asm";\r
+\r
+/*\r
+ * Opcode Cycle Definitions\r
+ */\r
+#define        OPCY_SDP        ((char) (0xFF))\r
+#define        OPCY_ERR        ((char) (0xFE))\r
+\r
+/*     OPCY_NONE       ((char) (0x80)) */\r
+/*     OPCY_MASK       ((char) (0x7F)) */\r
+\r
+#define        UN      ((char) (OPCY_NONE | 0x00))\r
+\r
+/*\r
+ * 8085 Cycle Count\r
+ *\r
+ *     opcycles = i85pg1[opcode]\r
+ */\r
+static char i85pg1[256] = {\r
+/*--*--* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */\r
+/*--*--* -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - */\r
+/*00*/   4,10, 7, 6, 4, 4, 7, 4,10,10, 7, 6, 4, 4, 7, 4,\r
+/*10*/   7,10, 7, 6, 4, 4, 7, 4,10,10, 7, 6, 4, 4, 7, 4,\r
+/*20*/   4,10,16, 6, 4, 4, 7, 4,10,10,16, 6, 4, 4, 7, 4,\r
+/*30*/   4,10,13, 6,10,10,10, 4,10,10,13, 6, 4, 4, 7, 4,\r
+/*40*/   4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,\r
+/*50*/   4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,\r
+/*60*/   4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,\r
+/*70*/   7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,\r
+/*80*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\r
+/*90*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\r
+/*A0*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\r
+/*B0*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\r
+/*C0*/  12,10,10,10,18,12, 7,12,12,10,10,12,18,18, 7,12,\r
+/*D0*/  12,10,10,10,18,12, 7,12,12,10,10,10,18,10, 7,12,\r
+/*E0*/  12,10,10,16,18,12, 7,12,12, 6,10, 4,18,10, 7,12,\r
+/*F0*/  12,10,10, 4,18,12, 7,12,12, 6,10, 4,18,10, 7,12\r
+};\r
+\r
+/*\r
+ * Process machine ops.\r
+ */\r
+VOID\r
+machine(mp)\r
+struct mne *mp;\r
+{\r
+       unsigned op, rd, rs;\r
+       struct expr e;\r
+\r
+       clrexpr(&e);\r
+       op = (int) mp->m_valu;\r
+       switch (mp->m_type) {\r
+\r
+       case S_INH:\r
+               outab(op);\r
+               break;\r
+\r
+       case S_RST:\r
+               rd = (int) absexpr();\r
+               if (rd > 7)\r
+                       aerr();\r
+               out3(op, rd);\r
+               break;\r
+\r
+       case S_ADI:\r
+               expr(&e, 0);\r
+               outab(op);\r
+               outrb(&e, 0);\r
+               break;\r
+\r
+       case S_ADD:\r
+               rd = reg();\r
+               if (rd > A)\r
+                       aerr();\r
+               outab(op | rd);\r
+               break;\r
+\r
+       case S_JMP:\r
+               expr(&e, 0);\r
+               outab(op);\r
+               outrw(&e, 0);\r
+               break;\r
+\r
+       case S_INR:\r
+               rd = reg();\r
+               if (rd > A)\r
+                       aerr();\r
+               out3(op, rd);\r
+               break;\r
+\r
+       case S_LXI:\r
+               rd = reg();\r
+               comma(1);\r
+               expr(&e, 0);\r
+               out3(op, regpair(rd, SP));\r
+               outrw(&e, 0);\r
+               break;\r
+\r
+       case S_LDAX:\r
+               rd = reg();\r
+               if (rd!=B && rd!=D)\r
+                       aerr();\r
+               out3(op, rd);\r
+               break;\r
+\r
+       case S_INX:\r
+               rd = reg();\r
+               out3(op, regpair(rd, SP));\r
+               break;\r
+\r
+       case S_PUSH:\r
+               rd = reg();\r
+               out3(op, regpair(rd, PSW));\r
+               break;\r
+\r
+       case S_MOV:\r
+               rd = reg();\r
+               comma(1);\r
+               rs = reg();\r
+               if (rs>A || rd>A)\r
+                       aerr();\r
+               outab(op | rs | (rd<<3));\r
+               break;\r
+\r
+       case S_MVI:\r
+               rd = reg();\r
+               comma(1);\r
+               expr(&e, 0);\r
+               if (rd > A)\r
+                       aerr();\r
+               out3(op, rd);\r
+               outrb(&e, 0);\r
+               break;\r
+\r
+       default:\r
+               opcycles = OPCY_ERR;\r
+               err('o');\r
+               break;\r
+       }\r
+       if (opcycles == OPCY_NONE) {\r
+               opcycles = i85pg1[cb[0] & 0xFF];\r
+       }\r
+}\r
+\r
+/*\r
+ * Output a | (b<<3);\r
+ */\r
+VOID\r
+out3(a, b)\r
+int a;\r
+int b;\r
+{\r
+       outab(a | (b<<3));\r
+}\r
+\r
+/*\r
+ * Make sure that `r' is usable as a\r
+ * register pair specifier. The extra\r
+ * register (code 3) is `s'.\r
+ */\r
+int\r
+regpair(r, s)\r
+int r;\r
+int s;\r
+{\r
+       if (r < M) {\r
+               if (r&01)\r
+                       aerr();\r
+       } else  if (r == s)\r
+               r = 6;\r
+       else\r
+               aerr();\r
+       return (r);\r
+}\r
+\r
+/*\r
+ * Read a register name.\r
+ */\r
+int\r
+reg()\r
+{\r
+       struct mne *mp;\r
+       char id[NCPS];\r
+\r
+       getid(id, -1);\r
+       if ((mp = mlookup(id))==NULL || mp->m_type!=S_REG) {\r
+               aerr();\r
+               return (0);\r
+       }\r
+       return ((int) mp->m_valu);\r
+}\r
+\r
+/*\r
+ *Machine specific initialization.\r
+ */\r
+VOID\r
+minit()\r
+{\r
+       /*\r
+        * Byte Order\r
+        */\r
+       hilo = 0;\r
+}\r

diff --git a/aslcop8/lcop8pst.c b/aslcop8/lcop8pst.c
new file mode 100644 (file)
index 0000000..b45d04f
--- /dev/null
+++ b/aslcop8/lcop8pst.c
@@ -0,0 +1,354 @@
+/* i85pst.c */\r
+\r
+/*\r
+ *  Copyright (C) 1989-2014  Alan R. Baldwin\r
+ *\r
+ *  This program is free software: you can redistribute it and/or modify\r
+ *  it under the terms of the GNU General Public License as published by\r
+ *  the Free Software Foundation, either version 3 of the License, or\r
+ *  (at your option) any later version.\r
+ *\r
+ *  This program is distributed in the hope that it will be useful,\r
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+ *  GNU General Public License for more details.\r
+ *\r
+ *  You should have received a copy of the GNU General Public License\r
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+ *\r
+ *\r
+ * Alan R. Baldwin\r
+ * 721 Berkeley St.\r
+ * Kent, Ohio  44240\r
+ *\r
+ *     Undocumented Instructions\r
+ *     implemented by:\r
+ *             John R. Hogerhuis\r
+ */\r
+\r
+#include "asxxxx.h"\r
+#include "lcop8.h"\r
+\r
+/*\r
+ * Coding Banks\r
+ */\r
+struct bank    bank[2] = {\r
+    /* The '_CODE' area/bank has a NULL default file suffix.   */\r
+    {  NULL,           "_CSEG",        NULL,           0,      0,      0,      0,      0       },\r
+    {  &bank[0],       "_DSEG",        "_DS",          1,      0,      0,      0,      B_FSFX  }\r
+};\r
+\r
+/*\r
+ * Coding Areas\r
+ */\r
+struct area    area[2] = {\r
+    {  NULL,           &bank[0],       "_CODE",        0,      0,      0,      A_1BYTE|A_BNK|A_CSEG    },\r
+    {  &area[0],       &bank[1],       "_DATA",        1,      0,      0,      A_1BYTE|A_BNK|A_DSEG    }\r
+};\r
+\r
+/*\r
+ * Basic Relocation Mode Definition\r
+ *\r
+ *     #define         R_NORM  0000            No Bit Positioning\r
+ */\r
+char   mode0[32] = {   /* R_NORM */\r
+       '\200', '\201', '\202', '\203', '\204', '\205', '\206', '\207',\r
+       '\210', '\211', '\212', '\213', '\214', '\215', '\216', '\217',\r
+       '\220', '\221', '\222', '\223', '\224', '\225', '\226', '\227',\r
+       '\230', '\231', '\232', '\233', '\234', '\235', '\236', '\237'\r
+};\r
+\r
+/*\r
+ * Additional Relocation Mode Definitions\r
+ */\r
+\r
+/* None Required */\r
+\r
+/*\r
+ *     *m_def is a pointer to the bit relocation definition.\r
+ *     m_flag indicates that bit position swapping is required.\r
+ *     m_dbits contains the active bit positions for the output.\r
+ *     m_sbits contains the active bit positions for the input.\r
+ *\r
+ *     struct  mode\r
+ *     {\r
+ *             char *  m_def;          Bit Relocation Definition\r
+ *             a_uint  m_flag;         Bit Swapping Flag\r
+ *             a_uint  m_dbits;        Destination Bit Mask\r
+ *             a_uint  m_sbits;        Source Bit Mask\r
+ *     };\r
+ */\r
+struct mode    mode[1] = {\r
+    {  &mode0[0],      0,      0x0000FFFF,     0x0000FFFF      }\r
+};\r
+\r
+/*\r
+ * Array of Pointers to mode Structures\r
+ */\r
+struct mode    *modep[16] = {\r
+       &mode[0],       NULL,           NULL,           NULL,\r
+       NULL,           NULL,           NULL,           NULL,\r
+       NULL,           NULL,           NULL,           NULL,\r
+       NULL,           NULL,           NULL,           NULL\r
+};\r
+\r
+/*\r
+ * Mnemonic Structure\r
+ */\r
+struct mne     mne[] = {\r
+\r
+       /* machine */\r
+\r
+       /* system */\r
+\r
+    {  NULL,   "CSEG",         S_ATYP,         0,      A_CSEG|A_1BYTE  },\r
+    {  NULL,   "DSEG",         S_ATYP,         0,      A_DSEG|A_1BYTE  },\r
+\r
+       /* system */\r
+\r
+    {  NULL,   "BANK",         S_ATYP,         0,      A_BNK   },\r
+    {  NULL,   "CON",          S_ATYP,         0,      A_CON   },\r
+    {  NULL,   "OVR",          S_ATYP,         0,      A_OVR   },\r
+    {  NULL,   "REL",          S_ATYP,         0,      A_REL   },\r
+    {  NULL,   "ABS",          S_ATYP,         0,      A_ABS   },\r
+    {  NULL,   "NOPAG",        S_ATYP,         0,      A_NOPAG },\r
+    {  NULL,   "PAG",          S_ATYP,         0,      A_PAG   },\r
+\r
+    {  NULL,   "BASE",         S_BTYP,         0,      B_BASE  },\r
+    {  NULL,   "SIZE",         S_BTYP,         0,      B_SIZE  },\r
+    {  NULL,   "FSFX",         S_BTYP,         0,      B_FSFX  },\r
+    {  NULL,   "MAP",          S_BTYP,         0,      B_MAP   },\r
+\r
+    {  NULL,   ".page",        S_PAGE,         0,      0       },\r
+    {  NULL,   ".title",       S_HEADER,       0,      O_TITLE },\r
+    {  NULL,   ".sbttl",       S_HEADER,       0,      O_SBTTL },\r
+    {  NULL,   ".module",      S_MODUL,        0,      0       },\r
+    {  NULL,   ".include",     S_INCL,         0,      0       },\r
+    {  NULL,   ".area",        S_AREA,         0,      0       },\r
+    {  NULL,   ".bank",        S_BANK,         0,      0       },\r
+    {  NULL,   ".org",         S_ORG,          0,      0       },\r
+    {  NULL,   ".radix",       S_RADIX,        0,      0       },\r
+    {  NULL,   ".globl",       S_GLOBL,        0,      0       },\r
+    {  NULL,   ".local",       S_LOCAL,        0,      0       },\r
+    {  NULL,   ".if",          S_CONDITIONAL,  0,      O_IF    },\r
+    {  NULL,   ".iff",         S_CONDITIONAL,  0,      O_IFF   },\r
+    {  NULL,   ".ift",         S_CONDITIONAL,  0,      O_IFT   },\r
+    {  NULL,   ".iftf",        S_CONDITIONAL,  0,      O_IFTF  },\r
+    {  NULL,   ".ifdef",       S_CONDITIONAL,  0,      O_IFDEF },\r
+    {  NULL,   ".ifndef",      S_CONDITIONAL,  0,      O_IFNDEF},\r
+    {  NULL,   ".ifgt",        S_CONDITIONAL,  0,      O_IFGT  },\r
+    {  NULL,   ".iflt",        S_CONDITIONAL,  0,      O_IFLT  },\r
+    {  NULL,   ".ifge",        S_CONDITIONAL,  0,      O_IFGE  },\r
+    {  NULL,   ".ifle",        S_CONDITIONAL,  0,      O_IFLE  },\r
+    {  NULL,   ".ifeq",        S_CONDITIONAL,  0,      O_IFEQ  },\r
+    {  NULL,   ".ifne",        S_CONDITIONAL,  0,      O_IFNE  },\r
+    {  NULL,   ".ifb",         S_CONDITIONAL,  0,      O_IFB   },\r
+    {  NULL,   ".ifnb",        S_CONDITIONAL,  0,      O_IFNB  },\r
+    {  NULL,   ".ifidn",       S_CONDITIONAL,  0,      O_IFIDN },\r
+    {  NULL,   ".ifdif",       S_CONDITIONAL,  0,      O_IFDIF },\r
+    {  NULL,   ".iif",         S_CONDITIONAL,  0,      O_IIF   },\r
+    {  NULL,   ".iiff",        S_CONDITIONAL,  0,      O_IIFF  },\r
+    {  NULL,   ".iift",        S_CONDITIONAL,  0,      O_IIFT  },\r
+    {  NULL,   ".iiftf",       S_CONDITIONAL,  0,      O_IIFTF },\r
+    {  NULL,   ".iifdef",      S_CONDITIONAL,  0,      O_IIFDEF},\r
+    {  NULL,   ".iifndef",     S_CONDITIONAL,  0,      O_IIFNDEF},\r
+    {  NULL,   ".iifgt",       S_CONDITIONAL,  0,      O_IIFGT },\r
+    {  NULL,   ".iiflt",       S_CONDITIONAL,  0,      O_IIFLT },\r
+    {  NULL,   ".iifge",       S_CONDITIONAL,  0,      O_IIFGE },\r
+    {  NULL,   ".iifle",       S_CONDITIONAL,  0,      O_IIFLE },\r
+    {  NULL,   ".iifeq",       S_CONDITIONAL,  0,      O_IIFEQ },\r
+    {  NULL,   ".iifne",       S_CONDITIONAL,  0,      O_IIFNE },\r
+    {  NULL,   ".iifb",        S_CONDITIONAL,  0,      O_IIFB  },\r
+    {  NULL,   ".iifnb",       S_CONDITIONAL,  0,      O_IIFNB },\r
+    {  NULL,   ".iifidn",      S_CONDITIONAL,  0,      O_IIFIDN},\r
+    {  NULL,   ".iifdif",      S_CONDITIONAL,  0,      O_IIFDIF},\r
+    {  NULL,   ".else",        S_CONDITIONAL,  0,      O_ELSE  },\r
+    {  NULL,   ".endif",       S_CONDITIONAL,  0,      O_ENDIF },\r
+    {  NULL,   ".list",        S_LISTING,      0,      O_LIST  },\r
+    {  NULL,   ".nlist",       S_LISTING,      0,      O_NLIST },\r
+    {  NULL,   ".equ",         S_EQU,          0,      O_EQU   },\r
+    {  NULL,   ".gblequ",      S_EQU,          0,      O_GBLEQU},\r
+    {  NULL,   ".lclequ",      S_EQU,          0,      O_LCLEQU},\r
+    {  NULL,   ".byte",        S_DATA,         0,      O_1BYTE },\r
+    {  NULL,   ".db",          S_DATA,         0,      O_1BYTE },\r
+    {  NULL,   ".fcb",         S_DATA,         0,      O_1BYTE },\r
+    {  NULL,   ".word",        S_DATA,         0,      O_2BYTE },\r
+    {  NULL,   ".dw",          S_DATA,         0,      O_2BYTE },\r
+    {  NULL,   ".fdb",         S_DATA,         0,      O_2BYTE },\r
+/*    {        NULL,   ".3byte",       S_DATA,         0,      O_3BYTE },      */\r
+/*    {        NULL,   ".triple",      S_DATA,         0,      O_3BYTE },      */\r
+/*    {        NULL,   ".4byte",       S_DATA,         0,      O_4BYTE },      */\r
+/*    {        NULL,   ".quad",        S_DATA,         0,      O_4BYTE },      */\r
+    {  NULL,   ".blkb",        S_BLK,          0,      O_1BYTE },\r
+    {  NULL,   ".ds",          S_BLK,          0,      O_1BYTE },\r
+    {  NULL,   ".rmb",         S_BLK,          0,      O_1BYTE },\r
+    {  NULL,   ".rs",          S_BLK,          0,      O_1BYTE },\r
+    {  NULL,   ".blkw",        S_BLK,          0,      O_2BYTE },\r
+/*    {        NULL,   ".blk3",        S_BLK,          0,      O_3BYTE },      */\r
+/*    {        NULL,   ".blk4",        S_BLK,          0,      O_4BYTE },      */\r
+    {  NULL,   ".ascii",       S_ASCIX,        0,      O_ASCII },\r
+    {  NULL,   ".ascis",       S_ASCIX,        0,      O_ASCIS },\r
+    {  NULL,   ".asciz",       S_ASCIX,        0,      O_ASCIZ },\r
+    {  NULL,   ".str",         S_ASCIX,        0,      O_ASCII },\r
+    {  NULL,   ".strs",        S_ASCIX,        0,      O_ASCIS },\r
+    {  NULL,   ".strz",        S_ASCIX,        0,      O_ASCIZ },\r
+    {  NULL,   ".fcc",         S_ASCIX,        0,      O_ASCII },\r
+    {  NULL,   ".define",      S_DEFINE,       0,      O_DEF   },\r
+    {  NULL,   ".undefine",    S_DEFINE,       0,      O_UNDEF },\r
+    {  NULL,   ".even",        S_BOUNDARY,     0,      O_EVEN  },\r
+    {  NULL,   ".odd",         S_BOUNDARY,     0,      O_ODD   },\r
+    {  NULL,   ".bndry",       S_BOUNDARY,     0,      O_BNDRY },\r
+    {  NULL,   ".msg"  ,       S_MSG,          0,      0       },\r
+    {  NULL,   ".assume",      S_ERROR,        0,      O_ASSUME},\r
+    {  NULL,   ".error",       S_ERROR,        0,      O_ERROR },\r
+/*    {        NULL,   ".msb",         S_MSB,          0,      0       },      */\r
+/*    {        NULL,   ".lohi",        S_MSB,          0,      O_LOHI  },      */\r
+/*    {        NULL,   ".hilo",        S_MSB,          0,      O_HILO  },      */\r
+/*    {        NULL,   ".8bit",        S_BITS,         0,      O_1BYTE },      */\r
+/*    {        NULL,   ".16bit",       S_BITS,         0,      O_2BYTE },      */\r
+/*    {        NULL,   ".24bit",       S_BITS,         0,      O_3BYTE },      */\r
+/*    {        NULL,   ".32bit",       S_BITS,         0,      O_4BYTE },      */\r
+    {  NULL,   ".end",         S_END,          0,      0       },\r
+\r
+       /* Macro Processor */\r
+\r
+    {  NULL,   ".macro",       S_MACRO,        0,      O_MACRO },\r
+    {  NULL,   ".endm",        S_MACRO,        0,      O_ENDM  },\r
+    {  NULL,   ".mexit",       S_MACRO,        0,      O_MEXIT },\r
+\r
+    {  NULL,   ".narg",        S_MACRO,        0,      O_NARG  },\r
+    {  NULL,   ".nchr",        S_MACRO,        0,      O_NCHR  },\r
+    {  NULL,   ".ntyp",        S_MACRO,        0,      O_NTYP  },\r
+\r
+    {  NULL,   ".irp",         S_MACRO,        0,      O_IRP   },\r
+    {  NULL,   ".irpc",        S_MACRO,        0,      O_IRPC  },\r
+    {  NULL,   ".rept",        S_MACRO,        0,      O_REPT  },\r
+\r
+    {  NULL,   ".nval",        S_MACRO,        0,      O_NVAL  },\r
+\r
+    {  NULL,   ".mdelete",     S_MACRO,        0,      O_MDEL  },\r
+\r
+       /* 8080/8085 */\r
+\r
+    {  NULL,   "b",            S_REG,          0,      B       },\r
+    {  NULL,   "c",            S_REG,          0,      C       },\r
+    {  NULL,   "bc",           S_REG,          0,      B       },\r
+    {  NULL,   "d",            S_REG,          0,      D       },\r
+    {  NULL,   "e",            S_REG,          0,      E       },\r
+    {  NULL,   "de",           S_REG,          0,      D       },\r
+    {  NULL,   "h",            S_REG,          0,      H       },\r
+    {  NULL,   "l",            S_REG,          0,      L       },\r
+    {  NULL,   "hl",           S_REG,          0,      H       },\r
+    {  NULL,   "m",            S_REG,          0,      M       },\r
+    {  NULL,   "psw",          S_REG,          0,      PSW     },\r
+    {  NULL,   "a",            S_REG,          0,      A       },\r
+    {  NULL,   "af",           S_REG,          0,      PSW     },\r
+    {  NULL,   "sp",           S_REG,          0,      SP      },\r
+\r
+    {  NULL,   "xthl",         S_INH,          0,      0343    },\r
+    {  NULL,   "sphl",         S_INH,          0,      0371    },\r
+    {  NULL,   "pchl",         S_INH,          0,      0351    },\r
+    {  NULL,   "xchg",         S_INH,          0,      0353    },\r
+    {  NULL,   "ret",          S_INH,          0,      0311    },\r
+    {  NULL,   "rc",           S_INH,          0,      0330    },\r
+    {  NULL,   "rnc",          S_INH,          0,      0320    },\r
+    {  NULL,   "rz",           S_INH,          0,      0310    },\r
+    {  NULL,   "rnz",          S_INH,          0,      0300    },\r
+    {  NULL,   "rp",           S_INH,          0,      0360    },\r
+    {  NULL,   "rm",           S_INH,          0,      0370    },\r
+    {  NULL,   "rpe",          S_INH,          0,      0350    },\r
+    {  NULL,   "rpo",          S_INH,          0,      0340    },\r
+    {  NULL,   "rim",          S_INH,          0,      0040    },\r
+    {  NULL,   "rlc",          S_INH,          0,      0007    },\r
+    {  NULL,   "rrc",          S_INH,          0,      0017    },\r
+    {  NULL,   "ral",          S_INH,          0,      0027    },\r
+    {  NULL,   "rar",          S_INH,          0,      0037    },\r
+    {  NULL,   "cma",          S_INH,          0,      0057    },\r
+    {  NULL,   "stc",          S_INH,          0,      0067    },\r
+    {  NULL,   "cmc",          S_INH,          0,      0077    },\r
+    {  NULL,   "daa",          S_INH,          0,      0047    },\r
+    {  NULL,   "ei",           S_INH,          0,      0373    },\r
+    {  NULL,   "di",           S_INH,          0,      0363    },\r
+    {  NULL,   "nop",          S_INH,          0,      0000    },\r
+    {  NULL,   "hlt",          S_INH,          0,      0166    },\r
+    {  NULL,   "sim",          S_INH,          0,      0060    },\r
+\r
+    {  NULL,   "rst",          S_RST,          0,      0307    },\r
+\r
+    {  NULL,   "in",           S_ADI,          0,      0333    },\r
+    {  NULL,   "out",          S_ADI,          0,      0323    },\r
+    {  NULL,   "adi",          S_ADI,          0,      0306    },\r
+    {  NULL,   "aci",          S_ADI,          0,      0316    },\r
+    {  NULL,   "sui",          S_ADI,          0,      0326    },\r
+    {  NULL,   "sbi",          S_ADI,          0,      0336    },\r
+    {  NULL,   "ani",          S_ADI,          0,      0346    },\r
+    {  NULL,   "xri",          S_ADI,          0,      0356    },\r
+    {  NULL,   "ori",          S_ADI,          0,      0366    },\r
+    {  NULL,   "cpi",          S_ADI,          0,      0376    },\r
+\r
+    {  NULL,   "add",          S_ADD,          0,      0200    },\r
+    {  NULL,   "adc",          S_ADD,          0,      0210    },\r
+    {  NULL,   "sub",          S_ADD,          0,      0220    },\r
+    {  NULL,   "sbb",          S_ADD,          0,      0230    },\r
+    {  NULL,   "ana",          S_ADD,          0,      0240    },\r
+    {  NULL,   "xra",          S_ADD,          0,      0250    },\r
+    {  NULL,   "ora",          S_ADD,          0,      0260    },\r
+    {  NULL,   "cmp",          S_ADD,          0,      0270    },\r
+\r
+    {  NULL,   "sta",          S_JMP,          0,      0062    },\r
+    {  NULL,   "lda",          S_JMP,          0,      0072    },\r
+    {  NULL,   "shld",         S_JMP,          0,      0042    },\r
+    {  NULL,   "lhld",         S_JMP,          0,      0052    },\r
+    {  NULL,   "jmp",          S_JMP,          0,      0303    },\r
+    {  NULL,   "jc",           S_JMP,          0,      0332    },\r
+    {  NULL,   "jnc",          S_JMP,          0,      0322    },\r
+    {  NULL,   "jz",           S_JMP,          0,      0312    },\r
+    {  NULL,   "jnz",          S_JMP,          0,      0302    },\r
+    {  NULL,   "jp",           S_JMP,          0,      0362    },\r
+    {  NULL,   "jm",           S_JMP,          0,      0372    },\r
+    {  NULL,   "jpe",          S_JMP,          0,      0352    },\r
+    {  NULL,   "jpo",          S_JMP,          0,      0342    },\r
+    {  NULL,   "call",         S_JMP,          0,      0315    },\r
+    {  NULL,   "cc",           S_JMP,          0,      0334    },\r
+    {  NULL,   "cnc",          S_JMP,          0,      0324    },\r
+    {  NULL,   "cz",           S_JMP,          0,      0314    },\r
+    {  NULL,   "cnz",          S_JMP,          0,      0304    },\r
+    {  NULL,   "cp",           S_JMP,          0,      0364    },\r
+    {  NULL,   "cm",           S_JMP,          0,      0374    },\r
+    {  NULL,   "cpe",          S_JMP,          0,      0354    },\r
+    {  NULL,   "cpo",          S_JMP,          0,      0344    },\r
+\r
+    {  NULL,   "inr",          S_INR,          0,      0004    },\r
+    {  NULL,   "dcr",          S_INR,          0,      0005    },\r
+\r
+    {  NULL,   "lxi",          S_LXI,          0,      0001    },\r
+\r
+    {  NULL,   "ldax",         S_LDAX,         0,      0012    },\r
+    {  NULL,   "stax",         S_LDAX,         0,      0002    },\r
+\r
+    {  NULL,   "inx",          S_INX,          0,      0003    },\r
+    {  NULL,   "dcx",          S_INX,          0,      0013    },\r
+    {  NULL,   "dad",          S_INX,          0,      0011    },\r
+\r
+    {  NULL,   "push",         S_PUSH,         0,      0305    },\r
+    {  NULL,   "pop",          S_PUSH,         0,      0301    },\r
+\r
+    {  NULL,   "mov",          S_MOV,          0,      0100    },\r
+\r
+    {  NULL,   "mvi",          S_MVI,          0,      0006    },\r
+\r
+       /* Undocumented 8085 Opcodes */\r
+\r
+    {  NULL,   "dsub",         S_INH,          0,      0010    },\r
+    {  NULL,   "arhl",         S_INH,          0,      0020    },\r
+    {  NULL,   "rdel",         S_INH,          0,      0030    },\r
+    {  NULL,   "rstv",         S_INH,          0,      0313    },\r
+    {  NULL,   "shlx",         S_INH,          0,      0331    },\r
+    {  NULL,   "lhlx",         S_INH,          0,      0355    },\r
+\r
+    {  NULL,   "ldhi",         S_ADI,          0,      0050    },\r
+    {  NULL,   "ldsi",         S_ADI,          0,      0070    },\r
+\r
+    {  NULL,   "jnx5",         S_JMP,          0,      0335    },\r
+    {  NULL,   "jx5",          S_JMP,          S_EOL,  0375    }\r
+};\r

diff --git a/asxmak/linux/build/makefile b/asxmak/linux/build/makefile
index 136ac16..e08d545 100644 (file)
--- a/asxmak/linux/build/makefile
+++ b/asxmak/linux/build/makefile
@@ -40,6 +40,7 @@ all:  as1802          \
        asf8            \\r
        asgb            \\r
        ash8            \\r
+       aslcop8         \\r
        asm8c           \\r
        aspdp11         \\r
        aspic           \\r
@@ -94,6 +95,7 @@ clean:
        rm -f $(SRCF8)*.o\r
        rm -f $(SRCGB)*.o\r
        rm -f $(SRCH8)*.o\r
+       rm -f $(SRCLCOP8)*.o\r
        rm -f $(SRCM8C)*.o\r
        rm -f $(SRCPIC)*.o\r
        rm -f $(SRCRAB)*.o\r
@@ -135,6 +137,7 @@ clean:
        rm -f asf8\r
        rm -f asgb\r
        rm -f ash8\r
+       rm -f aslcop8\r
        rm -f asm8c\r
        rm -f aspdp11\r
        rm -f aspic\r
@@ -190,6 +193,7 @@ prep:
        rm -f $(SRCF8)*.o\r
        rm -f $(SRCGB)*.o\r
        rm -f $(SRCH8)*.o\r
+       rm -f $(SRCLCOP8)*.o\r
        rm -f $(SRCM8C)*.o\r
        rm -f $(SRCPIC)*.o\r
        rm -f $(SRCRAB)*.o\r
@@ -231,6 +235,7 @@ prep:
        rm -f asf8\r
        rm -f asgb\r
        rm -f ash8\r
+       rm -f aslcop8\r
        rm -f asm8c\r
        rm -f aspdp11\r
        rm -f aspic\r
@@ -301,6 +306,7 @@ SRCF2MC8=   $(ASXBAS)asf2mc8/
 SRCF8=         $(ASXBAS)asf8/\r
 SRCGB=         $(ASXBAS)asgb/\r
 SRCH8=         $(ASXBAS)ash8/\r
+SRCLCOP8=      $(ASXBAS)aslcop8/\r
 SRCM8C=                $(ASXBAS)asm8c/\r
 SRCPDP11=      $(ASXBAS)aspdp11/\r
 SRCPIC=                $(ASXBAS)aspic/\r
@@ -870,6 +876,23 @@ ash8:      $(ASXXSRC) $(ASH8SRC)
        chmod 755 $(DSTEXE)ash8\r
 \r
 \r
+####################################################################\r
+# ASLCOP8\r
+####################################################################\r
+\r
+ASLCOP8 =      lcop8mch.o lcop8pst.o\r
+\r
+ASLCOP8SRC =   $(addprefix $(SRCLCOP8),$(ASLCOP8))\r
+\r
+$(ASLCOP8SRC): $(SRCMISC)alloc.h $(SRCASX)asxxxx.h $(SRCLCOP8)lcop8.h\r
+\r
+aslcop8:       $(ASXXSRC) $(ASLCOP8SRC)\r
+       $(LD) $(LDFLAGS) $(ASXXSRC) $(ASLCOP8SRC) -o aslcop8\r
+       cp aslcop8 $(DSTEXE)aslcop8\r
+       strip $(DSTEXE)aslcop8\r
+       chmod 755 $(DSTEXE)aslcop8\r
+\r
+\r
 ####################################################################\r
 # ASM8C\r
 ####################################################################\r

diff --git a/n.sh b/n.sh
index 90299a9..7e70cbb 100755 (executable)
--- a/n.sh
+++ b/n.sh
@@ -1,4 +1,6 @@
 #!/bin/sh
+mkdir --parents asxmak/linux/exe
 #make -C asxmak/linux/build asz80 aslink
-make -C asxmak/linux/build aspdp11 aslink
+#make -C asxmak/linux/build aspdp11 aslink
+make -C asxmak/linux/build aslcop8 aslink
 cp asxmak/linux/exe/as* $HOME/bin