4 * Copyright (C) 2012-2014 Alan R. Baldwin
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6 * This program is free software: you can redistribute it and/or modify
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7 * it under the terms of the GNU General Public License as published by
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8 * the Free Software Foundation, either version 3 of the License, or
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9 * (at your option) any later version.
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11 * This program is distributed in the hope that it will be useful,
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 * GNU General Public License for more details.
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16 * You should have received a copy of the GNU General Public License
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17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
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28 char *cpu = "Fairchild F8 / Mostek 3870";
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32 * Opcode Cycle Definitions
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34 #define OPCY_SDP ((char) (0xFF))
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35 #define OPCY_ERR ((char) (0xFE))
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37 /* OPCY_NONE ((char) (0x80)) */
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38 /* OPCY_MASK ((char) (0x7F)) */
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40 #define UN ((char) (OPCY_NONE | 0x00))
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45 * opcycles = f8cyc[opcode]
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48 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
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49 /*--*--* - - - - - - - - - - - - - - - - */
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50 /*00*/ 4, 4, 4, 4, 4, 4, 4, 4,16,16, 4, 4,16,16,16,16,
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51 /*10*/ 16,16, 4, 4, 4, 4,10,10, 4, 4, 8, 8, 8, 8, 4, 4,
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52 /*20*/ 10,10,10,10,10,10,16,16,26,22,24, 4, 8,UN,UN,UN,
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53 /*30*/ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,UN,
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54 /*40*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,UN,
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55 /*50*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,UN,
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56 /*60*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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57 /*70*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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58 /*80*/ 14,14,14,14,14,14,14,14,10,10,10,10,10,10,10,14,
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59 /*90*/ 14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,
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60 /*A0*/ 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
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61 /*B0*/ 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
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62 /*C0*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,UN,
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63 /*D0*/ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,UN,
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64 /*E0*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,UN,
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65 /*F0*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,UN
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69 * Process a machine op.
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82 op = (int) mp->m_valu;
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83 switch (mp->m_type) {
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91 outrbm(&e1, M_3BIT | R_MBRU, op);
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92 if ((t1 != S_IMMED) && (t1 != S_EXT)) {
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102 outrbm(&e1, M_4BIT | R_MBRU, op);
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103 if ((t1 != S_IMMED) && (t1 != S_EXT)) {
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119 outrb(&e1, R_NORM);
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120 if ((t1 != S_IMMED) && (t1 != S_EXT)) {
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132 outrw(&e1, R_NORM);
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133 if ((t1 != S_IMMED) && (t1 != S_EXT)) {
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146 if ((t1 == S_IMMED) || ( t1 == S_EXT)) {
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147 if (e1.e_addr == (a_uint) 1) {
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150 if (e1.e_addr == (a_uint) 4) {
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156 if (!is_abs(&e1)) {
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175 if (((t1 == S_RAIW) && (a1 == S_A)) && ((t2 == S_RAIW) && (a2 == S_IS))) {
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179 if (((t1 == S_RAIW) && (a1 == S_IS)) && ((t2 == S_RAIW) && (a2 == S_A))) {
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183 if (((t1 == S_RAIW) && (a1 == S_W)) && ((t2 == S_R8) && (a2 == S_J))) {
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187 if (((t1 == S_R8) && (a1 == S_J)) && ((t2 == S_RAIW) && (a2 == S_W))) {
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194 if (((t1 == S_RAIW) && (a1 == S_A)) && (t2 == S_RKQ)) {
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195 outab(0x00 | (a2 & 0x03));
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201 if ((t1 == S_RKQ) && ((t2 == S_RAIW) && (a2 == S_A))) {
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202 outab(0x04 | (a1 & 0x03));
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205 if (((t1 == S_RAIW) && (a1 == S_A)) && ((t2 == S_R8) || (t2 == S_RSID))) {
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209 if (((t1 == S_R8) || (t1 == S_RSID)) && ((t2 == S_RAIW) && (a2 == S_A))) {
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213 if (((t1 == S_R16) && (a1 == S_Q)) && ((t2 == S_R16) && (a2 == S_DC))) {
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217 if (((t1 == S_R16) && (a1 == S_DC)) && ((t2 == S_R16) && (a2 == S_Q))) {
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221 if (((t1 == S_R16) && (a1 == S_H)) && ((t2 == S_R16) && (a2 == S_DC))) {
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225 if (((t1 == S_R16) && (a1 == S_DC)) && ((t2 == S_R16) && (a2 == S_H))) {
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229 if (((t1 == S_R16) && (a1 == S_P)) && ((t2 == S_R16) && (a2 == S_K))) {
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233 if (((t1 == S_R16) && (a1 == S_K)) && ((t2 == S_R16) && (a2 == S_P))) {
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237 if (((t1 == S_R16) && (a1 == S_P0)) && ((t2 == S_R16) && (a2 == S_Q))) {
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255 if ((t1 == S_R8) || (t1 == S_RSID)) {
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269 if ((t1 != S_IMMED) && (t1 != S_EXT)) {
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273 outrb(&e1, R_NORM);
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282 if ((t1 != S_IMMED) && (t1 != S_EXT)) {
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285 outrbm(&e1, M_4BIT | R_MBRU, op);
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302 v1 = (int) (e1.e_addr - dot.s_addr - 1);
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303 if ((v1 < -128) || (v1 > 127)) {
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310 if (e1.e_mode != S_USER) {
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320 if ((t1 != S_IMMED) && (t1 != S_EXT)) {
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325 if (e2.e_mode != S_USER) {
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328 outrbm(&e1, M_3BIT | R_MBRO, op);
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330 v2 = (int) (e2.e_addr - dot.s_addr - 1);
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331 if ((v2 < -128) || (v2 > 127)) {
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345 if ((t1 != S_IMMED) && (t1 != S_EXT)) {
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350 if (e2.e_mode != S_USER) {
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353 outrbm(&e1, M_4BIT | R_MBRO, op);
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355 v2 = (int) (e2.e_addr - dot.s_addr - 1);
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356 if ((v2 < -128) || (v2 > 127)) {
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395 opcycles = OPCY_ERR;
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400 if (opcycles == OPCY_NONE) {
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401 opcycles = f8cyc[cb[0] & 0xFF];
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406 * Branch/Jump PCR Mode Check
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412 if (esp->e_base.e_ap == dot.s_area) {
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415 if (esp->e_flag==0 && esp->e_base.e_ap==NULL) {
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417 * Absolute Destination
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419 * Use the global symbol '.__.ABS.'
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420 * of value zero and force the assembler
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421 * to use this absolute constant as the
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422 * base value for the relocation.
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425 esp->e_base.e_sp = &sym[1];
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431 * Machine dependent initialization
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