# These flags should be fine for most cases
APOUT_OPTIONS?= -DNATIVES -DDEBUG
ifeq ($(CPU),PDP11)
-APOUT_OPTIONS+= -DEMU211 -DEMUv1
+APOUT_OPTIONS+= -DEMU211 -DEMUV1
endif
# These flags for speed
OBJS+= v1trap.o pdp11/branch.o pdp11/cpu.o pdp11/debug.o \
pdp11/double.o pdp11/ea.o pdp11/fp.o pdp11/itab.o pdp11/ke11a.o \
pdp11/single.o
-else ($(CPU),Z180)
-OBJS+= z180/cpu.o
+else ifeq ($(CPU),Z180)
+OBJS+= z180/cpu.o z180/z180.o z180/z180dasm.o
endif
apout: $(OBJS)
pdp11/single.o: pdp11/single.c defines.h pdp11/cpu.h Makefile
v1trap.o: v1trap.c v1trap.h defines.h pdp11/cpu.h z180/cpu.h Makefile
v7trap.o: v7trap.c v7trap.h defines.h pdp11/cpu.h z180/cpu.h Makefile
-z180/cpu.o: z180/cpu.c defines.h z180/cpu.h z180/cpu.h Makefile
+z180/cpu.o: z180/cpu.c defines.h z180/cpu.h z180/z180.h z180/z180dasm.h \
+ Makefile
+z180/z180.o: z180/z180.c z180/z180ops.inc z180/z180tbl.inc z180/z180cb.inc \
+ z180/z180xy.inc z180/z180dd.inc z180/z180fd.inc z180/z180ed.inc \
+ z180/z180op.inc z180/z180.h z180/debugger.h z180/emu.h \
+ z180/logmacro.h Makefile
+z180/z180.o: z180/z180dasm.c z180/z180dasm.h z180/debugger.h z180/emu.h \
+ z180/logmacro.h Makefile
--- /dev/null
+#ifndef _RASSERT_H
+#define _RASSERT_H 1
+
+// tries to be the same as assert(), but always present even with NDEBUG
+
+#ifdef __FUZIX__
+extern void __assert(const char *__expr, const char *__file, const int __line);
+
+#if 1 // smaller code
+#define rassert(expr) \
+ ((void) ((expr) || (__assert ("", __FILE__, __LINE__), 0)))
+#else
+#define rassert(expr) \
+ ((void) ((expr) || (__assert (__STRING(expr), __FILE__, __LINE__), 0)))
+#endif
+#elif defined(__GLIBC__)
+extern void __assert_fail (const char *__assertion, const char *__file,
+ unsigned int __line, const char *__function)
+ __THROW __attribute__ ((__noreturn__));
+
+# define rassert(expr) \
+ ((expr) \
+ ? (void) (0) \
+ : __assert_fail (#expr, __FILE__, __LINE__, __extension__ __PRETTY_FUNCTION__))
+#else
+// for unsupported platforms, it won't work with NDEBUG
+#include <assert.h>
+
+#define rassert(expr) assert(expr)
+#endif
+
+#endif
*/
#include <assert.h>
#include <stdbool.h>
-#include "defines.h"
#include <unistd.h>
+#include "defines.h"
+#include "emu.h"
+#include "z180.h"
u_int16_t *adptr; /* used in memory access macros */
+void daisy_call_reti_device(void) {
+}
+device_z80daisy_interface *daisy_get_irq_device(void) {
+ return NULL;
+}
+int intf_z80daisy_irq_ack(void) {
+ return 0;
+}
+int standard_irq_callback_member(int arg) {
+ return 0;
+}
+bool daisy_chain_present(void) {
+ return false;
+}
+int daisy_update_irq_state(void) {
+ return 0;
+}
+
+void debugger_instruction_hook(offs_t address) {
+}
+
+const char *tag(void) {
+ return "nick";
+}
+uint8_t opcodes_r8(offs_t address) {
+ return 0;
+}
+uint8_t params_r8(offs_t address) {
+ return 0;
+}
+uint16_t params_r16(offs_t address) {
+ return 0;
+}
+
+u8 m_iospace_read_byte(offs_t address) {
+ return 0;
+}
+u8 m_program_read_byte(offs_t address) {
+ return 0;
+}
+u8 m_ocache_read_byte(offs_t address) {
+ return 0;
+}
+u8 m_cache_read_byte(offs_t address) {
+ return 0;
+}
+void m_iospace_write_byte(offs_t address, u8 data) {
+}
+void m_program_write_byte(offs_t address, u8 data) {
+}
+void m_ocache_write_byte(offs_t address, u8 data) {
+}
+void m_cache_write_byte(offs_t address, u8 data) {
+}
+
void run(void) {
assert(false);
}
--- /dev/null
+#ifndef _DEBUGGER_H
+#define _DEBUGGER_H
+
+void debugger_instruction_hook(offs_t address);
+
+#endif
--- /dev/null
+#ifndef _EMU_H
+#define _EMU_H 1
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+
+// this must be large enough to hold a physical address:
+typedef uint32_t offs_t;
+
+//#include <memory>
+#include <stdlib.h>
+#include "rassert.h"
+
+//class device_state_entry {
+//};
+//
+//class device_t {
+//public:
+// virtual void device_start() = 0;
+// virtual void device_reset() = 0;
+//};
+//
+//class cpu_device : public device_t {
+//public:
+// int *m_icountptr;
+//
+// cpu_device() : m_icountptr(NULL) {}
+// virtual uint32_t execute_min_cycles() const = 0;
+// virtual uint32_t execute_max_cycles() const = 0;
+// virtual uint32_t execute_input_lines() const = 0;
+// virtual uint32_t execute_default_irq_vector(int inputnum) const = 0;
+// virtual bool execute_input_edge_triggered(int inputnum) const = 0;
+// virtual void execute_run() = 0;
+// virtual void execute_burn(int32_t cycles) = 0;
+// virtual void execute_set_input(int inputnum, int state) = 0;
+// void set_icountptr(int &icount) {
+// assert(!m_icountptr);
+// m_icountptr = &icount;
+// }
+// int standard_irq_callback_member(device_t &device, int irqline) {
+// return standard_irq_callback(device, irqline);
+// }
+// virtual int standard_irq_callback(device_t &device, int irqline) = 0;
+//};
+//
+//class machine_config {
+//};
+//
+//class address_space {
+//public:
+// virtual u8 read_byte(offs_t address) = 0;
+u8 m_iospace_read_byte(offs_t address);
+u8 m_program_read_byte(offs_t address);
+u8 m_ocache_read_byte(offs_t address);
+u8 m_cache_read_byte(offs_t address);
+// virtual void write_byte(offs_t address, u8 data) = 0;
+void m_iospace_write_byte(offs_t address, u8 data);
+void m_program_write_byte(offs_t address, u8 data);
+void m_ocache_write_byte(offs_t address, u8 data);
+void m_cache_write_byte(offs_t address, u8 data);
+//};
+
+// PAIR is an endian-safe union useful for representing 32-bit CPU registers
+typedef union PAIR
+{
+//#ifdef LSB_FIRST
+ struct { u8 l,h,h2,h3; } b;
+ struct { u16 l,h; } w;
+ struct { s8 l,h,h2,h3; } sb;
+ struct { s16 l,h; } sw;
+//#else
+// struct { u8 h3,h2,h,l; } b;
+// struct { s8 h3,h2,h,l; } sb;
+// struct { u16 h,l; } w;
+// struct { s16 h,l; } sw;
+//#endif
+ u32 d;
+ s32 sd;
+} PAIR;
+
+enum {
+ INPUT_LINE_NMI = -1
+ // device specific input lines start at 0
+};
+
+enum {
+ CLEAR_LINE,
+ ASSERT_LINE
+};
+
+const char *tag(void);
+uint8_t opcodes_r8(offs_t address);
+uint8_t params_r8(offs_t address);
+uint16_t params_r16(offs_t address);
+enum {
+ STEP_OUT = 1,
+ STEP_OVER = 2,
+ SUPPORTED = 4
+};
+
+#endif
--- /dev/null
+#ifndef _LOGMACRO_H
+#define _LOGMACRO_H
+
+#include <stdio.h>
+
+#define LOG printf
+#define logerror printf
+
+#endif
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+/*****************************************************************************
+ *
+ * z180.c
+ * Portable Z180 emulator V0.3
+ *
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ TODO:
+ - HALT processing is not yet perfect. The manual states that
+ during HALT, all dma and internal i/o incl. timers continue to
+ work. Currently, only timers are implemented. Ideally, the
+ burn_cycles routine would go away and halt processing be
+ implemented in cpu_execute.
+ *****************************************************************************/
+
+/*****************************************************************************
+
+Z180 Info:
+
+Known clock speeds (from ZiLOG): 6, 8, 10, 20 & 33MHz
+
+ZiLOG Z180 codes:
+
+ Speed: 10 = 10MHZ
+ 20 = 20MHz
+ 33 = 33MHz
+Package: P = 60-Pin Plastic DIP
+ V = 68-Pin PLCC
+ F = 80-Pin QFP
+ Temp: S = 0C to +70C
+ E = -40C to +85C
+
+Environmental Flow: C = Plastic Standard
+
+
+Example from Ms.Pac-Man/Galaga - 20 year Reunion hardare (see src/mame/drivers/20pacgal.c):
+
+ CPU is Z8S18020VSC = Z180, 20MHz, 68-Pin PLCC, 0C to +70C, Plastic Standard
+
+
+Other CPUs that use a compatible Z180 core:
+
+Hitachi HD647180 series:
+ Available in QFP80, PLCC84 & DIP90 packages (the QFP80 is not pinout compatible)
+ The HD647180 also has an internal ROM
+
+ *****************************************************************************/
+
+#include "emu.h"
+#include "z180.h"
+#include "z180dasm.h"
+#include "debugger.h"
+
+//#define VERBOSE 1
+#include "logmacro.h"
+
+/* interrupt priorities */
+#define Z180_INT_TRAP 0 /* Undefined opcode */
+#define Z180_INT_NMI 1 /* NMI */
+#define Z180_INT_IRQ0 2 /* Execute IRQ1 */
+#define Z180_INT_IRQ1 3 /* Execute IRQ1 */
+#define Z180_INT_IRQ2 4 /* Execute IRQ2 */
+#define Z180_INT_PRT0 5 /* Internal PRT channel 0 */
+#define Z180_INT_PRT1 6 /* Internal PRT channel 1 */
+#define Z180_INT_DMA0 7 /* Internal DMA channel 0 */
+#define Z180_INT_DMA1 8 /* Internal DMA channel 1 */
+#define Z180_INT_CSIO 9 /* Internal CSI/O */
+#define Z180_INT_ASCI0 10 /* Internal ASCI channel 0 */
+#define Z180_INT_ASCI1 11 /* Internal ASCI channel 1 */
+#define Z180_INT_MAX Z180_INT_ASCI1
+
+/****************************************************************************/
+/* The Z180 registers. HALT is set to 1 when the CPU is halted, the refresh */
+/* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128) */
+/****************************************************************************/
+
+//DEFINE_DEVICE_TYPE(Z180, z180_device, "z180", "Zilog Z180")
+//
+//
+///*z180_device::*/z180_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+// : cpu_device(mconfig, Z180, tag, owner, clock)
+// , z80_daisy_chain_interface(mconfig, *this)
+// , m_program_config("program", ENDIANNESS_LITTLE, 8, 20, 0)
+// , m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0)
+// , m_decrypted_opcodes_config("program", ENDIANNESS_LITTLE, 8, 20, 0)
+//{
+//}
+//
+//std::unique_ptr<util::disasm_interface> /*z180_device::*/create_disassembler()
+//{
+// return std::make_unique<z180_disassembler>();
+//}
+
+#define CF 0x01
+#define NF 0x02
+#define PF 0x04
+#define VF PF
+#define XF 0x08
+#define HF 0x10
+#define YF 0x20
+#define ZF 0x40
+#define SF 0x80
+
+/* I/O line status flags */
+#define Z180_CKA0 0x00000001 /* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
+#define Z180_CKA1 0x00000002 /* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
+#define Z180_CKS 0x00000004 /* I/O serial clock (active high) */
+#define Z180_CTS0 0x00000100 /* I clear to send 0 (active low) */
+#define Z180_CTS1 0x00000200 /* I clear to send 1 (active low) or RXS (mux) */
+#define Z180_DCD0 0x00000400 /* I data carrier detect (active low) */
+#define Z180_DREQ0 0x00000800 /* I data request DMA ch 0 (active low) or CKA0 (mux) */
+#define Z180_DREQ1 0x00001000 /* I data request DMA ch 1 (active low) */
+#define Z180_RXA0 0x00002000 /* I asynchronous receive data 0 (active high) */
+#define Z180_RXA1 0x00004000 /* I asynchronous receive data 1 (active high) */
+#define Z180_RXS 0x00008000 /* I clocked serial receive data (active high) or CTS1 (mux) */
+#define Z180_RTS0 0x00010000 /* O request to send (active low) */
+#define Z180_TEND0 0x00020000 /* O transfer end 0 (active low) or CKA1 (mux) */
+#define Z180_TEND1 0x00040000 /* O transfer end 1 (active low) */
+#define Z180_A18_TOUT 0x00080000 /* O transfer out (PRT channel, active low) or A18 (mux) */
+#define Z180_TXA0 0x00100000 /* O asynchronous transmit data 0 (active high) */
+#define Z180_TXA1 0x00200000 /* O asynchronous transmit data 1 (active high) */
+#define Z180_TXS 0x00400000 /* O clocked serial transmit data (active high) */
+
+bool /*z180_device::*/get_tend0()
+{
+ return !!(m_iol & Z180_TEND0);
+}
+
+bool /*z180_device::*/get_tend1()
+{
+ return !!(m_iol & Z180_TEND1);
+}
+
+/*
+ * Prevent warnings on NetBSD. All identifiers beginning with an underscore
+ * followed by an uppercase letter are reserved by the C standard (ISO/IEC
+ * 9899:1999, 7.1.3) to be used by the implementation. It'd be best to rename
+ * all such instances, but this is less intrusive and error-prone.
+ */
+#undef _B
+#undef _C
+#undef _L
+
+#define _PPC m_PREPC.d /* previous program counter */
+
+#define _PCD m_PC.d
+#define _PC m_PC.w.l
+
+#define _SPD m_SP.d
+#define _SP m_SP.w.l
+
+#define _AFD m_AF.d
+#define _AF m_AF.w.l
+#define _A m_AF.b.h
+#define _F m_AF.b.l
+
+#define _BCD m_BC.d
+#define _BC m_BC.w.l
+#define _B m_BC.b.h
+#define _C m_BC.b.l
+
+#define _DED m_DE.d
+#define _DE m_DE.w.l
+#define _D m_DE.b.h
+#define _E m_DE.b.l
+
+#define _HLD m_HL.d
+#define _HL m_HL.w.l
+#define _H m_HL.b.h
+#define _L m_HL.b.l
+
+#define _IXD m_IX.d
+#define _IX m_IX.w.l
+#define _HX m_IX.b.h
+#define _LX m_IX.b.l
+
+#define _IYD m_IY.d
+#define _IY m_IY.w.l
+#define _HY m_IY.b.h
+#define _LY m_IY.b.l
+
+#define IO(n) m_io[(n)-Z180_CNTLA0]
+#define IO_CNTLA0 IO(Z180_CNTLA0)
+#define IO_CNTLA1 IO(Z180_CNTLA1)
+#define IO_CNTLB0 IO(Z180_CNTLB0)
+#define IO_CNTLB1 IO(Z180_CNTLB1)
+#define IO_STAT0 IO(Z180_STAT0)
+#define IO_STAT1 IO(Z180_STAT1)
+#define IO_TDR0 IO(Z180_TDR0)
+#define IO_TDR1 IO(Z180_TDR1)
+#define IO_RDR0 IO(Z180_RDR0)
+#define IO_RDR1 IO(Z180_RDR1)
+#define IO_CNTR IO(Z180_CNTR)
+#define IO_TRDR IO(Z180_TRDR)
+#define IO_TMDR0L IO(Z180_TMDR0L)
+#define IO_TMDR0H IO(Z180_TMDR0H)
+#define IO_RLDR0L IO(Z180_RLDR0L)
+#define IO_RLDR0H IO(Z180_RLDR0H)
+#define IO_TCR IO(Z180_TCR)
+#define IO_IO11 IO(Z180_IO11)
+#define IO_ASEXT0 IO(Z180_ASEXT0)
+#define IO_ASEXT1 IO(Z180_ASEXT1)
+#define IO_TMDR1L IO(Z180_TMDR1L)
+#define IO_TMDR1H IO(Z180_TMDR1H)
+#define IO_RLDR1L IO(Z180_RLDR1L)
+#define IO_RLDR1H IO(Z180_RLDR1H)
+#define IO_FRC IO(Z180_FRC)
+#define IO_IO19 IO(Z180_IO19)
+#define IO_ASTC0L IO(Z180_ASTC0L)
+#define IO_ASTC0H IO(Z180_ASTC0H)
+#define IO_ASTC1L IO(Z180_ASTC1L)
+#define IO_ASTC1H IO(Z180_ASTC1H)
+#define IO_CMR IO(Z180_CMR)
+#define IO_CCR IO(Z180_CCR)
+#define IO_SAR0L IO(Z180_SAR0L)
+#define IO_SAR0H IO(Z180_SAR0H)
+#define IO_SAR0B IO(Z180_SAR0B)
+#define IO_DAR0L IO(Z180_DAR0L)
+#define IO_DAR0H IO(Z180_DAR0H)
+#define IO_DAR0B IO(Z180_DAR0B)
+#define IO_BCR0L IO(Z180_BCR0L)
+#define IO_BCR0H IO(Z180_BCR0H)
+#define IO_MAR1L IO(Z180_MAR1L)
+#define IO_MAR1H IO(Z180_MAR1H)
+#define IO_MAR1B IO(Z180_MAR1B)
+#define IO_IAR1L IO(Z180_IAR1L)
+#define IO_IAR1H IO(Z180_IAR1H)
+#define IO_IAR1B IO(Z180_IAR1B)
+#define IO_BCR1L IO(Z180_BCR1L)
+#define IO_BCR1H IO(Z180_BCR1H)
+#define IO_DSTAT IO(Z180_DSTAT)
+#define IO_DMODE IO(Z180_DMODE)
+#define IO_DCNTL IO(Z180_DCNTL)
+#define IO_IL IO(Z180_IL)
+#define IO_ITC IO(Z180_ITC)
+#define IO_IO35 IO(Z180_IO35)
+#define IO_RCR IO(Z180_RCR)
+#define IO_IO37 IO(Z180_IO37)
+#define IO_CBR IO(Z180_CBR)
+#define IO_BBR IO(Z180_BBR)
+#define IO_CBAR IO(Z180_CBAR)
+#define IO_IO3B IO(Z180_IO3B)
+#define IO_IO3C IO(Z180_IO3C)
+#define IO_IO3D IO(Z180_IO3D)
+#define IO_OMCR IO(Z180_OMCR)
+#define IO_IOCR IO(Z180_IOCR)
+
+/* 00 ASCI control register A ch 0 */
+#define Z180_CNTLA0_MPE 0x80
+#define Z180_CNTLA0_RE 0x40
+#define Z180_CNTLA0_TE 0x20
+#define Z180_CNTLA0_RTS0 0x10
+#define Z180_CNTLA0_MPBR_EFR 0x08
+#define Z180_CNTLA0_MODE_DATA 0x04
+#define Z180_CNTLA0_MODE_PARITY 0x02
+#define Z180_CNTLA0_MODE_STOPB 0x01
+
+#define Z180_CNTLA0_RESET 0x10
+#define Z180_CNTLA0_RMASK 0xff
+#define Z180_CNTLA0_WMASK 0xff
+
+/* 01 ASCI control register A ch 1 */
+#define Z180_CNTLA1_MPE 0x80
+#define Z180_CNTLA1_RE 0x40
+#define Z180_CNTLA1_TE 0x20
+#define Z180_CNTLA1_CKA1D 0x10
+#define Z180_CNTLA1_MPBR_EFR 0x08
+#define Z180_CNTLA1_MODE 0x07
+
+#define Z180_CNTLA1_RESET 0x10
+#define Z180_CNTLA1_RMASK 0xff
+#define Z180_CNTLA1_WMASK 0xff
+
+/* 02 ASCI control register B ch 0 */
+#define Z180_CNTLB0_MPBT 0x80
+#define Z180_CNTLB0_MP 0x40
+#define Z180_CNTLB0_CTS_PS 0x20
+#define Z180_CNTLB0_PEO 0x10
+#define Z180_CNTLB0_DR 0x08
+#define Z180_CNTLB0_SS 0x07
+
+#define Z180_CNTLB0_RESET 0x07
+#define Z180_CNTLB0_RMASK 0xff
+#define Z180_CNTLB0_WMASK 0xff
+
+/* 03 ASCI control register B ch 1 */
+#define Z180_CNTLB1_MPBT 0x80
+#define Z180_CNTLB1_MP 0x40
+#define Z180_CNTLB1_CTS_PS 0x20
+#define Z180_CNTLB1_PEO 0x10
+#define Z180_CNTLB1_DR 0x08
+#define Z180_CNTLB1_SS 0x07
+
+#define Z180_CNTLB1_RESET 0x07
+#define Z180_CNTLB1_RMASK 0xff
+#define Z180_CNTLB1_WMASK 0xff
+
+/* 04 ASCI status register 0 */
+#define Z180_STAT0_RDRF 0x80
+#define Z180_STAT0_OVRN 0x40
+#define Z180_STAT0_PE 0x20
+#define Z180_STAT0_FE 0x10
+#define Z180_STAT0_RIE 0x08
+#define Z180_STAT0_DCD0 0x04
+#define Z180_STAT0_TDRE 0x02
+#define Z180_STAT0_TIE 0x01
+
+#define Z180_STAT0_RESET 0x00
+#define Z180_STAT0_RMASK 0xff
+#define Z180_STAT0_WMASK 0x09
+
+/* 05 ASCI status register 1 */
+#define Z180_STAT1_RDRF 0x80
+#define Z180_STAT1_OVRN 0x40
+#define Z180_STAT1_PE 0x20
+#define Z180_STAT1_FE 0x10
+#define Z180_STAT1_RIE 0x08
+#define Z180_STAT1_CTS1E 0x04
+#define Z180_STAT1_TDRE 0x02
+#define Z180_STAT1_TIE 0x01
+
+#define Z180_STAT1_RESET 0x02
+#define Z180_STAT1_RMASK 0xff
+#define Z180_STAT1_WMASK 0x0d
+
+/* 06 ASCI transmit data register 0 */
+#define Z180_TDR0_TDR 0xff
+
+#define Z180_TDR0_RESET 0x00
+#define Z180_TDR0_RMASK 0xff
+#define Z180_TDR0_WMASK 0xff
+
+/* 07 ASCI transmit data register 1 */
+#define Z180_TDR1_TDR 0xff
+
+#define Z180_TDR1_RESET 0x00
+#define Z180_TDR1_RMASK 0xff
+#define Z180_TDR1_WMASK 0xff
+
+/* 08 ASCI receive register 0 */
+#define Z180_RDR0_RDR 0xff
+
+#define Z180_RDR0_RESET 0x00
+#define Z180_RDR0_RMASK 0xff
+#define Z180_RDR0_WMASK 0xff
+
+/* 09 ASCI receive register 1 */
+#define Z180_RDR1_RDR 0xff
+
+#define Z180_RDR1_RESET 0x00
+#define Z180_RDR1_RMASK 0xff
+#define Z180_RDR1_WMASK 0xff
+
+/* 0a CSI/O control/status register */
+#define Z180_CNTR_EF 0x80
+#define Z180_CNTR_EIE 0x40
+#define Z180_CNTR_RE 0x20
+#define Z180_CNTR_TE 0x10
+#define Z180_CNTR_SS 0x07
+
+#define Z180_CNTR_RESET 0x07
+#define Z180_CNTR_RMASK 0xff
+#define Z180_CNTR_WMASK 0x4f /* Original: 0x7f - Modified: 0x4f - Inhibits setting up TI & RI flags due to the lack of CSIO implementation */
+
+/* 0b CSI/O transmit/receive register */
+#define Z180_TRDR_RESET 0x00
+#define Z180_TRDR_RMASK 0xff
+#define Z180_TRDR_WMASK 0xff
+
+/* 0c TIMER data register ch 0 L */
+#define Z180_TMDR0L_RESET 0x00
+#define Z180_TMDR0L_RMASK 0xff
+#define Z180_TMDR0L_WMASK 0xff
+
+/* 0d TIMER data register ch 0 H */
+#define Z180_TMDR0H_RESET 0x00
+#define Z180_TMDR0H_RMASK 0xff
+#define Z180_TMDR0H_WMASK 0xff
+
+/* 0e TIMER reload register ch 0 L */
+#define Z180_RLDR0L_RESET 0xff
+#define Z180_RLDR0L_RMASK 0xff
+#define Z180_RLDR0L_WMASK 0xff
+
+/* 0f TIMER reload register ch 0 H */
+#define Z180_RLDR0H_RESET 0xff
+#define Z180_RLDR0H_RMASK 0xff
+#define Z180_RLDR0H_WMASK 0xff
+
+/* 10 TIMER control register */
+#define Z180_TCR_TIF1 0x80
+#define Z180_TCR_TIF0 0x40
+#define Z180_TCR_TIE1 0x20
+#define Z180_TCR_TIE0 0x10
+#define Z180_TCR_TOC1 0x08
+#define Z180_TCR_TOC0 0x04
+#define Z180_TCR_TDE1 0x02
+#define Z180_TCR_TDE0 0x01
+
+#define Z180_TCR_RESET 0x00
+#define Z180_TCR_RMASK 0xff
+#define Z180_TCR_WMASK 0x3f
+
+/* 11 reserved */
+#define Z180_IO11_RESET 0x00
+#define Z180_IO11_RMASK 0xff
+#define Z180_IO11_WMASK 0xff
+
+/* 12 (Z8S180/Z8L180) ASCI extension control register 0 */
+#define Z180_ASEXT0_RDRF 0x80
+#define Z180_ASEXT0_DCD0 0x40
+#define Z180_ASEXT0_CTS0 0x20
+#define Z180_ASEXT0_X1_BIT_CLK0 0x10
+#define Z180_ASEXT0_BRG0_MODE 0x08
+#define Z180_ASEXT0_BRK_EN 0x04
+#define Z180_ASEXT0_BRK_DET 0x02
+#define Z180_ASEXT0_BRK_SEND 0x01
+
+#define Z180_ASEXT0_RESET 0x00
+#define Z180_ASEXT0_RMASK 0xff
+#define Z180_ASEXT0_WMASK 0xfd
+
+/* 13 (Z8S180/Z8L180) ASCI extension control register 0 */
+#define Z180_ASEXT1_RDRF 0x80
+#define Z180_ASEXT1_X1_BIT_CLK1 0x10
+#define Z180_ASEXT1_BRG1_MODE 0x08
+#define Z180_ASEXT1_BRK_EN 0x04
+#define Z180_ASEXT1_BRK_DET 0x02
+#define Z180_ASEXT1_BRK_SEND 0x01
+
+#define Z180_ASEXT1_RESET 0x00
+#define Z180_ASEXT1_RMASK 0xff
+#define Z180_ASEXT1_WMASK 0xfd
+
+
+/* 14 TIMER data register ch 1 L */
+#define Z180_TMDR1L_RESET 0x00
+#define Z180_TMDR1L_RMASK 0xff
+#define Z180_TMDR1L_WMASK 0xff
+
+/* 15 TIMER data register ch 1 H */
+#define Z180_TMDR1H_RESET 0x00
+#define Z180_TMDR1H_RMASK 0xff
+#define Z180_TMDR1H_WMASK 0xff
+
+/* 16 TIMER reload register ch 1 L */
+#define Z180_RLDR1L_RESET 0x00
+#define Z180_RLDR1L_RMASK 0xff
+#define Z180_RLDR1L_WMASK 0xff
+
+/* 17 TIMER reload register ch 1 H */
+#define Z180_RLDR1H_RESET 0x00
+#define Z180_RLDR1H_RMASK 0xff
+#define Z180_RLDR1H_WMASK 0xff
+
+/* 18 free running counter */
+#define Z180_FRC_RESET 0x00
+#define Z180_FRC_RMASK 0xff
+#define Z180_FRC_WMASK 0xff
+
+/* 19 reserved */
+#define Z180_IO19_RESET 0x00
+#define Z180_IO19_RMASK 0xff
+#define Z180_IO19_WMASK 0xff
+
+/* 1a ASCI time constant ch 0 L */
+#define Z180_ASTC0L_RESET 0x00
+#define Z180_ASTC0L_RMASK 0xff
+#define Z180_ASTC0L_WMASK 0xff
+
+/* 1b ASCI time constant ch 0 H */
+#define Z180_ASTC0H_RESET 0x00
+#define Z180_ASTC0H_RMASK 0xff
+#define Z180_ASTC0H_WMASK 0xff
+
+/* 1c ASCI time constant ch 1 L */
+#define Z180_ASTC1L_RESET 0x00
+#define Z180_ASTC1L_RMASK 0xff
+#define Z180_ASTC1L_WMASK 0xff
+
+/* 1d ASCI time constant ch 1 H */
+#define Z180_ASTC1H_RESET 0x00
+#define Z180_ASTC1H_RMASK 0xff
+#define Z180_ASTC1H_WMASK 0xff
+
+/* 1e clock multiplier */
+#define Z180_CMR_X2 0x80
+
+#define Z180_CMR_RESET 0x7f
+#define Z180_CMR_RMASK 0x80
+#define Z180_CMR_WMASK 0x80
+
+/* 1f chip control register */
+#define Z180_CCR_CLOCK_DIVIDE 0x80
+#define Z180_CCR_STDBY_IDLE1 0x40
+#define Z180_CCR_BREXT 0x20
+#define Z180_CCR_LNPHI 0x10
+#define Z180_CCR_STDBY_IDLE0 0x08
+#define Z180_CCR_LNIO 0x04
+#define Z180_CCR_LNCPU_CTL 0x02
+#define Z180_CCR_LNAD_DATA 0x01
+
+#define Z180_CCR_RESET 0x00
+#define Z180_CCR_RMASK 0xff
+#define Z180_CCR_WMASK 0xff
+
+/* 20 DMA source address register ch 0 L */
+#define Z180_SAR0L_SAR 0xff
+
+#define Z180_SAR0L_RESET 0x00
+#define Z180_SAR0L_RMASK 0xff
+#define Z180_SAR0L_WMASK 0xff
+
+/* 21 DMA source address register ch 0 H */
+#define Z180_SAR0H_SAR 0xff
+
+#define Z180_SAR0H_RESET 0x00
+#define Z180_SAR0H_RMASK 0xff
+#define Z180_SAR0H_WMASK 0xff
+
+/* 22 DMA source address register ch 0 B */
+#define Z180_SAR0B_SAR 0x0f
+
+#define Z180_SAR0B_RESET 0x00
+#define Z180_SAR0B_RMASK 0x0f
+#define Z180_SAR0B_WMASK 0x0f
+
+/* 23 DMA destination address register ch 0 L */
+#define Z180_DAR0L_DAR 0xff
+
+#define Z180_DAR0L_RESET 0x00
+#define Z180_DAR0L_RMASK 0xff
+#define Z180_DAR0L_WMASK 0xff
+
+/* 24 DMA destination address register ch 0 H */
+#define Z180_DAR0H_DAR 0xff
+
+#define Z180_DAR0H_RESET 0x00
+#define Z180_DAR0H_RMASK 0xff
+#define Z180_DAR0H_WMASK 0xff
+
+/* 25 DMA destination address register ch 0 B */
+#define Z180_DAR0B_DAR 0x00
+
+#define Z180_DAR0B_RESET 0x00
+#define Z180_DAR0B_RMASK 0x0f
+#define Z180_DAR0B_WMASK 0x0f
+
+/* 26 DMA byte count register ch 0 L */
+#define Z180_BCR0L_BCR 0xff
+
+#define Z180_BCR0L_RESET 0x00
+#define Z180_BCR0L_RMASK 0xff
+#define Z180_BCR0L_WMASK 0xff
+
+/* 27 DMA byte count register ch 0 H */
+#define Z180_BCR0H_BCR 0xff
+
+#define Z180_BCR0H_RESET 0x00
+#define Z180_BCR0H_RMASK 0xff
+#define Z180_BCR0H_WMASK 0xff
+
+/* 28 DMA memory address register ch 1 L */
+#define Z180_MAR1L_MAR 0xff
+
+#define Z180_MAR1L_RESET 0x00
+#define Z180_MAR1L_RMASK 0xff
+#define Z180_MAR1L_WMASK 0xff
+
+/* 29 DMA memory address register ch 1 H */
+#define Z180_MAR1H_MAR 0xff
+
+#define Z180_MAR1H_RESET 0x00
+#define Z180_MAR1H_RMASK 0xff
+#define Z180_MAR1H_WMASK 0xff
+
+/* 2a DMA memory address register ch 1 B */
+#define Z180_MAR1B_MAR 0x0f
+
+#define Z180_MAR1B_RESET 0x00
+#define Z180_MAR1B_RMASK 0x0f
+#define Z180_MAR1B_WMASK 0x0f
+
+/* 2b DMA I/O address register ch 1 L */
+#define Z180_IAR1L_IAR 0xff
+
+#define Z180_IAR1L_RESET 0x00
+#define Z180_IAR1L_RMASK 0xff
+#define Z180_IAR1L_WMASK 0xff
+
+/* 2c DMA I/O address register ch 1 H */
+#define Z180_IAR1H_IAR 0xff
+
+#define Z180_IAR1H_RESET 0x00
+#define Z180_IAR1H_RMASK 0xff
+#define Z180_IAR1H_WMASK 0xff
+
+/* 2d (Z8S180/Z8L180) DMA I/O address register ch 1 B */
+#define Z180_IAR1B_IAR 0x0f
+
+#define Z180_IAR1B_RESET 0x00
+#define Z180_IAR1B_RMASK 0x0f
+#define Z180_IAR1B_WMASK 0x0f
+
+/* 2e DMA byte count register ch 1 L */
+#define Z180_BCR1L_BCR 0xff
+
+#define Z180_BCR1L_RESET 0x00
+#define Z180_BCR1L_RMASK 0xff
+#define Z180_BCR1L_WMASK 0xff
+
+/* 2f DMA byte count register ch 1 H */
+#define Z180_BCR1H_BCR 0xff
+
+#define Z180_BCR1H_RESET 0x00
+#define Z180_BCR1H_RMASK 0xff
+#define Z180_BCR1H_WMASK 0xff
+
+/* 30 DMA status register */
+#define Z180_DSTAT_DE1 0x80 /* DMA enable ch 1 */
+#define Z180_DSTAT_DE0 0x40 /* DMA enable ch 0 */
+#define Z180_DSTAT_DWE1 0x20 /* DMA write enable ch 0 (active low) */
+#define Z180_DSTAT_DWE0 0x10 /* DMA write enable ch 1 (active low) */
+#define Z180_DSTAT_DIE1 0x08 /* DMA IRQ enable ch 1 */
+#define Z180_DSTAT_DIE0 0x04 /* DMA IRQ enable ch 0 */
+#define Z180_DSTAT_DME 0x01 /* DMA enable (read only) */
+
+#define Z180_DSTAT_RESET 0x30
+#define Z180_DSTAT_RMASK 0xfd
+#define Z180_DSTAT_WMASK 0xcc
+
+/* 31 DMA mode register */
+#define Z180_DMODE_DM 0x30 /* DMA ch 0 destination addressing mode */
+#define Z180_DMODE_SM 0x0c /* DMA ch 0 source addressing mode */
+#define Z180_DMODE_MMOD 0x02 /* DMA cycle steal/burst mode select */
+
+#define Z180_DMODE_RESET 0x00
+#define Z180_DMODE_RMASK 0x3e
+#define Z180_DMODE_WMASK 0x3e
+
+/* 32 DMA/WAIT control register */
+#define Z180_DCNTL_MWI1 0x80
+#define Z180_DCNTL_MWI0 0x40
+#define Z180_DCNTL_IWI1 0x20
+#define Z180_DCNTL_IWI0 0x10
+#define Z180_DCNTL_DMS1 0x08
+#define Z180_DCNTL_DMS0 0x04
+#define Z180_DCNTL_DIM1 0x02
+#define Z180_DCNTL_DIM0 0x01
+
+#define Z180_DCNTL_RESET 0x00
+#define Z180_DCNTL_RMASK 0xff
+#define Z180_DCNTL_WMASK 0xff
+
+/* 33 INT vector low register */
+#define Z180_IL_IL 0xe0
+
+#define Z180_IL_RESET 0x00
+#define Z180_IL_RMASK 0xe0
+#define Z180_IL_WMASK 0xe0
+
+/* 34 INT/TRAP control register */
+#define Z180_ITC_TRAP 0x80
+#define Z180_ITC_UFO 0x40
+#define Z180_ITC_ITE2 0x04
+#define Z180_ITC_ITE1 0x02
+#define Z180_ITC_ITE0 0x01
+
+#define Z180_ITC_RESET 0x01
+#define Z180_ITC_RMASK 0xc7
+#define Z180_ITC_WMASK 0x87
+
+/* 35 reserved */
+#define Z180_IO35_RESET 0x00
+#define Z180_IO35_RMASK 0xff
+#define Z180_IO35_WMASK 0xff
+
+/* 36 refresh control register */
+#define Z180_RCR_REFE 0x80
+#define Z180_RCR_REFW 0x40
+#define Z180_RCR_CYC 0x03
+
+#define Z180_RCR_RESET 0xc0
+#define Z180_RCR_RMASK 0xc3
+#define Z180_RCR_WMASK 0xc3
+
+/* 37 reserved */
+#define Z180_IO37_RESET 0x00
+#define Z180_IO37_RMASK 0xff
+#define Z180_IO37_WMASK 0xff
+
+/* 38 MMU common base register */
+#define Z180_CBR_CB 0xff
+
+#define Z180_CBR_RESET 0x00
+#define Z180_CBR_RMASK 0xff
+#define Z180_CBR_WMASK 0xff
+
+/* 39 MMU bank base register */
+#define Z180_BBR_BB 0xff
+
+#define Z180_BBR_RESET 0x00
+#define Z180_BBR_RMASK 0xff
+#define Z180_BBR_WMASK 0xff
+
+/* 3a MMU common/bank area register */
+#define Z180_CBAR_CA 0xf0
+#define Z180_CBAR_BA 0x0f
+
+#define Z180_CBAR_RESET 0xf0
+#define Z180_CBAR_RMASK 0xff
+#define Z180_CBAR_WMASK 0xff
+
+/* 3b reserved */
+#define Z180_IO3B_RESET 0x00
+#define Z180_IO3B_RMASK 0xff
+#define Z180_IO3B_WMASK 0xff
+
+/* 3c reserved */
+#define Z180_IO3C_RESET 0x00
+#define Z180_IO3C_RMASK 0xff
+#define Z180_IO3C_WMASK 0xff
+
+/* 3d reserved */
+#define Z180_IO3D_RESET 0x00
+#define Z180_IO3D_RMASK 0xff
+#define Z180_IO3D_WMASK 0xff
+
+/* 3e operation mode control register */
+#define Z180_OMCR_RESET 0x00
+#define Z180_OMCR_RMASK 0xff
+#define Z180_OMCR_WMASK 0xff
+
+/* 3f I/O control register */
+#define Z180_IOCR_RESET 0x00
+#define Z180_IOCR_RMASK 0xff
+#define Z180_IOCR_WMASK 0xff
+
+/***************************************************************************
+ CPU PREFIXES
+
+ order is important here - see z180tbl.h
+***************************************************************************/
+
+#define Z180_PREFIX_op 0
+#define Z180_PREFIX_cb 1
+#define Z180_PREFIX_dd 2
+#define Z180_PREFIX_ed 3
+#define Z180_PREFIX_fd 4
+#define Z180_PREFIX_xycb 5
+
+#define Z180_PREFIX_COUNT (Z180_PREFIX_xycb + 1)
+
+
+
+static uint8_t SZ[256]; /* zero and sign flags */
+static uint8_t SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
+static uint8_t SZP[256]; /* zero, sign and parity flags */
+static uint8_t SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
+static uint8_t SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
+
+static uint8_t *SZHVC_add; //std::unique_ptr<uint8_t[]> SZHVC_add;
+static uint8_t *SZHVC_sub; //std::unique_ptr<uint8_t[]> SZHVC_sub;
+
+#include "z180ops.inc"
+#include "z180tbl.inc"
+
+#include "z180cb.inc"
+#include "z180xy.inc"
+#include "z180dd.inc"
+#include "z180fd.inc"
+#include "z180ed.inc"
+#include "z180op.inc"
+
+
+///*device_memory_interface::*/space_config_vector /*z180_device::*/memory_space_config() const
+//{
+// if(has_configured_map(AS_OPCODES))
+// return space_config_vector {
+// std::make_pair(AS_PROGRAM, &m_program_config),
+// std::make_pair(AS_OPCODES, &m_decrypted_opcodes_config),
+// std::make_pair(AS_IO, &m_io_config)
+// };
+// else
+// return space_config_vector {
+// std::make_pair(AS_PROGRAM, &m_program_config),
+// std::make_pair(AS_IO, &m_io_config)
+// };
+//}
+
+uint8_t /*z180_device::*/z180_readcontrol(offs_t port)
+{
+ /* normal external readport */
+ uint8_t data = m_iospace_read_byte(port);
+
+ /* remap internal I/O registers */
+ if((port & (IO_IOCR & 0xc0)) == (IO_IOCR & 0xc0))
+ port = port - (IO_IOCR & 0xc0);
+
+ /* but ignore the data and read the internal register */
+ switch (port + Z180_CNTLA0)
+ {
+ case Z180_CNTLA0:
+ data = IO_CNTLA0 & Z180_CNTLA0_RMASK;
+ LOG("Z180 CNTLA0 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_CNTLA1:
+ data = IO_CNTLA1 & Z180_CNTLA1_RMASK;
+ LOG("Z180 CNTLA1 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_CNTLB0:
+ data = IO_CNTLB0 & Z180_CNTLB0_RMASK;
+ LOG("Z180 CNTLB0 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_CNTLB1:
+ data = IO_CNTLB1 & Z180_CNTLB1_RMASK;
+ LOG("Z180 CNTLB1 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_STAT0:
+ data = IO_STAT0 & Z180_STAT0_RMASK;
+ data |= 0x02; // kludge for 20pacgal
+ LOG("Z180 STAT0 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_STAT1:
+ data = IO_STAT1 & Z180_STAT1_RMASK;
+ LOG("Z180 STAT1 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_TDR0:
+ data = IO_TDR0 & Z180_TDR0_RMASK;
+ LOG("Z180 TDR0 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_TDR1:
+ data = IO_TDR1 & Z180_TDR1_RMASK;
+ LOG("Z180 TDR1 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_RDR0:
+ data = IO_RDR0 & Z180_RDR0_RMASK;
+ LOG("Z180 RDR0 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_RDR1:
+ data = IO_RDR1 & Z180_RDR1_RMASK;
+ LOG("Z180 RDR1 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_CNTR:
+ data = IO_CNTR & Z180_CNTR_RMASK;
+ LOG("Z180 CNTR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_TRDR:
+ data = IO_TRDR & Z180_TRDR_RMASK;
+ logerror("Z180 TRDR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_TMDR0L:
+ data = m_tmdr_value[0] & Z180_TMDR0L_RMASK;
+ LOG("Z180 TMDR0L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ /* if timer is counting, latch the MSB and set the latch flag */
+ if ((IO_TCR & Z180_TCR_TDE0) == 0)
+ {
+ m_tmdr_latch |= 1;
+ m_tmdrh[0] = (m_tmdr_value[0] & 0xff00) >> 8;
+ }
+
+ if(m_read_tcr_tmdr[0])
+ {
+ m_tif[0] = 0; // reset TIF0
+ m_read_tcr_tmdr[0] = 0;
+ }
+ else
+ {
+ m_read_tcr_tmdr[0] = 1;
+ }
+ break;
+
+ case Z180_TMDR0H:
+ /* read latched value? */
+ if (m_tmdr_latch & 1)
+ {
+ m_tmdr_latch &= ~1;
+ data = m_tmdrh[0];
+ }
+ else
+ {
+ data = (m_tmdr_value[0] & 0xff00) >> 8;
+ }
+
+ if(m_read_tcr_tmdr[0])
+ {
+ m_tif[0] = 0; // reset TIF0
+ m_read_tcr_tmdr[0] = 0;
+ }
+ else
+ {
+ m_read_tcr_tmdr[0] = 1;
+ }
+ LOG("Z180 TMDR0H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_RLDR0L:
+ data = IO_RLDR0L & Z180_RLDR0L_RMASK;
+ LOG("Z180 RLDR0L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_RLDR0H:
+ data = IO_RLDR0H & Z180_RLDR0H_RMASK;
+ LOG("Z180 RLDR0H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_TCR:
+ data = (IO_TCR & Z180_TCR_RMASK) | (m_tif[0] << 6) | (m_tif[1] << 7);
+
+ if(m_read_tcr_tmdr[0])
+ {
+ m_tif[0] = 0; // reset TIF0
+ m_read_tcr_tmdr[0] = 0;
+ }
+ else
+ {
+ m_read_tcr_tmdr[0] = 1;
+ }
+
+ if(m_read_tcr_tmdr[1])
+ {
+ m_tif[1] = 0; // reset TIF1
+ m_read_tcr_tmdr[1] = 0;
+ }
+ else
+ {
+ m_read_tcr_tmdr[1] = 1;
+ }
+
+ LOG("Z180 TCR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IO11:
+ data = IO_IO11 & Z180_IO11_RMASK;
+ LOG("Z180 IO11 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_ASEXT0:
+ data = IO_ASEXT0 & Z180_ASEXT0_RMASK;
+ LOG("Z180 ASEXT0 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_ASEXT1:
+ data = IO_ASEXT1 & Z180_ASEXT1_RMASK;
+ LOG("Z180 ASEXT1 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_TMDR1L:
+ data = m_tmdr_value[1] & Z180_TMDR1L_RMASK;
+ LOG("Z180 TMDR1L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ /* if timer is counting, latch the MSB and set the latch flag */
+ if ((IO_TCR & Z180_TCR_TDE1) == 0)
+ {
+ m_tmdr_latch |= 2;
+ m_tmdrh[1] = (m_tmdr_value[1] & 0xff00) >> 8;
+ }
+
+ if(m_read_tcr_tmdr[1])
+ {
+ m_tif[1] = 0; // reset TIF1
+ m_read_tcr_tmdr[1] = 0;
+ }
+ else
+ {
+ m_read_tcr_tmdr[1] = 1;
+ }
+ break;
+
+ case Z180_TMDR1H:
+ /* read latched value? */
+ if (m_tmdr_latch & 2)
+ {
+ m_tmdr_latch &= ~2;
+ data = m_tmdrh[1];
+ }
+ else
+ {
+ data = (m_tmdr_value[1] & 0xff00) >> 8;
+ }
+
+ if(m_read_tcr_tmdr[1])
+ {
+ m_tif[1] = 0; // reset TIF1
+ m_read_tcr_tmdr[1] = 0;
+ }
+ else
+ {
+ m_read_tcr_tmdr[1] = 1;
+ }
+ LOG("Z180 TMDR1H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_RLDR1L:
+ data = IO_RLDR1L & Z180_RLDR1L_RMASK;
+ LOG("Z180 RLDR1L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_RLDR1H:
+ data = IO_RLDR1H & Z180_RLDR1H_RMASK;
+ LOG("Z180 RLDR1H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_FRC:
+ data = IO_FRC & Z180_FRC_RMASK;
+ LOG("Z180 FRC rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IO19:
+ data = IO_IO19 & Z180_IO19_RMASK;
+ LOG("Z180 IO19 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_ASTC0L:
+ data = IO_ASTC0L & Z180_ASTC0L_RMASK;
+ LOG("Z180 ASTC0L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_ASTC0H:
+ data = IO_ASTC0H & Z180_ASTC0H_RMASK;
+ LOG("Z180 ASTC0H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_ASTC1L:
+ data = IO_ASTC1L & Z180_ASTC1L_RMASK;
+ LOG("Z180 ASTC1L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_ASTC1H:
+ data = IO_ASTC1H & Z180_ASTC1H_RMASK;
+ LOG("Z180 ASTC1H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_CMR:
+ data = IO_CMR & Z180_CMR_RMASK;
+ LOG("Z180 CMR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_CCR:
+ data = IO_CCR & Z180_CCR_RMASK;
+ LOG("Z180 CCR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_SAR0L:
+ data = IO_SAR0L & Z180_SAR0L_RMASK;
+ LOG("Z180 SAR0L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_SAR0H:
+ data = IO_SAR0H & Z180_SAR0H_RMASK;
+ LOG("Z180 SAR0H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_SAR0B:
+ data = IO_SAR0B & Z180_SAR0B_RMASK;
+ LOG("Z180 SAR0B rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_DAR0L:
+ data = IO_DAR0L & Z180_DAR0L_RMASK;
+ LOG("Z180 DAR0L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_DAR0H:
+ data = IO_DAR0H & Z180_DAR0H_RMASK;
+ LOG("Z180 DAR0H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_DAR0B:
+ data = IO_DAR0B & Z180_DAR0B_RMASK;
+ LOG("Z180 DAR0B rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_BCR0L:
+ data = IO_BCR0L & Z180_BCR0L_RMASK;
+ LOG("Z180 BCR0L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_BCR0H:
+ data = IO_BCR0H & Z180_BCR0H_RMASK;
+ LOG("Z180 BCR0H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_MAR1L:
+ data = IO_MAR1L & Z180_MAR1L_RMASK;
+ LOG("Z180 MAR1L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_MAR1H:
+ data = IO_MAR1H & Z180_MAR1H_RMASK;
+ LOG("Z180 MAR1H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_MAR1B:
+ data = IO_MAR1B & Z180_MAR1B_RMASK;
+ LOG("Z180 MAR1B rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IAR1L:
+ data = IO_IAR1L & Z180_IAR1L_RMASK;
+ LOG("Z180 IAR1L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IAR1H:
+ data = IO_IAR1H & Z180_IAR1H_RMASK;
+ LOG("Z180 IAR1H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IAR1B:
+ data = IO_IAR1B & Z180_IAR1B_RMASK;
+ LOG("Z180 IAR1B rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_BCR1L:
+ data = IO_BCR1L & Z180_BCR1L_RMASK;
+ LOG("Z180 BCR1L rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_BCR1H:
+ data = IO_BCR1H & Z180_BCR1H_RMASK;
+ LOG("Z180 BCR1H rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_DSTAT:
+ data = IO_DSTAT & Z180_DSTAT_RMASK;
+ LOG("Z180 DSTAT rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_DMODE:
+ data = IO_DMODE & Z180_DMODE_RMASK;
+ LOG("Z180 DMODE rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_DCNTL:
+ data = IO_DCNTL & Z180_DCNTL_RMASK;
+ LOG("Z180 DCNTL rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IL:
+ data = IO_IL & Z180_IL_RMASK;
+ LOG("Z180 IL rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_ITC:
+ data = IO_ITC & Z180_ITC_RMASK;
+ LOG("Z180 ITC rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IO35:
+ data = IO_IO35 & Z180_IO35_RMASK;
+ LOG("Z180 IO35 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_RCR:
+ data = IO_RCR & Z180_RCR_RMASK;
+ LOG("Z180 RCR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IO37:
+ data = IO_IO37 & Z180_IO37_RMASK;
+ LOG("Z180 IO37 rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_CBR:
+ data = IO_CBR & Z180_CBR_RMASK;
+ LOG("Z180 CBR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_BBR:
+ data = IO_BBR & Z180_BBR_RMASK;
+ LOG("Z180 BBR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_CBAR:
+ data = IO_CBAR & Z180_CBAR_RMASK;
+ LOG("Z180 CBAR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IO3B:
+ data = IO_IO3B & Z180_IO3B_RMASK;
+ LOG("Z180 IO3B rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IO3C:
+ data = IO_IO3C & Z180_IO3C_RMASK;
+ LOG("Z180 IO3C rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IO3D:
+ data = IO_IO3D & Z180_IO3D_RMASK;
+ LOG("Z180 IO3D rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_OMCR:
+ data = IO_OMCR & Z180_OMCR_RMASK;
+ LOG("Z180 OMCR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+
+ case Z180_IOCR:
+ data = IO_IOCR & Z180_IOCR_RMASK;
+ LOG("Z180 IOCR rd $%02x ($%02x)\n", data, m_io[port & 0x3f]);
+ break;
+ }
+
+ return data;
+}
+
+void /*z180_device::*/z180_writecontrol(offs_t port, uint8_t data)
+{
+ /* normal external write port */
+ m_iospace_write_byte(port, data);
+
+ /* remap internal I/O registers */
+ if((port & (IO_IOCR & 0xc0)) == (IO_IOCR & 0xc0))
+ port = port - (IO_IOCR & 0xc0);
+
+ /* store the data in the internal register */
+ switch (port + Z180_CNTLA0)
+ {
+ case Z180_CNTLA0:
+ LOG("Z180 CNTLA0 wr $%02x ($%02x)\n", data, data & Z180_CNTLA0_WMASK);
+ IO_CNTLA0 = (IO_CNTLA0 & ~Z180_CNTLA0_WMASK) | (data & Z180_CNTLA0_WMASK);
+ break;
+
+ case Z180_CNTLA1:
+ LOG("Z180 CNTLA1 wr $%02x ($%02x)\n", data, data & Z180_CNTLA1_WMASK);
+ IO_CNTLA1 = (IO_CNTLA1 & ~Z180_CNTLA1_WMASK) | (data & Z180_CNTLA1_WMASK);
+ break;
+
+ case Z180_CNTLB0:
+ LOG("Z180 CNTLB0 wr $%02x ($%02x)\n", data, data & Z180_CNTLB0_WMASK);
+ IO_CNTLB0 = (IO_CNTLB0 & ~Z180_CNTLB0_WMASK) | (data & Z180_CNTLB0_WMASK);
+ break;
+
+ case Z180_CNTLB1:
+ LOG("Z180 CNTLB1 wr $%02x ($%02x)\n", data, data & Z180_CNTLB1_WMASK);
+ IO_CNTLB1 = (IO_CNTLB1 & ~Z180_CNTLB1_WMASK) | (data & Z180_CNTLB1_WMASK);
+ break;
+
+ case Z180_STAT0:
+ LOG("Z180 STAT0 wr $%02x ($%02x)\n", data, data & Z180_STAT0_WMASK);
+ IO_STAT0 = (IO_STAT0 & ~Z180_STAT0_WMASK) | (data & Z180_STAT0_WMASK);
+ break;
+
+ case Z180_STAT1:
+ LOG("Z180 STAT1 wr $%02x ($%02x)\n", data, data & Z180_STAT1_WMASK);
+ IO_STAT1 = (IO_STAT1 & ~Z180_STAT1_WMASK) | (data & Z180_STAT1_WMASK);
+ break;
+
+ case Z180_TDR0:
+ LOG("Z180 TDR0 wr $%02x ($%02x)\n", data, data & Z180_TDR0_WMASK);
+ IO_TDR0 = (IO_TDR0 & ~Z180_TDR0_WMASK) | (data & Z180_TDR0_WMASK);
+ break;
+
+ case Z180_TDR1:
+ LOG("Z180 TDR1 wr $%02x ($%02x)\n", data, data & Z180_TDR1_WMASK);
+ IO_TDR1 = (IO_TDR1 & ~Z180_TDR1_WMASK) | (data & Z180_TDR1_WMASK);
+ break;
+
+ case Z180_RDR0:
+ LOG("Z180 RDR0 wr $%02x ($%02x)\n", data, data & Z180_RDR0_WMASK);
+ IO_RDR0 = (IO_RDR0 & ~Z180_RDR0_WMASK) | (data & Z180_RDR0_WMASK);
+ break;
+
+ case Z180_RDR1:
+ LOG("Z180 RDR1 wr $%02x ($%02x)\n", data, data & Z180_RDR1_WMASK);
+ IO_RDR1 = (IO_RDR1 & ~Z180_RDR1_WMASK) | (data & Z180_RDR1_WMASK);
+ break;
+
+ case Z180_CNTR:
+ LOG("Z180 CNTR wr $%02x ($%02x)\n", data, data & Z180_CNTR_WMASK);
+ IO_CNTR = (IO_CNTR & ~Z180_CNTR_WMASK) | (data & Z180_CNTR_WMASK);
+ break;
+
+ case Z180_TRDR:
+ LOG("Z180 TRDR wr $%02x ($%02x)\n", data, data & Z180_TRDR_WMASK);
+ IO_TRDR = (IO_TRDR & ~Z180_TRDR_WMASK) | (data & Z180_TRDR_WMASK);
+ break;
+
+ case Z180_TMDR0L:
+ LOG("Z180 TMDR0L wr $%02x ($%02x)\n", data, data & Z180_TMDR0L_WMASK);
+ IO_TMDR0L = data & Z180_TMDR0L_WMASK;
+ m_tmdr_value[0] = (m_tmdr_value[0] & 0xff00) | IO_TMDR0L;
+ break;
+
+ case Z180_TMDR0H:
+ LOG("Z180 TMDR0H wr $%02x ($%02x)\n", data, data & Z180_TMDR0H_WMASK);
+ IO_TMDR0H = data & Z180_TMDR0H_WMASK;
+ m_tmdr_value[0] = (m_tmdr_value[0] & 0x00ff) | (IO_TMDR0H << 8);
+ break;
+
+ case Z180_RLDR0L:
+ LOG("Z180 RLDR0L wr $%02x ($%02x)\n", data, data & Z180_RLDR0L_WMASK);
+ IO_RLDR0L = (IO_RLDR0L & ~Z180_RLDR0L_WMASK) | (data & Z180_RLDR0L_WMASK);
+ break;
+
+ case Z180_RLDR0H:
+ LOG("Z180 RLDR0H wr $%02x ($%02x)\n", data, data & Z180_RLDR0H_WMASK);
+ IO_RLDR0H = (IO_RLDR0H & ~Z180_RLDR0H_WMASK) | (data & Z180_RLDR0H_WMASK);
+ break;
+
+ case Z180_TCR:
+ LOG("Z180 TCR wr $%02x ($%02x)\n", data, data & Z180_TCR_WMASK);
+ {
+ uint16_t old = IO_TCR;
+ /* Force reload on state change */
+ IO_TCR = (IO_TCR & ~Z180_TCR_WMASK) | (data & Z180_TCR_WMASK);
+ if (!(old & Z180_TCR_TDE0) && (IO_TCR & Z180_TCR_TDE0))
+ m_tmdr_value[0] = 0; //IO_RLDR0L | (IO_RLDR0H << 8);
+ if (!(old & Z180_TCR_TDE1) && (IO_TCR & Z180_TCR_TDE1))
+ m_tmdr_value[1] = 0; //IO_RLDR1L | (IO_RLDR1H << 8);
+ }
+
+ break;
+
+ case Z180_IO11:
+ LOG("Z180 IO11 wr $%02x ($%02x)\n", data, data & Z180_IO11_WMASK);
+ IO_IO11 = (IO_IO11 & ~Z180_IO11_WMASK) | (data & Z180_IO11_WMASK);
+ break;
+
+ case Z180_ASEXT0:
+ LOG("Z180 ASEXT0 wr $%02x ($%02x)\n", data, data & Z180_ASEXT0_WMASK);
+ IO_ASEXT0 = (IO_ASEXT0 & ~Z180_ASEXT0_WMASK) | (data & Z180_ASEXT0_WMASK);
+ break;
+
+ case Z180_ASEXT1:
+ LOG("Z180 ASEXT1 wr $%02x ($%02x)\n", data, data & Z180_ASEXT1_WMASK);
+ IO_ASEXT1 = (IO_ASEXT1 & ~Z180_ASEXT1_WMASK) | (data & Z180_ASEXT1_WMASK);
+ break;
+
+ case Z180_TMDR1L:
+ LOG("Z180 TMDR1L wr $%02x ($%02x)\n", data, data & Z180_TMDR1L_WMASK);
+ IO_TMDR1L = data & Z180_TMDR1L_WMASK;
+ m_tmdr_value[1] = (m_tmdr_value[1] & 0xff00) | IO_TMDR1L;
+ break;
+
+ case Z180_TMDR1H:
+ LOG("Z180 TMDR1H wr $%02x ($%02x)\n", data, data & Z180_TMDR1H_WMASK);
+ IO_TMDR1H = data & Z180_TMDR1H_WMASK;
+ m_tmdr_value[1] = (m_tmdr_value[1] & 0x00ff) | IO_TMDR1H;
+ break;
+
+ case Z180_RLDR1L:
+ LOG("Z180 RLDR1L wr $%02x ($%02x)\n", data, data & Z180_RLDR1L_WMASK);
+ IO_RLDR1L = (IO_RLDR1L & ~Z180_RLDR1L_WMASK) | (data & Z180_RLDR1L_WMASK);
+ break;
+
+ case Z180_RLDR1H:
+ LOG("Z180 RLDR1H wr $%02x ($%02x)\n", data, data & Z180_RLDR1H_WMASK);
+ IO_RLDR1H = (IO_RLDR1H & ~Z180_RLDR1H_WMASK) | (data & Z180_RLDR1H_WMASK);
+ break;
+
+ case Z180_FRC:
+ LOG("Z180 FRC wr $%02x ($%02x)\n", data, data & Z180_FRC_WMASK);
+ IO_FRC = (IO_FRC & ~Z180_FRC_WMASK) | (data & Z180_FRC_WMASK);
+ break;
+
+ case Z180_IO19:
+ LOG("Z180 IO19 wr $%02x ($%02x)\n", data, data & Z180_IO19_WMASK);
+ IO_IO19 = (IO_IO19 & ~Z180_IO19_WMASK) | (data & Z180_IO19_WMASK);
+ break;
+
+ case Z180_ASTC0L:
+ LOG("Z180 ASTC0L wr $%02x ($%02x)\n", data, data & Z180_ASTC0L_WMASK);
+ IO_ASTC0L = (IO_ASTC0L & ~Z180_ASTC0L_WMASK) | (data & Z180_ASTC0L_WMASK);
+ break;
+
+ case Z180_ASTC0H:
+ LOG("Z180 ASTC0H wr $%02x ($%02x)\n", data, data & Z180_ASTC0H_WMASK);
+ IO_ASTC0H = (IO_ASTC0H & ~Z180_ASTC0H_WMASK) | (data & Z180_ASTC0H_WMASK);
+ break;
+
+ case Z180_ASTC1L:
+ LOG("Z180 ASTC1L wr $%02x ($%02x)\n", data, data & Z180_ASTC1L_WMASK);
+ IO_ASTC1L = (IO_ASTC1L & ~Z180_ASTC1L_WMASK) | (data & Z180_ASTC1L_WMASK);
+ break;
+
+ case Z180_ASTC1H:
+ LOG("Z180 ASTC1H wr $%02x ($%02x)\n", data, data & Z180_ASTC1H_WMASK);
+ IO_ASTC1H = (IO_ASTC1H & ~Z180_ASTC1H_WMASK) | (data & Z180_ASTC1H_WMASK);
+ break;
+
+ case Z180_CMR:
+ LOG("Z180 CMR wr $%02x ($%02x)\n", data, data & Z180_CMR_WMASK);
+ IO_CMR = (IO_CMR & ~Z180_CMR_WMASK) | (data & Z180_CMR_WMASK);
+ break;
+
+ case Z180_CCR:
+ LOG("Z180 CCR wr $%02x ($%02x)\n", data, data & Z180_CCR_WMASK);
+ IO_CCR = (IO_CCR & ~Z180_CCR_WMASK) | (data & Z180_CCR_WMASK);
+ break;
+
+ case Z180_SAR0L:
+ LOG("Z180 SAR0L wr $%02x ($%02x)\n", data, data & Z180_SAR0L_WMASK);
+ IO_SAR0L = (IO_SAR0L & ~Z180_SAR0L_WMASK) | (data & Z180_SAR0L_WMASK);
+ break;
+
+ case Z180_SAR0H:
+ LOG("Z180 SAR0H wr $%02x ($%02x)\n", data, data & Z180_SAR0H_WMASK);
+ IO_SAR0H = (IO_SAR0H & ~Z180_SAR0H_WMASK) | (data & Z180_SAR0H_WMASK);
+ break;
+
+ case Z180_SAR0B:
+ LOG("Z180 SAR0B wr $%02x ($%02x)\n", data, data & Z180_SAR0B_WMASK);
+ IO_SAR0B = (IO_SAR0B & ~Z180_SAR0B_WMASK) | (data & Z180_SAR0B_WMASK);
+ break;
+
+ case Z180_DAR0L:
+ LOG("Z180 DAR0L wr $%02x ($%02x)\n", data, data & Z180_DAR0L_WMASK);
+ IO_DAR0L = (IO_DAR0L & ~Z180_DAR0L_WMASK) | (data & Z180_DAR0L_WMASK);
+ break;
+
+ case Z180_DAR0H:
+ LOG("Z180 DAR0H wr $%02x ($%02x)\n", data, data & Z180_DAR0H_WMASK);
+ IO_DAR0H = (IO_DAR0H & ~Z180_DAR0H_WMASK) | (data & Z180_DAR0H_WMASK);
+ break;
+
+ case Z180_DAR0B:
+ LOG("Z180 DAR0B wr $%02x ($%02x)\n", data, data & Z180_DAR0B_WMASK);
+ IO_DAR0B = (IO_DAR0B & ~Z180_DAR0B_WMASK) | (data & Z180_DAR0B_WMASK);
+ break;
+
+ case Z180_BCR0L:
+ LOG("Z180 BCR0L wr $%02x ($%02x)\n", data, data & Z180_BCR0L_WMASK);
+ IO_BCR0L = (IO_BCR0L & ~Z180_BCR0L_WMASK) | (data & Z180_BCR0L_WMASK);
+ break;
+
+ case Z180_BCR0H:
+ LOG("Z180 BCR0H wr $%02x ($%02x)\n", data, data & Z180_BCR0H_WMASK);
+ IO_BCR0H = (IO_BCR0H & ~Z180_BCR0H_WMASK) | (data & Z180_BCR0H_WMASK);
+ break;
+
+ case Z180_MAR1L:
+ LOG("Z180 MAR1L wr $%02x ($%02x)\n", data, data & Z180_MAR1L_WMASK);
+ IO_MAR1L = (IO_MAR1L & ~Z180_MAR1L_WMASK) | (data & Z180_MAR1L_WMASK);
+ break;
+
+ case Z180_MAR1H:
+ LOG("Z180 MAR1H wr $%02x ($%02x)\n", data, data & Z180_MAR1H_WMASK);
+ IO_MAR1H = (IO_MAR1H & ~Z180_MAR1H_WMASK) | (data & Z180_MAR1H_WMASK);
+ break;
+
+ case Z180_MAR1B:
+ LOG("Z180 MAR1B wr $%02x ($%02x)\n", data, data & Z180_MAR1B_WMASK);
+ IO_MAR1B = (IO_MAR1B & ~Z180_MAR1B_WMASK) | (data & Z180_MAR1B_WMASK);
+ break;
+
+ case Z180_IAR1L:
+ LOG("Z180 IAR1L wr $%02x ($%02x)\n", data, data & Z180_IAR1L_WMASK);
+ IO_IAR1L = (IO_IAR1L & ~Z180_IAR1L_WMASK) | (data & Z180_IAR1L_WMASK);
+ break;
+
+ case Z180_IAR1H:
+ LOG("Z180 IAR1H wr $%02x ($%02x)\n", data, data & Z180_IAR1H_WMASK);
+ IO_IAR1H = (IO_IAR1H & ~Z180_IAR1H_WMASK) | (data & Z180_IAR1H_WMASK);
+ break;
+
+ case Z180_IAR1B:
+ LOG("Z180 IAR1B wr $%02x ($%02x)\n", data, data & Z180_IAR1B_WMASK);
+ IO_IAR1B = (IO_IAR1B & ~Z180_IAR1B_WMASK) | (data & Z180_IAR1B_WMASK);
+ break;
+
+ case Z180_BCR1L:
+ LOG("Z180 BCR1L wr $%02x ($%02x)\n", data, data & Z180_BCR1L_WMASK);
+ IO_BCR1L = (IO_BCR1L & ~Z180_BCR1L_WMASK) | (data & Z180_BCR1L_WMASK);
+ break;
+
+ case Z180_BCR1H:
+ LOG("Z180 BCR1H wr $%02x ($%02x)\n", data, data & Z180_BCR1H_WMASK);
+ IO_BCR1H = (IO_BCR1H & ~Z180_BCR1H_WMASK) | (data & Z180_BCR1H_WMASK);
+ break;
+
+ case Z180_DSTAT:
+ LOG("Z180 DSTAT wr $%02x ($%02x)\n", data, data & Z180_DSTAT_WMASK);
+ IO_DSTAT = (IO_DSTAT & ~Z180_DSTAT_WMASK) | (data & Z180_DSTAT_WMASK);
+ if ((data & (Z180_DSTAT_DE1 | Z180_DSTAT_DWE1)) == Z180_DSTAT_DE1)
+ {
+ IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
+ }
+ if ((data & (Z180_DSTAT_DE0 | Z180_DSTAT_DWE0)) == Z180_DSTAT_DE0)
+ {
+ IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
+ }
+ break;
+
+ case Z180_DMODE:
+ LOG("Z180 DMODE wr $%02x ($%02x)\n", data, data & Z180_DMODE_WMASK);
+ IO_DMODE = (IO_DMODE & ~Z180_DMODE_WMASK) | (data & Z180_DMODE_WMASK);
+ break;
+
+ case Z180_DCNTL:
+ LOG("Z180 DCNTL wr $%02x ($%02x)\n", data, data & Z180_DCNTL_WMASK);
+ IO_DCNTL = (IO_DCNTL & ~Z180_DCNTL_WMASK) | (data & Z180_DCNTL_WMASK);
+ break;
+
+ case Z180_IL:
+ LOG("Z180 IL wr $%02x ($%02x)\n", data, data & Z180_IL_WMASK);
+ IO_IL = (IO_IL & ~Z180_IL_WMASK) | (data & Z180_IL_WMASK);
+ break;
+
+ case Z180_ITC:
+ LOG("Z180 ITC wr $%02x ($%02x)\n", data, data & Z180_ITC_WMASK);
+ IO_ITC = (IO_ITC & ~Z180_ITC_WMASK) | (data & Z180_ITC_WMASK);
+ break;
+
+ case Z180_IO35:
+ LOG("Z180 IO35 wr $%02x ($%02x)\n", data, data & Z180_IO35_WMASK);
+ IO_IO35 = (IO_IO35 & ~Z180_IO35_WMASK) | (data & Z180_IO35_WMASK);
+ break;
+
+ case Z180_RCR:
+ LOG("Z180 RCR wr $%02x ($%02x)\n", data, data & Z180_RCR_WMASK);
+ IO_RCR = (IO_RCR & ~Z180_RCR_WMASK) | (data & Z180_RCR_WMASK);
+ break;
+
+ case Z180_IO37:
+ LOG("Z180 IO37 wr $%02x ($%02x)\n", data, data & Z180_IO37_WMASK);
+ IO_IO37 = (IO_IO37 & ~Z180_IO37_WMASK) | (data & Z180_IO37_WMASK);
+ break;
+
+ case Z180_CBR:
+ LOG("Z180 CBR wr $%02x ($%02x)\n", data, data & Z180_CBR_WMASK);
+ IO_CBR = (IO_CBR & ~Z180_CBR_WMASK) | (data & Z180_CBR_WMASK);
+ z180_mmu();
+ break;
+
+ case Z180_BBR:
+ LOG("Z180 BBR wr $%02x ($%02x)\n", data, data & Z180_BBR_WMASK);
+ IO_BBR = (IO_BBR & ~Z180_BBR_WMASK) | (data & Z180_BBR_WMASK);
+ z180_mmu();
+ break;
+
+ case Z180_CBAR:
+ LOG("Z180 CBAR wr $%02x ($%02x)\n", data, data & Z180_CBAR_WMASK);
+ IO_CBAR = (IO_CBAR & ~Z180_CBAR_WMASK) | (data & Z180_CBAR_WMASK);
+ z180_mmu();
+ break;
+
+ case Z180_IO3B:
+ LOG("Z180 IO3B wr $%02x ($%02x)\n", data, data & Z180_IO3B_WMASK);
+ IO_IO3B = (IO_IO3B & ~Z180_IO3B_WMASK) | (data & Z180_IO3B_WMASK);
+ break;
+
+ case Z180_IO3C:
+ LOG("Z180 IO3C wr $%02x ($%02x)\n", data, data & Z180_IO3C_WMASK);
+ IO_IO3C = (IO_IO3C & ~Z180_IO3C_WMASK) | (data & Z180_IO3C_WMASK);
+ break;
+
+ case Z180_IO3D:
+ LOG("Z180 IO3D wr $%02x ($%02x)\n", data, data & Z180_IO3D_WMASK);
+ IO_IO3D = (IO_IO3D & ~Z180_IO3D_WMASK) | (data & Z180_IO3D_WMASK);
+ break;
+
+ case Z180_OMCR:
+ LOG("Z180 OMCR wr $%02x ($%02x)\n", data, data & Z180_OMCR_WMASK);
+ IO_OMCR = (IO_OMCR & ~Z180_OMCR_WMASK) | (data & Z180_OMCR_WMASK);
+ break;
+
+ case Z180_IOCR:
+ LOG("Z180 IOCR wr $%02x ($%02x)\n", data, data & Z180_IOCR_WMASK);
+ IO_IOCR = (IO_IOCR & ~Z180_IOCR_WMASK) | (data & Z180_IOCR_WMASK);
+ break;
+ }
+}
+
+int /*z180_device::*/z180_dma0(int max_cycles)
+{
+ offs_t sar0 = 65536 * IO_SAR0B + 256 * IO_SAR0H + IO_SAR0L;
+ offs_t dar0 = 65536 * IO_DAR0B + 256 * IO_DAR0H + IO_DAR0L;
+ int bcr0 = 256 * IO_BCR0H + IO_BCR0L;
+
+ if (bcr0 == 0)
+ {
+ bcr0 = 0x10000;
+ }
+
+ int count = (IO_DMODE & Z180_DMODE_MMOD) ? bcr0 : 1;
+ int cycles = 0;
+
+ if (!(IO_DSTAT & Z180_DSTAT_DE0))
+ {
+ return 0;
+ }
+
+ while (count > 0)
+ {
+ m_extra_cycles = 0;
+ /* last transfer happening now? */
+ if (bcr0 == 1)
+ {
+ m_iol |= Z180_TEND0;
+ }
+ switch( IO_DMODE & (Z180_DMODE_SM | Z180_DMODE_DM) )
+ {
+ case 0x00: /* memory SAR0+1 to memory DAR0+1 */
+ m_program_write_byte(dar0++, m_program_read_byte(sar0++));
+ cycles += (IO_DCNTL >> 6) * 2; // memory wait states
+ bcr0--;
+ break;
+ case 0x04: /* memory SAR0-1 to memory DAR0+1 */
+ m_program_write_byte(dar0++, m_program_read_byte(sar0--));
+ cycles += (IO_DCNTL >> 6) * 2; // memory wait states
+ bcr0--;
+ break;
+ case 0x08: /* memory SAR0 fixed to memory DAR0+1 */
+ m_program_write_byte(dar0++, m_program_read_byte(sar0));
+ cycles += (IO_DCNTL >> 6) * 2; // memory wait states
+ bcr0--;
+ break;
+ case 0x0c: /* I/O SAR0 fixed to memory DAR0+1 */
+ if (m_iol & Z180_DREQ0)
+ {
+ m_program_write_byte(dar0++, IN(sar0));
+ cycles += IO_DCNTL >> 6; // memory wait states
+ bcr0--;
+ /* edge sensitive DREQ0 ? */
+ if (IO_DCNTL & Z180_DCNTL_DMS0)
+ {
+ m_iol &= ~Z180_DREQ0;
+ count = 0;
+ }
+ }
+ break;
+ case 0x10: /* memory SAR0+1 to memory DAR0-1 */
+ m_program_write_byte(dar0--, m_program_read_byte(sar0++));
+ cycles += (IO_DCNTL >> 6) * 2; // memory wait states
+ bcr0--;
+ break;
+ case 0x14: /* memory SAR0-1 to memory DAR0-1 */
+ m_program_write_byte(dar0--, m_program_read_byte(sar0--));
+ cycles += (IO_DCNTL >> 6) * 2; // memory wait states
+ bcr0--;
+ break;
+ case 0x18: /* memory SAR0 fixed to memory DAR0-1 */
+ m_program_write_byte(dar0--, m_program_read_byte(sar0));
+ cycles += (IO_DCNTL >> 6) * 2; // memory wait states
+ bcr0--;
+ break;
+ case 0x1c: /* I/O SAR0 fixed to memory DAR0-1 */
+ if (m_iol & Z180_DREQ0)
+ {
+ m_program_write_byte(dar0--, IN(sar0));
+ cycles += IO_DCNTL >> 6; // memory wait states
+ bcr0--;
+ /* edge sensitive DREQ0 ? */
+ if (IO_DCNTL & Z180_DCNTL_DMS0)
+ {
+ m_iol &= ~Z180_DREQ0;
+ count = 0;
+ }
+ }
+ break;
+ case 0x20: /* memory SAR0+1 to memory DAR0 fixed */
+ m_program_write_byte(dar0, m_program_read_byte(sar0++));
+ cycles += (IO_DCNTL >> 6) * 2; // memory wait states
+ bcr0--;
+ break;
+ case 0x24: /* memory SAR0-1 to memory DAR0 fixed */
+ m_program_write_byte(dar0, m_program_read_byte(sar0--));
+ cycles += (IO_DCNTL >> 6) * 2; // memory wait states
+ bcr0--;
+ break;
+ case 0x28: /* reserved */
+ break;
+ case 0x2c: /* reserved */
+ break;
+ case 0x30: /* memory SAR0+1 to I/O DAR0 fixed */
+ if (m_iol & Z180_DREQ0)
+ {
+ OUT(dar0, m_program_read_byte(sar0++));
+ cycles += IO_DCNTL >> 6; // memory wait states
+ bcr0--;
+ /* edge sensitive DREQ0 ? */
+ if (IO_DCNTL & Z180_DCNTL_DMS0)
+ {
+ m_iol &= ~Z180_DREQ0;
+ count = 0;
+ }
+ }
+ break;
+ case 0x34: /* memory SAR0-1 to I/O DAR0 fixed */
+ if (m_iol & Z180_DREQ0)
+ {
+ OUT(dar0, m_program_read_byte(sar0--));
+ cycles += IO_DCNTL >> 6; // memory wait states
+ bcr0--;
+ /* edge sensitive DREQ0 ? */
+ if (IO_DCNTL & Z180_DCNTL_DMS0)
+ {
+ m_iol &= ~Z180_DREQ0;
+ count = 0;
+ }
+ }
+ break;
+ case 0x38: /* reserved */
+ break;
+ case 0x3c: /* reserved */
+ break;
+ }
+ count--;
+ cycles += 6 + m_extra_cycles; // use extra_cycles for I/O wait states
+ if (cycles > max_cycles)
+ break;
+ }
+
+ IO_SAR0L = sar0;
+ IO_SAR0H = sar0 >> 8;
+ IO_SAR0B = sar0 >> 16;
+ IO_DAR0L = dar0;
+ IO_DAR0H = dar0 >> 8;
+ IO_DAR0B = dar0 >> 16;
+ IO_BCR0L = bcr0;
+ IO_BCR0H = bcr0 >> 8;
+
+ /* DMA terminal count? */
+ if (bcr0 == 0)
+ {
+ m_iol &= ~Z180_TEND0;
+ IO_DSTAT &= ~Z180_DSTAT_DE0;
+ /* terminal count interrupt enabled? */
+ if (IO_DSTAT & Z180_DSTAT_DIE0 && m_IFF1)
+ m_int_pending[Z180_INT_DMA0] = 1;
+ }
+ return cycles;
+}
+
+int /*z180_device::*/z180_dma1()
+{
+ offs_t mar1 = 65536 * IO_MAR1B + 256 * IO_MAR1H + IO_MAR1L;
+ offs_t iar1 = 256 * IO_IAR1H + IO_IAR1L;
+ int bcr1 = 256 * IO_BCR1H + IO_BCR1L;
+
+ if (bcr1 == 0)
+ {
+ bcr1 = 0x10000;
+ }
+
+ int cycles = 0;
+
+ if ((m_iol & Z180_DREQ1) == 0)
+ return 0;
+
+ if (!(IO_DSTAT & Z180_DSTAT_DE1))
+ {
+ return 0;
+ }
+
+ /* last transfer happening now? */
+ if (bcr1 == 1)
+ {
+ m_iol |= Z180_TEND1;
+ }
+
+ m_extra_cycles = 0;
+
+ switch (IO_DCNTL & (Z180_DCNTL_DIM1 | Z180_DCNTL_DIM0))
+ {
+ case 0x00: /* memory MAR1+1 to I/O IAR1 fixed */
+ m_iospace_write_byte(iar1, m_program_read_byte(mar1++));
+ break;
+ case 0x01: /* memory MAR1-1 to I/O IAR1 fixed */
+ m_iospace_write_byte(iar1, m_program_read_byte(mar1--));
+ break;
+ case 0x02: /* I/O IAR1 fixed to memory MAR1+1 */
+ m_program_write_byte(mar1++, m_iospace_read_byte(iar1));
+ break;
+ case 0x03: /* I/O IAR1 fixed to memory MAR1-1 */
+ m_program_write_byte(mar1--, m_iospace_read_byte(iar1));
+ break;
+ }
+
+ cycles += IO_DCNTL >> 6; // memory wait states
+ cycles += m_extra_cycles; // use extra_cycles for I/O wait states
+
+ /* edge sensitive DREQ1 ? */
+ if (IO_DCNTL & Z180_DCNTL_DIM1)
+ m_iol &= ~Z180_DREQ1;
+
+ IO_MAR1L = mar1;
+ IO_MAR1H = mar1 >> 8;
+ IO_MAR1B = mar1 >> 16;
+ IO_BCR1L = bcr1;
+ IO_BCR1H = bcr1 >> 8;
+
+ /* DMA terminal count? */
+ if (bcr1 == 0)
+ {
+ m_iol &= ~Z180_TEND1;
+ IO_DSTAT &= ~Z180_DSTAT_DE1;
+ if (IO_DSTAT & Z180_DSTAT_DIE1 && m_IFF1)
+ m_int_pending[Z180_INT_DMA1] = 1;
+ }
+
+ /* six cycles per transfer (minimum) */
+ return 6 + cycles;
+}
+
+void /*z180_device::*/z180_write_iolines(uint32_t data)
+{
+ uint32_t changes = m_iol ^ data;
+
+ /* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
+ if (changes & Z180_CKA0)
+ {
+ LOG("Z180 CKA0 %d\n", data & Z180_CKA0 ? 1 : 0);
+ m_iol = (m_iol & ~Z180_CKA0) | (data & Z180_CKA0);
+ }
+
+ /* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
+ if (changes & Z180_CKA1)
+ {
+ LOG("Z180 CKA1 %d\n", data & Z180_CKA1 ? 1 : 0);
+ m_iol = (m_iol & ~Z180_CKA1) | (data & Z180_CKA1);
+ }
+
+ /* I/O serial clock (active high) */
+ if (changes & Z180_CKS)
+ {
+ LOG("Z180 CKS %d\n", data & Z180_CKS ? 1 : 0);
+ m_iol = (m_iol & ~Z180_CKS) | (data & Z180_CKS);
+ }
+
+ /* I clear to send 0 (active low) */
+ if (changes & Z180_CTS0)
+ {
+ LOG("Z180 CTS0 %d\n", data & Z180_CTS0 ? 1 : 0);
+ m_iol = (m_iol & ~Z180_CTS0) | (data & Z180_CTS0);
+ }
+
+ /* I clear to send 1 (active low) or RXS (mux) */
+ if (changes & Z180_CTS1)
+ {
+ LOG("Z180 CTS1 %d\n", data & Z180_CTS1 ? 1 : 0);
+ m_iol = (m_iol & ~Z180_CTS1) | (data & Z180_CTS1);
+ }
+
+ /* I data carrier detect (active low) */
+ if (changes & Z180_DCD0)
+ {
+ LOG("Z180 DCD0 %d\n", data & Z180_DCD0 ? 1 : 0);
+ m_iol = (m_iol & ~Z180_DCD0) | (data & Z180_DCD0);
+ }
+
+ /* I data request DMA ch 0 (active low) or CKA0 (mux) */
+ if (changes & Z180_DREQ0)
+ {
+ LOG("Z180 DREQ0 %d\n", data & Z180_DREQ0 ? 1 : 0);
+ m_iol = (m_iol & ~Z180_DREQ0) | (data & Z180_DREQ0);
+ }
+
+ /* I data request DMA ch 1 (active low) */
+ if (changes & Z180_DREQ1)
+ {
+ LOG("Z180 DREQ1 %d\n", data & Z180_DREQ1 ? 1 : 0);
+ m_iol = (m_iol & ~Z180_DREQ1) | (data & Z180_DREQ1);
+ }
+
+ /* I asynchronous receive data 0 (active high) */
+ if (changes & Z180_RXA0)
+ {
+ LOG("Z180 RXA0 %d\n", data & Z180_RXA0 ? 1 : 0);
+ m_iol = (m_iol & ~Z180_RXA0) | (data & Z180_RXA0);
+ }
+
+ /* I asynchronous receive data 1 (active high) */
+ if (changes & Z180_RXA1)
+ {
+ LOG("Z180 RXA1 %d\n", data & Z180_RXA1 ? 1 : 0);
+ m_iol = (m_iol & ~Z180_RXA1) | (data & Z180_RXA1);
+ }
+
+ /* I clocked serial receive data (active high) or CTS1 (mux) */
+ if (changes & Z180_RXS)
+ {
+ LOG("Z180 RXS %d\n", data & Z180_RXS ? 1 : 0);
+ m_iol = (m_iol & ~Z180_RXS) | (data & Z180_RXS);
+ }
+
+ /* O request to send (active low) */
+ if (changes & Z180_RTS0)
+ {
+ LOG("Z180 RTS0 won't change output\n");
+ }
+
+ /* O transfer end 0 (active low) or CKA1 (mux) */
+ if (changes & Z180_TEND0)
+ {
+ LOG("Z180 TEND0 won't change output\n");
+ }
+
+ /* O transfer end 1 (active low) */
+ if (changes & Z180_TEND1)
+ {
+ LOG("Z180 TEND1 won't change output\n");
+ }
+
+ /* O transfer out (PRT channel, active low) or A18 (mux) */
+ if (changes & Z180_A18_TOUT)
+ {
+ LOG("Z180 TOUT won't change output\n");
+ }
+
+ /* O asynchronous transmit data 0 (active high) */
+ if (changes & Z180_TXA0)
+ {
+ LOG("Z180 TXA0 won't change output\n");
+ }
+
+ /* O asynchronous transmit data 1 (active high) */
+ if (changes & Z180_TXA1)
+ {
+ LOG("Z180 TXA1 won't change output\n");
+ }
+
+ /* O clocked serial transmit data (active high) */
+ if (changes & Z180_TXS)
+ {
+ LOG("Z180 TXS won't change output\n");
+ }
+}
+
+void /*z180_device::*/device_start()
+{
+ int i, p;
+ int oldval, newval, val;
+ uint8_t *padd, *padc, *psub, *psbc;
+
+ /* allocate big flag arrays once */
+ SZHVC_add = (uint8_t *)malloc(2*256*256); //std::make_unique<uint8_t[]>(2*256*256);
+ rassert(SZHVC_add);
+ SZHVC_sub = (uint8_t *)malloc(2*256*256); //std::make_unique<uint8_t[]>(2*256*256);
+ rassert(SZHVC_sub);
+
+ padd = &SZHVC_add[ 0*256];
+ padc = &SZHVC_add[256*256];
+ psub = &SZHVC_sub[ 0*256];
+ psbc = &SZHVC_sub[256*256];
+ for (oldval = 0; oldval < 256; oldval++)
+ {
+ for (newval = 0; newval < 256; newval++)
+ {
+ /* add or adc w/o carry set */
+ val = newval - oldval;
+ *padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
+ *padd |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
+
+ if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF;
+ if( newval < oldval ) *padd |= CF;
+ if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF;
+ padd++;
+
+ /* adc with carry set */
+ val = newval - oldval - 1;
+ *padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
+ *padc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
+ if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF;
+ if( newval <= oldval ) *padc |= CF;
+ if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF;
+ padc++;
+
+ /* cp, sub or sbc w/o carry set */
+ val = oldval - newval;
+ *psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
+ *psub |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
+ if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF;
+ if( newval > oldval ) *psub |= CF;
+ if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF;
+ psub++;
+
+ /* sbc with carry set */
+ val = oldval - newval - 1;
+ *psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
+ *psbc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
+ if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF;
+ if( newval >= oldval ) *psbc |= CF;
+ if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF;
+ psbc++;
+ }
+ }
+ for (i = 0; i < 256; i++)
+ {
+ p = 0;
+ if( i&0x01 ) ++p;
+ if( i&0x02 ) ++p;
+ if( i&0x04 ) ++p;
+ if( i&0x08 ) ++p;
+ if( i&0x10 ) ++p;
+ if( i&0x20 ) ++p;
+ if( i&0x40 ) ++p;
+ if( i&0x80 ) ++p;
+ SZ[i] = i ? i & SF : ZF;
+ SZ[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */
+ SZ_BIT[i] = i ? i & SF : ZF | PF;
+ SZ_BIT[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */
+ SZP[i] = SZ[i] | ((p & 1) ? 0 : PF);
+ SZHV_inc[i] = SZ[i];
+ if( i == 0x80 ) SZHV_inc[i] |= VF;
+ if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF;
+ SZHV_dec[i] = SZ[i] | NF;
+ if( i == 0x7f ) SZHV_dec[i] |= VF;
+ if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF;
+ }
+
+// m_program = &space(AS_PROGRAM);
+// m_cache = m_program_cache<0, 0, ENDIANNESS_LITTLE>();
+// m_oprogram = has_space(AS_OPCODES) ? &space(AS_OPCODES) : m_program;
+// m_ocache = m_oprogram->cache<0, 0, ENDIANNESS_LITTLE>();
+// m_iospace = &space(AS_IO);
+
+// /* set up the state table */
+// {
+// state_add(Z180_PC, "PC", m_PC.w.l);
+// state_add(STATE_GENPC, "GENPC", _PCD).noshow();
+// state_add(STATE_GENPCBASE, "CURPC", m_PREPC.w.l).noshow();
+// state_add(Z180_SP, "SP", _SPD);
+// state_add(STATE_GENSP, "GENSP", m_SP.w.l).noshow();
+// state_add(STATE_GENFLAGS, "GENFLAGS", m_AF.b.l).noshow().formatstr("%8s");
+// state_add(Z180_A, "A", _A).noshow();
+// state_add(Z180_B, "B", _B).noshow();
+// state_add(Z180_C, "C", _C).noshow();
+// state_add(Z180_D, "D", _D).noshow();
+// state_add(Z180_E, "E", _E).noshow();
+// state_add(Z180_H, "H", _H).noshow();
+// state_add(Z180_L, "L", _L).noshow();
+// state_add(Z180_AF, "AF", m_AF.w.l);
+// state_add(Z180_BC, "BC", m_BC.w.l);
+// state_add(Z180_DE, "DE", m_DE.w.l);
+// state_add(Z180_HL, "HL", m_HL.w.l);
+// state_add(Z180_IX, "IX", m_IX.w.l);
+// state_add(Z180_IY, "IY", m_IY.w.l);
+// state_add(Z180_AF2, "AF2", m_AF2.w.l);
+// state_add(Z180_BC2, "BC2", m_BC2.w.l);
+// state_add(Z180_DE2, "DE2", m_DE2.w.l);
+// state_add(Z180_HL2, "HL2", m_HL2.w.l);
+// state_add(Z180_R, "R", m_rtemp).callimport().callexport();
+// state_add(Z180_I, "I", m_I);
+// state_add(Z180_IM, "IM", m_IM).mask(0x3);
+// state_add(Z180_IFF1, "IFF1", m_IFF1).mask(0x1);
+// state_add(Z180_IFF2, "IFF2", m_IFF2).mask(0x1);
+// state_add(Z180_HALT, "HALT", m_HALT).mask(0x1);
+//
+// state_add(Z180_IOLINES, "IOLINES", m_ioltemp).mask(0xffffff).callimport();
+//
+// state_add(Z180_CNTLA0, "CNTLA0", IO_CNTLA0);
+// state_add(Z180_CNTLA1, "CNTLA1", IO_CNTLA1);
+// state_add(Z180_CNTLB0, "CNTLB0", IO_CNTLB0);
+// state_add(Z180_CNTLB1, "CNTLB1", IO_CNTLB1);
+// state_add(Z180_STAT0, "STAT0", IO_STAT0);
+// state_add(Z180_STAT1, "STAT1", IO_STAT1);
+// state_add(Z180_TDR0, "TDR0", IO_TDR0);
+// state_add(Z180_TDR1, "TDR1", IO_TDR1);
+// state_add(Z180_RDR0, "RDR0", IO_RDR0);
+// state_add(Z180_RDR1, "RDR1", IO_RDR1);
+// state_add(Z180_CNTR, "CNTR", IO_CNTR);
+// state_add(Z180_TRDR, "TRDR", IO_TRDR);
+// state_add(Z180_TMDR0L, "TMDR0L", IO_TMDR0L);
+// state_add(Z180_TMDR0H, "TMDR0H", IO_TMDR0H);
+// state_add(Z180_RLDR0L, "RLDR0L", IO_RLDR0L);
+// state_add(Z180_RLDR0H, "RLDR0H", IO_RLDR0H);
+// state_add(Z180_TCR, "TCR", IO_TCR);
+// state_add(Z180_IO11, "IO11", IO_IO11);
+// state_add(Z180_ASEXT0, "ASEXT0", IO_ASEXT0);
+// state_add(Z180_ASEXT1, "ASEXT1", IO_ASEXT1);
+// state_add(Z180_TMDR1L, "TMDR1L", IO_TMDR1L);
+// state_add(Z180_TMDR1H, "TMDR1H", IO_TMDR1H);
+// state_add(Z180_RLDR1L, "RLDR1L", IO_RLDR1L);
+// state_add(Z180_RLDR1H, "RLDR1H", IO_RLDR1H);
+// state_add(Z180_FRC, "FRC", IO_FRC);
+// state_add(Z180_IO19, "IO19", IO_IO19);
+// state_add(Z180_ASTC0L, "ASTC0L", IO_ASTC0L);
+// state_add(Z180_ASTC0H, "ASTC0H", IO_ASTC0H);
+// state_add(Z180_ASTC1L, "ASTC1L", IO_ASTC1L);
+// state_add(Z180_ASTC1H, "ASTC1H", IO_ASTC1H);
+// state_add(Z180_CMR, "CMR", IO_CMR);
+// state_add(Z180_CCR, "CCR", IO_CCR);
+// state_add(Z180_SAR0L, "SAR0L", IO_SAR0L);
+// state_add(Z180_SAR0H, "SAR0H", IO_SAR0H);
+// state_add(Z180_SAR0B, "SAR0B", IO_SAR0B);
+// state_add(Z180_DAR0L, "DAR0L", IO_DAR0L);
+// state_add(Z180_DAR0H, "DAR0H", IO_DAR0H);
+// state_add(Z180_DAR0B, "DAR0B", IO_DAR0B);
+// state_add(Z180_BCR0L, "BCR0L", IO_BCR0L);
+// state_add(Z180_BCR0H, "BCR0H", IO_BCR0H);
+// state_add(Z180_MAR1L, "MAR1L", IO_MAR1L);
+// state_add(Z180_MAR1H, "MAR1H", IO_MAR1H);
+// state_add(Z180_MAR1B, "MAR1B", IO_MAR1B);
+// state_add(Z180_IAR1L, "IAR1L", IO_IAR1L);
+// state_add(Z180_IAR1H, "IAR1H", IO_IAR1H);
+// state_add(Z180_IAR1B, "IAR1B", IO_IAR1B);
+// state_add(Z180_BCR1L, "BCR1L", IO_BCR1L);
+// state_add(Z180_BCR1H, "BCR1H", IO_BCR1H);
+// state_add(Z180_DSTAT, "DSTAT", IO_DSTAT);
+// state_add(Z180_DMODE, "DMODE", IO_DMODE);
+// state_add(Z180_DCNTL, "DCNTL", IO_DCNTL);
+// state_add(Z180_IL, "IL", IO_IL);
+// state_add(Z180_ITC, "ITC", IO_ITC);
+// state_add(Z180_IO35, "IO35", IO_IO35);
+// state_add(Z180_RCR, "RCR", IO_RCR);
+// state_add(Z180_IO37, "IO37", IO_IO37);
+// state_add(Z180_CBR, "CBR", IO_CBR).callimport();
+// state_add(Z180_BBR, "BBR", IO_BBR).callimport();
+// state_add(Z180_CBAR, "CBAR", IO_CBAR).callimport();
+// state_add(Z180_IO3B, "IO3B", IO_IO3B);
+// state_add(Z180_IO3C, "IO3C", IO_IO3C);
+// state_add(Z180_IO3D, "IO3D", IO_IO3D);
+// state_add(Z180_OMCR, "OMCR", IO_OMCR);
+// state_add(Z180_IOCR, "IOCR", IO_IOCR);
+// }
+//
+// save_item(NAME(m_AF.w.l));
+// save_item(NAME(m_BC.w.l));
+// save_item(NAME(m_DE.w.l));
+// save_item(NAME(m_HL.w.l));
+// save_item(NAME(m_IX.w.l));
+// save_item(NAME(m_IY.w.l));
+// save_item(NAME(m_PC.w.l));
+// save_item(NAME(m_SP.w.l));
+// save_item(NAME(m_AF2.w.l));
+// save_item(NAME(m_BC2.w.l));
+// save_item(NAME(m_DE2.w.l));
+// save_item(NAME(m_HL2.w.l));
+// save_item(NAME(m_R));
+// save_item(NAME(m_R2));
+// save_item(NAME(m_IFF1));
+// save_item(NAME(m_IFF2));
+// save_item(NAME(m_HALT));
+// save_item(NAME(m_IM));
+// save_item(NAME(m_I));
+// save_item(NAME(m_nmi_state));
+// save_item(NAME(m_nmi_pending));
+// save_item(NAME(m_irq_state));
+// save_item(NAME(m_int_pending));
+// save_item(NAME(m_timer_cnt));
+// save_item(NAME(m_dma0_cnt));
+// save_item(NAME(m_dma1_cnt));
+// save_item(NAME(m_after_EI));
+//
+// save_item(NAME(m_tif));
+//
+// save_item(NAME(m_read_tcr_tmdr));
+// save_item(NAME(m_tmdr_value));
+// save_item(NAME(m_tmdrh));
+// save_item(NAME(m_tmdr_latch));
+//
+// save_item(NAME(m_io));
+// save_item(NAME(m_iol));
+// save_item(NAME(m_ioltemp));
+//
+// save_item(NAME(m_mmu));
+//
+// set_icountptr(m_icount);
+}
+
+/****************************************************************************
+ * Reset registers to their initial values
+ ****************************************************************************/
+void /*z180_device::*/device_reset()
+{
+ _PPC = 0;
+ _PCD = 0;
+ _SPD = 0;
+ _AFD = 0;
+ _BCD = 0;
+ _DED = 0;
+ _HLD = 0;
+ _IXD = 0;
+ _IYD = 0;
+ m_AF2.d = 0;
+ m_BC2.d = 0;
+ m_DE2.d = 0;
+ m_HL2.d = 0;
+ m_R = 0;
+ m_R2 = 0;
+ m_IFF1 = 0;
+ m_IFF2 = 0;
+ m_HALT = 0;
+ m_IM = 0;
+ m_I = 0;
+ m_tmdr_latch = 0;
+ m_read_tcr_tmdr[0] = 0;
+ m_read_tcr_tmdr[1] = 0;
+ m_iol = 0;
+ memset(m_io, 0, sizeof(m_io));
+ memset(m_mmu, 0, sizeof(m_mmu));
+ m_tmdrh[0] = 0;
+ m_tmdrh[1] = 0;
+ m_tmdr_value[0] = 0xffff;
+ m_tmdr_value[1] = 0xffff;
+ m_tif[0] = 0;
+ m_tif[1] = 0;
+ m_nmi_state = CLEAR_LINE;
+ m_nmi_pending = 0;
+ m_irq_state[0] = CLEAR_LINE;
+ m_irq_state[1] = CLEAR_LINE;
+ m_irq_state[2] = CLEAR_LINE;
+ m_after_EI = 0;
+ m_ea = 0;
+
+ memcpy(m_cc, (uint8_t *)cc_default, sizeof(m_cc));
+ _IX = _IY = 0xffff; /* IX and IY are FFFF after a reset! */
+ _F = ZF; /* Zero flag is set */
+
+ for (int i=0; i <= Z180_INT_MAX; i++)
+ {
+ m_int_pending[i] = 0;
+ }
+
+ m_timer_cnt = 0;
+ m_dma0_cnt = 0;
+ m_dma1_cnt = 0;
+
+ /* reset io registers */
+ IO_CNTLA0 = Z180_CNTLA0_RESET;
+ IO_CNTLA1 = Z180_CNTLA1_RESET;
+ IO_CNTLB0 = Z180_CNTLB0_RESET;
+ IO_CNTLB1 = Z180_CNTLB1_RESET;
+ IO_STAT0 = Z180_STAT0_RESET;
+ IO_STAT1 = Z180_STAT1_RESET;
+ IO_TDR0 = Z180_TDR0_RESET;
+ IO_TDR1 = Z180_TDR1_RESET;
+ IO_RDR0 = Z180_RDR0_RESET;
+ IO_RDR1 = Z180_RDR1_RESET;
+ IO_CNTR = Z180_CNTR_RESET;
+ IO_TRDR = Z180_TRDR_RESET;
+ IO_TMDR0L = Z180_TMDR0L_RESET;
+ IO_TMDR0H = Z180_TMDR0H_RESET;
+ IO_RLDR0L = Z180_RLDR0L_RESET;
+ IO_RLDR0H = Z180_RLDR0H_RESET;
+ IO_TCR = Z180_TCR_RESET;
+ IO_IO11 = Z180_IO11_RESET;
+ IO_ASEXT0 = Z180_ASEXT0_RESET;
+ IO_ASEXT1 = Z180_ASEXT1_RESET;
+ IO_TMDR1L = Z180_TMDR1L_RESET;
+ IO_TMDR1H = Z180_TMDR1H_RESET;
+ IO_RLDR1L = Z180_RLDR1L_RESET;
+ IO_RLDR1H = Z180_RLDR1H_RESET;
+ IO_FRC = Z180_FRC_RESET;
+ IO_IO19 = Z180_IO19_RESET;
+ IO_ASTC0L = Z180_ASTC0L_RESET;
+ IO_ASTC0H = Z180_ASTC0H_RESET;
+ IO_ASTC1L = Z180_ASTC1L_RESET;
+ IO_ASTC1H = Z180_ASTC1H_RESET;
+ IO_CMR = Z180_CMR_RESET;
+ IO_CCR = Z180_CCR_RESET;
+ IO_SAR0L = Z180_SAR0L_RESET;
+ IO_SAR0H = Z180_SAR0H_RESET;
+ IO_SAR0B = Z180_SAR0B_RESET;
+ IO_DAR0L = Z180_DAR0L_RESET;
+ IO_DAR0H = Z180_DAR0H_RESET;
+ IO_DAR0B = Z180_DAR0B_RESET;
+ IO_BCR0L = Z180_BCR0L_RESET;
+ IO_BCR0H = Z180_BCR0H_RESET;
+ IO_MAR1L = Z180_MAR1L_RESET;
+ IO_MAR1H = Z180_MAR1H_RESET;
+ IO_MAR1B = Z180_MAR1B_RESET;
+ IO_IAR1L = Z180_IAR1L_RESET;
+ IO_IAR1H = Z180_IAR1H_RESET;
+ IO_IAR1B = Z180_IAR1B_RESET;
+ IO_BCR1L = Z180_BCR1L_RESET;
+ IO_BCR1H = Z180_BCR1H_RESET;
+ IO_DSTAT = Z180_DSTAT_RESET;
+ IO_DMODE = Z180_DMODE_RESET;
+ IO_DCNTL = Z180_DCNTL_RESET;
+ IO_IL = Z180_IL_RESET;
+ IO_ITC = Z180_ITC_RESET;
+ IO_IO35 = Z180_IO35_RESET;
+ IO_RCR = Z180_RCR_RESET;
+ IO_IO37 = Z180_IO37_RESET;
+ IO_CBR = Z180_CBR_RESET;
+ IO_BBR = Z180_BBR_RESET;
+ IO_CBAR = Z180_CBAR_RESET;
+ IO_IO3B = Z180_IO3B_RESET;
+ IO_IO3C = Z180_IO3C_RESET;
+ IO_IO3D = Z180_IO3D_RESET;
+ IO_OMCR = Z180_OMCR_RESET;
+ IO_IOCR = Z180_IOCR_RESET;
+
+ z180_mmu();
+}
+
+/* Handle PRT timers, decreasing them after 20 clocks and returning the new icount base that needs to be used for the next check */
+void /*z180_device::*/clock_timers()
+{
+ m_timer_cnt++;
+ if (m_timer_cnt >= 20)
+ {
+ m_timer_cnt = 0;
+ /* Programmable Reload Timer 0 */
+ if(IO_TCR & Z180_TCR_TDE0)
+ {
+ if(m_tmdr_value[0] == 0)
+ {
+ m_tmdr_value[0] = IO_RLDR0L | (IO_RLDR0H << 8);
+ m_tif[0] = 1;
+ }
+ else
+ m_tmdr_value[0]--;
+ }
+
+ /* Programmable Reload Timer 1 */
+ if(IO_TCR & Z180_TCR_TDE1)
+ {
+ if(m_tmdr_value[1] == 0)
+ {
+ m_tmdr_value[1] = IO_RLDR1L | (IO_RLDR1H << 8);
+ m_tif[1] = 1;
+ }
+ else
+ m_tmdr_value[1]--;
+ }
+
+ if((IO_TCR & Z180_TCR_TIE0) && m_tif[0])
+ {
+ // check if we can take the interrupt
+ if(m_IFF1 && !m_after_EI)
+ {
+ m_int_pending[Z180_INT_PRT0] = 1;
+ }
+ }
+
+ if((IO_TCR & Z180_TCR_TIE1) && m_tif[1])
+ {
+ // check if we can take the interrupt
+ if(m_IFF1 && !m_after_EI)
+ {
+ m_int_pending[Z180_INT_PRT1] = 1;
+ }
+ }
+
+ }
+}
+
+int /*z180_device::*/check_interrupts()
+{
+ int i;
+ int cycles = 0;
+
+ /* check for IRQs before each instruction */
+ if (m_IFF1 && !m_after_EI)
+ {
+ if (m_irq_state[0] != CLEAR_LINE && (IO_ITC & Z180_ITC_ITE0) == Z180_ITC_ITE0)
+ m_int_pending[Z180_INT_IRQ0] = 1;
+
+ if (m_irq_state[1] != CLEAR_LINE && (IO_ITC & Z180_ITC_ITE1) == Z180_ITC_ITE1)
+ m_int_pending[Z180_INT_IRQ1] = 1;
+
+ if (m_irq_state[2] != CLEAR_LINE && (IO_ITC & Z180_ITC_ITE2) == Z180_ITC_ITE2)
+ m_int_pending[Z180_INT_IRQ2] = 1;
+ }
+
+ for (i = 0; i <= Z180_INT_MAX; i++)
+ if (m_int_pending[i])
+ {
+ cycles += take_interrupt(i);
+ m_int_pending[i] = 0;
+ break;
+ }
+
+ return cycles;
+}
+
+/****************************************************************************
+ * Handle I/O and timers
+ ****************************************************************************/
+
+void /*z180_device::*/handle_io_timers(int cycles)
+{
+ while (cycles-- > 0)
+ {
+ clock_timers();
+ }
+}
+
+/****************************************************************************
+ * Execute 'cycles' T-states. Return number of T-states really executed
+ ****************************************************************************/
+void /*z180_device::*/execute_run()
+{
+ int curcycles;
+
+ /* check for NMIs on the way in; they can only be set externally */
+ /* via timers, and can't be dynamically enabled, so it is safe */
+ /* to just check here */
+ if (m_nmi_pending)
+ {
+ LOG("Z180 take NMI\n");
+ LEAVE_HALT(); /* Check if processor was halted */
+
+ /* disable DMA transfers!! */
+ IO_DSTAT &= ~Z180_DSTAT_DME;
+
+ m_IFF2 = m_IFF1;
+ m_IFF1 = 0;
+ PUSH( PC );
+ _PCD = 0x0066;
+ m_icount -= 11;
+ m_nmi_pending = 0;
+ handle_io_timers(11);
+ }
+
+again:
+ /* check if any DMA transfer is running */
+ if ((IO_DSTAT & Z180_DSTAT_DME) == Z180_DSTAT_DME)
+ {
+ /* check if DMA channel 0 is running and also is in burst mode */
+ if ((IO_DSTAT & Z180_DSTAT_DE0) == Z180_DSTAT_DE0 &&
+ (IO_DMODE & Z180_DMODE_MMOD) == Z180_DMODE_MMOD)
+ {
+ debugger_instruction_hook(_PCD);
+
+ /* FIXME z180_dma0 should be handled in handle_io_timers */
+ curcycles = z180_dma0(m_icount);
+ m_icount -= curcycles;
+ handle_io_timers(curcycles);
+ }
+ else
+ {
+ do
+ {
+ curcycles = check_interrupts();
+ m_icount -= curcycles;
+ handle_io_timers(curcycles);
+ m_after_EI = 0;
+
+ _PPC = _PCD;
+ debugger_instruction_hook(_PCD);
+
+ if (!m_HALT)
+ {
+ m_R++;
+ IO_FRC++; /* Added FRC counting, not implemented yet */
+ m_extra_cycles = 0;
+ curcycles = exec_op(ROP());
+ curcycles += m_extra_cycles;
+ }
+ else
+ curcycles = 3;
+
+ m_icount -= curcycles;
+
+ handle_io_timers(curcycles);
+
+ /* if channel 0 was started in burst mode, go recheck the mode */
+ if ((IO_DSTAT & Z180_DSTAT_DE0) == Z180_DSTAT_DE0 &&
+ (IO_DMODE & Z180_DMODE_MMOD) == Z180_DMODE_MMOD)
+ goto again;
+
+ /* FIXME:
+ * For simultaneous DREQ0 and DREQ1 requests, channel 0 has priority
+ * over channel 1. When channel 0 is performing a memory to/from memory
+ * transfer, channel 1 cannot operate until the channel 0 operation has
+ * terminated. If channel 1 is operating, channel 0 cannot operate until
+ * channel 1 releases control of the bus.
+ *
+ */
+ curcycles = z180_dma0(6);
+ m_icount -= curcycles;
+ handle_io_timers(curcycles);
+
+ curcycles = z180_dma1();
+ m_icount -= curcycles;
+ handle_io_timers(curcycles);
+
+ /* If DMA is done break out to the faster loop */
+ if ((IO_DSTAT & Z180_DSTAT_DME) != Z180_DSTAT_DME)
+ break;
+ } while( m_icount > 0 );
+ }
+ }
+
+ if (m_icount > 0)
+ {
+ do
+ {
+ /* If DMA is started go to check the mode */
+ if ((IO_DSTAT & Z180_DSTAT_DME) == Z180_DSTAT_DME)
+ goto again;
+
+ curcycles = check_interrupts();
+ m_icount -= curcycles;
+ handle_io_timers(curcycles);
+ m_after_EI = 0;
+
+ _PPC = _PCD;
+ debugger_instruction_hook(_PCD);
+
+ if (!m_HALT)
+ {
+ m_R++;
+ IO_FRC++; /* Added FRC counting, not implemented yet */
+ m_extra_cycles = 0;
+ curcycles = exec_op(ROP());
+ curcycles += m_extra_cycles;
+ }
+ else
+ curcycles = 3;
+
+ m_icount -= curcycles;
+ handle_io_timers(curcycles);
+ } while( m_icount > 0 );
+ }
+}
+
+/****************************************************************************
+ * Burn 'cycles' T-states. Adjust R register for the lost time
+ ****************************************************************************/
+void /*z180_device::*/execute_burn(int32_t cycles)
+{
+ int extra_cycles = IO_DCNTL >> 6; // memory wait states
+
+ /* FIXME: This is not appropriate for dma */
+ while ( (cycles > 0) )
+ {
+ handle_io_timers(3 + extra_cycles);
+ /* NOP takes 3 cycles per instruction */
+ m_R += 1;
+ m_icount -= 3 + extra_cycles;
+ cycles -= 3 + extra_cycles;
+ }
+}
+
+/****************************************************************************
+ * Set IRQ line state
+ ****************************************************************************/
+void /*z180_device::*/execute_set_input(int irqline, int state)
+{
+ if (irqline == INPUT_LINE_NMI)
+ {
+ /* mark an NMI pending on the rising edge */
+ if (m_nmi_state == CLEAR_LINE && state != CLEAR_LINE)
+ m_nmi_pending = 1;
+ m_nmi_state = state;
+ }
+ else
+ {
+ LOG("Z180 set_irq_line %d = %d\n", irqline,state);
+
+ if(irqline == Z180_INPUT_LINE_IRQ0 || irqline == Z180_INPUT_LINE_IRQ1 || irqline == Z180_INPUT_LINE_IRQ2) {
+ /* update the IRQ state */
+ m_irq_state[irqline] = state;
+ if(daisy_chain_present())
+ m_irq_state[0] = daisy_update_irq_state();
+
+ /* the main execute loop will take the interrupt */
+ } else if(irqline == Z180_INPUT_LINE_DREQ0) {
+ uint32_t iol = m_iol & ~Z180_DREQ0;
+ if(state == ASSERT_LINE)
+ iol |= Z180_DREQ0;
+ z180_write_iolines(iol);
+ } else if(irqline == Z180_INPUT_LINE_DREQ1) {
+ uint32_t iol = m_iol & ~Z180_DREQ1;
+ if(state == ASSERT_LINE)
+ iol |= Z180_DREQ1;
+ z180_write_iolines(iol);
+ }
+ }
+}
+
+/* logical to physical address translation */
+//bool /*z180_device::*/memory_translate(int spacenum, int intention, offs_t &address)
+//{
+// if (spacenum == AS_PROGRAM)
+// {
+// address = MMU_REMAP_ADDR(address);
+// }
+// return true;
+//}
+
+
+/**************************************************************************
+ * STATE IMPORT/EXPORT
+ **************************************************************************/
+
+//void /*z180_device::*/state_import(const device_state_entry &entry)
+//{
+// switch (entry.index())
+// {
+// case Z180_R:
+// m_R = m_rtemp & 0x7f;
+// m_R2 = m_rtemp & 0x80;
+// break;
+//
+// case Z180_CBR:
+// case Z180_BBR:
+// case Z180_CBAR:
+// z180_mmu();
+// break;
+//
+// case Z180_IOLINES:
+// z180_write_iolines(m_ioltemp);
+// break;
+//
+// default:
+// fatalerror("CPU_IMPORT_STATE(z80) called for unexpected value\n");
+// }
+//}
+//
+//
+//void /*z180_device::*/state_export(const device_state_entry &entry)
+//{
+// switch (entry.index())
+// {
+// case Z180_R:
+// m_rtemp = (m_R & 0x7f) | (m_R2 & 0x80);
+// break;
+//
+// case Z180_IOLINES:
+// m_ioltemp = m_iol;
+// break;
+//
+// default:
+// fatalerror("CPU_EXPORT_STATE(z80) called for unexpected value\n");
+// }
+//}
+//
+//void /*z180_device::*/state_string_export(const device_state_entry &entry, std::string &str) const
+//{
+// switch (entry.index())
+// {
+// case STATE_GENFLAGS:
+// str = string_format("%c%c%c%c%c%c%c%c",
+// m_AF.b.l & 0x80 ? 'S':'.',
+// m_AF.b.l & 0x40 ? 'Z':'.',
+// m_AF.b.l & 0x20 ? '5':'.',
+// m_AF.b.l & 0x10 ? 'H':'.',
+// m_AF.b.l & 0x08 ? '3':'.',
+// m_AF.b.l & 0x04 ? 'P':'.',
+// m_AF.b.l & 0x02 ? 'N':'.',
+// m_AF.b.l & 0x01 ? 'C':'.');
+// break;
+// }
+//}
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+#ifndef MAME_CPU_Z180_Z180_H
+#define MAME_CPU_Z180_Z180_H
+
+//#pragma once
+
+//#include "machine/z80daisy.h"
+void daisy_call_reti_device(void);
+typedef struct device_z80daisy_interface {
+} device_z80daisy_interface;
+device_z80daisy_interface *daisy_get_irq_device(void);
+int intf_z80daisy_irq_ack(void);
+int standard_irq_callback_member(int arg);
+bool daisy_chain_present(void);
+int daisy_update_irq_state(void);
+
+
+enum
+{
+ Z180_PC,
+ Z180_SP,
+ Z180_AF,
+ Z180_BC,
+ Z180_DE,
+ Z180_HL,
+ Z180_IX,
+ Z180_IY,
+ Z180_A,
+ Z180_B,
+ Z180_C,
+ Z180_D,
+ Z180_E,
+ Z180_H,
+ Z180_L,
+ Z180_AF2,
+ Z180_BC2,
+ Z180_DE2,
+ Z180_HL2,
+ Z180_R,
+ Z180_I,
+ Z180_IM,
+ Z180_IFF1,
+ Z180_IFF2,
+ Z180_HALT,
+ Z180_DC0,
+ Z180_DC1,
+ Z180_DC2,
+ Z180_DC3,
+ Z180_CNTLA0, /* 00 ASCI control register A ch 0 */
+ Z180_CNTLA1, /* 01 ASCI control register A ch 1 */
+ Z180_CNTLB0, /* 02 ASCI control register B ch 0 */
+ Z180_CNTLB1, /* 03 ASCI control register B ch 1 */
+ Z180_STAT0, /* 04 ASCI status register 0 */
+ Z180_STAT1, /* 05 ASCI status register 1 */
+ Z180_TDR0, /* 06 ASCI transmit data register 0 */
+ Z180_TDR1, /* 07 ASCI transmit data register 1 */
+ Z180_RDR0, /* 08 ASCI receive data register 0 */
+ Z180_RDR1, /* 09 ASCI receive data register 1 */
+ Z180_CNTR, /* 0a CSI/O control/status register */
+ Z180_TRDR, /* 0b CSI/O transmit/receive register */
+ Z180_TMDR0L, /* 0c TIMER data register ch 0 L */
+ Z180_TMDR0H, /* 0d TIMER data register ch 0 H */
+ Z180_RLDR0L, /* 0e TIMER reload register ch 0 L */
+ Z180_RLDR0H, /* 0f TIMER reload register ch 0 H */
+ Z180_TCR, /* 10 TIMER control register */
+ Z180_IO11, /* 11 reserved */
+ Z180_ASEXT0, /* 12 (Z8S180/Z8L180) ASCI extension control register 0 */
+ Z180_ASEXT1, /* 13 (Z8S180/Z8L180) ASCI extension control register 0 */
+ Z180_TMDR1L, /* 14 TIMER data register ch 1 L */
+ Z180_TMDR1H, /* 15 TIMER data register ch 1 H */
+ Z180_RLDR1L, /* 16 TIMER reload register ch 1 L */
+ Z180_RLDR1H, /* 17 TIMER reload register ch 1 H */
+ Z180_FRC, /* 18 free running counter */
+ Z180_IO19, /* 19 reserved */
+ Z180_ASTC0L, /* 1a ASCI time constant ch 0 L */
+ Z180_ASTC0H, /* 1b ASCI time constant ch 0 H */
+ Z180_ASTC1L, /* 1c ASCI time constant ch 1 L */
+ Z180_ASTC1H, /* 1d ASCI time constant ch 1 H */
+ Z180_CMR, /* 1e clock multiplier */
+ Z180_CCR, /* 1f chip control register */
+ Z180_SAR0L, /* 20 DMA source address register ch 0 L */
+ Z180_SAR0H, /* 21 DMA source address register ch 0 H */
+ Z180_SAR0B, /* 22 DMA source address register ch 0 B */
+ Z180_DAR0L, /* 23 DMA destination address register ch 0 L */
+ Z180_DAR0H, /* 24 DMA destination address register ch 0 H */
+ Z180_DAR0B, /* 25 DMA destination address register ch 0 B */
+ Z180_BCR0L, /* 26 DMA byte count register ch 0 L */
+ Z180_BCR0H, /* 27 DMA byte count register ch 0 H */
+ Z180_MAR1L, /* 28 DMA memory address register ch 1 L */
+ Z180_MAR1H, /* 29 DMA memory address register ch 1 H */
+ Z180_MAR1B, /* 2a DMA memory address register ch 1 B */
+ Z180_IAR1L, /* 2b DMA I/O address register ch 1 L */
+ Z180_IAR1H, /* 2c DMA I/O address register ch 1 H */
+ Z180_IAR1B, /* 2d (Z8S180/Z8L180) DMA I/O address register ch 1 B */
+ Z180_BCR1L, /* 2e DMA byte count register ch 1 L */
+ Z180_BCR1H, /* 2f DMA byte count register ch 1 H */
+ Z180_DSTAT, /* 30 DMA status register */
+ Z180_DMODE, /* 31 DMA mode register */
+ Z180_DCNTL, /* 32 DMA/WAIT control register */
+ Z180_IL, /* 33 INT vector low register */
+ Z180_ITC, /* 34 INT/TRAP control register */
+ Z180_IO35, /* 35 reserved */
+ Z180_RCR, /* 36 refresh control register */
+ Z180_IO37, /* 37 reserved */
+ Z180_CBR, /* 38 MMU common base register */
+ Z180_BBR, /* 39 MMU bank base register */
+ Z180_CBAR, /* 3a MMU common/bank area register */
+ Z180_IO3B, /* 3b reserved */
+ Z180_IO3C, /* 3c reserved */
+ Z180_IO3D, /* 3d reserved */
+ Z180_OMCR, /* 3e operation mode control register */
+ Z180_IOCR, /* 3f I/O control register */
+ Z180_IOLINES /* read/write I/O lines */
+};
+
+enum
+{
+ Z180_TABLE_op,
+ Z180_TABLE_cb,
+ Z180_TABLE_ed,
+ Z180_TABLE_xy,
+ Z180_TABLE_xycb,
+ Z180_TABLE_ex /* cycles counts for taken jr/jp/call and interrupt latency (rst opcodes) */
+};
+
+// input lines
+enum {
+ Z180_INPUT_LINE_IRQ0, /* Execute IRQ1 */
+ Z180_INPUT_LINE_IRQ1, /* Execute IRQ1 */
+ Z180_INPUT_LINE_IRQ2, /* Execute IRQ2 */
+ Z180_INPUT_LINE_DREQ0, /* Start DMA0 */
+ Z180_INPUT_LINE_DREQ1 /* Start DMA1 */
+};
+
+//class z180_device : public cpu_device, public z80_daisy_chain_interface
+//{
+//public:
+// // construction/destruction
+// z180_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock);
+
+ bool get_tend0();
+ bool get_tend1();
+
+//protected:
+// // device-level overrides
+// virtual void device_start() override;
+// virtual void device_reset() override;
+//
+// // device_execute_interface overrides
+// virtual uint32_t execute_min_cycles() const override { return 1; }
+// virtual uint32_t execute_max_cycles() const override { return 16; }
+// virtual uint32_t execute_input_lines() const override { return 5; }
+// virtual uint32_t execute_default_irq_vector(int inputnum) const override { return 0xff; }
+// virtual bool execute_input_edge_triggered(int inputnum) const override { return inputnum == INPUT_LINE_NMI; }
+// virtual void execute_run() override;
+// virtual void execute_burn(int32_t cycles) override;
+// virtual void execute_set_input(int inputnum, int state) override;
+//
+// // device_memory_interface overrides
+// virtual space_config_vector memory_space_config() const override;
+// virtual bool memory_translate(int spacenum, int intention, offs_t &address) override;
+//
+// // device_state_interface overrides
+// virtual void state_import(const device_state_entry &entry) override;
+// virtual void state_export(const device_state_entry &entry) override;
+// virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
+//
+// // device_disasm_interface overrides
+// virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
+//
+//private:
+// address_space_config m_program_config;
+// address_space_config m_io_config;
+// address_space_config m_decrypted_opcodes_config;
+
+ PAIR m_PREPC,m_PC,m_SP,m_AF,m_BC,m_DE,m_HL,m_IX,m_IY;
+ PAIR m_AF2,m_BC2,m_DE2,m_HL2;
+ uint8_t m_R,m_R2,m_IFF1,m_IFF2,m_HALT,m_IM,m_I;
+ uint8_t m_tmdr_latch; /* flag latched TMDR0H, TMDR1H values */
+ uint8_t m_read_tcr_tmdr[2]; /* flag to indicate that TCR or TMDR was read */
+ uint32_t m_iol; /* I/O line status bits */
+ uint8_t m_io[64]; /* 64 internal 8 bit registers */
+ offs_t m_mmu[16]; /* MMU address translation */
+ uint8_t m_tmdrh[2]; /* latched TMDR0H and TMDR1H values */
+ uint16_t m_tmdr_value[2]; /* TMDR values used byt PRT0 and PRT1 as down counter */
+ uint8_t m_tif[2]; /* TIF0 and TIF1 values */
+ uint8_t m_nmi_state; /* nmi line state */
+ uint8_t m_nmi_pending; /* nmi pending */
+ uint8_t m_irq_state[3]; /* irq line states (INT0,INT1,INT2) */
+ uint8_t m_int_pending[11 + 1]; /* interrupt pending */
+ uint8_t m_after_EI; /* are we in the EI shadow? */
+ uint32_t m_ea;
+ uint8_t m_timer_cnt; /* timer counter / divide by 20 */
+ uint8_t m_dma0_cnt; /* dma0 counter / divide by 20 */
+ uint8_t m_dma1_cnt; /* dma1 counter / divide by 20 */
+// address_space *m_program;
+// memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_cache;
+// address_space *m_oprogram;
+// memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_ocache;
+// address_space *m_iospace;
+ uint8_t m_rtemp;
+ uint32_t m_ioltemp;
+ int m_icount;
+ int m_extra_cycles; /* extra cpu cycles */
+ uint8_t *m_cc[6];
+
+ typedef void (/*z180_device::*/*opcode_func)();
+// static const opcode_func s_z180ops[6][0x100];
+extern const /*z180_device::*/opcode_func /*z180_device::*/s_z180ops[/*Z180_PREFIX_COUNT*/6][0x100];
+
+ /*inline*/ void z180_mmu();
+ /*inline*/ u8 RM(offs_t addr);
+ /*inline*/ u8 IN(u16 port);
+ /*inline*/ void OUT(u16 port, u8 value);
+ /*inline*/ void RM16( offs_t addr, PAIR *r );
+ /*inline*/ void WM16( offs_t addr, PAIR *r );
+ /*inline*/ uint8_t ROP();
+ /*inline*/ uint8_t ARG();
+ /*inline*/ uint32_t ARG16();
+ /*inline*/ uint8_t INC(uint8_t value);
+ /*inline*/ uint8_t DEC(uint8_t value);
+ /*inline*/ uint8_t RLC(uint8_t value);
+ /*inline*/ uint8_t RRC(uint8_t value);
+ /*inline*/ uint8_t RL(uint8_t value);
+ /*inline*/ uint8_t RR(uint8_t value);
+ /*inline*/ uint8_t SLA(uint8_t value);
+ /*inline*/ uint8_t SRA(uint8_t value);
+ /*inline*/ uint8_t SLL(uint8_t value);
+ /*inline*/ uint8_t SRL(uint8_t value);
+ /*inline*/ uint8_t RES(uint8_t bit, uint8_t value);
+ /*inline*/ uint8_t SET(uint8_t bit, uint8_t value);
+ /*inline*/ int exec_op(const uint8_t opcode);
+ /*inline*/ int exec_cb(const uint8_t opcode);
+ /*inline*/ int exec_dd(const uint8_t opcode);
+ /*inline*/ int exec_ed(const uint8_t opcode);
+ /*inline*/ int exec_fd(const uint8_t opcode);
+ /*inline*/ int exec_xycb(const uint8_t opcode);
+ int take_interrupt(int irq);
+ uint8_t z180_readcontrol(offs_t port);
+ void z180_writecontrol(offs_t port, uint8_t data);
+ int z180_dma0(int max_cycles);
+ int z180_dma1();
+ void z180_write_iolines(uint32_t data);
+ void clock_timers();
+ int check_interrupts();
+ void handle_io_timers(int cycles);
+
+ void op_00();
+ void op_01();
+ void op_02();
+ void op_03();
+ void op_04();
+ void op_05();
+ void op_06();
+ void op_07();
+ void op_08();
+ void op_09();
+ void op_0a();
+ void op_0b();
+ void op_0c();
+ void op_0d();
+ void op_0e();
+ void op_0f();
+ void op_10();
+ void op_11();
+ void op_12();
+ void op_13();
+ void op_14();
+ void op_15();
+ void op_16();
+ void op_17();
+ void op_18();
+ void op_19();
+ void op_1a();
+ void op_1b();
+ void op_1c();
+ void op_1d();
+ void op_1e();
+ void op_1f();
+ void op_20();
+ void op_21();
+ void op_22();
+ void op_23();
+ void op_24();
+ void op_25();
+ void op_26();
+ void op_27();
+ void op_28();
+ void op_29();
+ void op_2a();
+ void op_2b();
+ void op_2c();
+ void op_2d();
+ void op_2e();
+ void op_2f();
+ void op_30();
+ void op_31();
+ void op_32();
+ void op_33();
+ void op_34();
+ void op_35();
+ void op_36();
+ void op_37();
+ void op_38();
+ void op_39();
+ void op_3a();
+ void op_3b();
+ void op_3c();
+ void op_3d();
+ void op_3e();
+ void op_3f();
+ void op_40();
+ void op_41();
+ void op_42();
+ void op_43();
+ void op_44();
+ void op_45();
+ void op_46();
+ void op_47();
+ void op_48();
+ void op_49();
+ void op_4a();
+ void op_4b();
+ void op_4c();
+ void op_4d();
+ void op_4e();
+ void op_4f();
+ void op_50();
+ void op_51();
+ void op_52();
+ void op_53();
+ void op_54();
+ void op_55();
+ void op_56();
+ void op_57();
+ void op_58();
+ void op_59();
+ void op_5a();
+ void op_5b();
+ void op_5c();
+ void op_5d();
+ void op_5e();
+ void op_5f();
+ void op_60();
+ void op_61();
+ void op_62();
+ void op_63();
+ void op_64();
+ void op_65();
+ void op_66();
+ void op_67();
+ void op_68();
+ void op_69();
+ void op_6a();
+ void op_6b();
+ void op_6c();
+ void op_6d();
+ void op_6e();
+ void op_6f();
+ void op_70();
+ void op_71();
+ void op_72();
+ void op_73();
+ void op_74();
+ void op_75();
+ void op_76();
+ void op_77();
+ void op_78();
+ void op_79();
+ void op_7a();
+ void op_7b();
+ void op_7c();
+ void op_7d();
+ void op_7e();
+ void op_7f();
+ void op_80();
+ void op_81();
+ void op_82();
+ void op_83();
+ void op_84();
+ void op_85();
+ void op_86();
+ void op_87();
+ void op_88();
+ void op_89();
+ void op_8a();
+ void op_8b();
+ void op_8c();
+ void op_8d();
+ void op_8e();
+ void op_8f();
+ void op_90();
+ void op_91();
+ void op_92();
+ void op_93();
+ void op_94();
+ void op_95();
+ void op_96();
+ void op_97();
+ void op_98();
+ void op_99();
+ void op_9a();
+ void op_9b();
+ void op_9c();
+ void op_9d();
+ void op_9e();
+ void op_9f();
+ void op_a0();
+ void op_a1();
+ void op_a2();
+ void op_a3();
+ void op_a4();
+ void op_a5();
+ void op_a6();
+ void op_a7();
+ void op_a8();
+ void op_a9();
+ void op_aa();
+ void op_ab();
+ void op_ac();
+ void op_ad();
+ void op_ae();
+ void op_af();
+ void op_b0();
+ void op_b1();
+ void op_b2();
+ void op_b3();
+ void op_b4();
+ void op_b5();
+ void op_b6();
+ void op_b7();
+ void op_b8();
+ void op_b9();
+ void op_ba();
+ void op_bb();
+ void op_bc();
+ void op_bd();
+ void op_be();
+ void op_bf();
+ void op_c0();
+ void op_c1();
+ void op_c2();
+ void op_c3();
+ void op_c4();
+ void op_c5();
+ void op_c6();
+ void op_c7();
+ void op_c8();
+ void op_c9();
+ void op_ca();
+ void op_cb();
+ void op_cc();
+ void op_cd();
+ void op_ce();
+ void op_cf();
+ void op_d0();
+ void op_d1();
+ void op_d2();
+ void op_d3();
+ void op_d4();
+ void op_d5();
+ void op_d6();
+ void op_d7();
+ void op_d8();
+ void op_d9();
+ void op_da();
+ void op_db();
+ void op_dc();
+ void op_dd();
+ void op_de();
+ void op_df();
+ void op_e0();
+ void op_e1();
+ void op_e2();
+ void op_e3();
+ void op_e4();
+ void op_e5();
+ void op_e6();
+ void op_e7();
+ void op_e8();
+ void op_e9();
+ void op_ea();
+ void op_eb();
+ void op_ec();
+ void op_ed();
+ void op_ee();
+ void op_ef();
+ void op_f0();
+ void op_f1();
+ void op_f2();
+ void op_f3();
+ void op_f4();
+ void op_f5();
+ void op_f6();
+ void op_f7();
+ void op_f8();
+ void op_f9();
+ void op_fa();
+ void op_fb();
+ void op_fc();
+ void op_fd();
+ void op_fe();
+ void op_ff();
+ void cb_00();
+ void cb_01();
+ void cb_02();
+ void cb_03();
+ void cb_04();
+ void cb_05();
+ void cb_06();
+ void cb_07();
+ void cb_08();
+ void cb_09();
+ void cb_0a();
+ void cb_0b();
+ void cb_0c();
+ void cb_0d();
+ void cb_0e();
+ void cb_0f();
+ void cb_10();
+ void cb_11();
+ void cb_12();
+ void cb_13();
+ void cb_14();
+ void cb_15();
+ void cb_16();
+ void cb_17();
+ void cb_18();
+ void cb_19();
+ void cb_1a();
+ void cb_1b();
+ void cb_1c();
+ void cb_1d();
+ void cb_1e();
+ void cb_1f();
+ void cb_20();
+ void cb_21();
+ void cb_22();
+ void cb_23();
+ void cb_24();
+ void cb_25();
+ void cb_26();
+ void cb_27();
+ void cb_28();
+ void cb_29();
+ void cb_2a();
+ void cb_2b();
+ void cb_2c();
+ void cb_2d();
+ void cb_2e();
+ void cb_2f();
+ void cb_30();
+ void cb_31();
+ void cb_32();
+ void cb_33();
+ void cb_34();
+ void cb_35();
+ void cb_36();
+ void cb_37();
+ void cb_38();
+ void cb_39();
+ void cb_3a();
+ void cb_3b();
+ void cb_3c();
+ void cb_3d();
+ void cb_3e();
+ void cb_3f();
+ void cb_40();
+ void cb_41();
+ void cb_42();
+ void cb_43();
+ void cb_44();
+ void cb_45();
+ void cb_46();
+ void cb_47();
+ void cb_48();
+ void cb_49();
+ void cb_4a();
+ void cb_4b();
+ void cb_4c();
+ void cb_4d();
+ void cb_4e();
+ void cb_4f();
+ void cb_50();
+ void cb_51();
+ void cb_52();
+ void cb_53();
+ void cb_54();
+ void cb_55();
+ void cb_56();
+ void cb_57();
+ void cb_58();
+ void cb_59();
+ void cb_5a();
+ void cb_5b();
+ void cb_5c();
+ void cb_5d();
+ void cb_5e();
+ void cb_5f();
+ void cb_60();
+ void cb_61();
+ void cb_62();
+ void cb_63();
+ void cb_64();
+ void cb_65();
+ void cb_66();
+ void cb_67();
+ void cb_68();
+ void cb_69();
+ void cb_6a();
+ void cb_6b();
+ void cb_6c();
+ void cb_6d();
+ void cb_6e();
+ void cb_6f();
+ void cb_70();
+ void cb_71();
+ void cb_72();
+ void cb_73();
+ void cb_74();
+ void cb_75();
+ void cb_76();
+ void cb_77();
+ void cb_78();
+ void cb_79();
+ void cb_7a();
+ void cb_7b();
+ void cb_7c();
+ void cb_7d();
+ void cb_7e();
+ void cb_7f();
+ void cb_80();
+ void cb_81();
+ void cb_82();
+ void cb_83();
+ void cb_84();
+ void cb_85();
+ void cb_86();
+ void cb_87();
+ void cb_88();
+ void cb_89();
+ void cb_8a();
+ void cb_8b();
+ void cb_8c();
+ void cb_8d();
+ void cb_8e();
+ void cb_8f();
+ void cb_90();
+ void cb_91();
+ void cb_92();
+ void cb_93();
+ void cb_94();
+ void cb_95();
+ void cb_96();
+ void cb_97();
+ void cb_98();
+ void cb_99();
+ void cb_9a();
+ void cb_9b();
+ void cb_9c();
+ void cb_9d();
+ void cb_9e();
+ void cb_9f();
+ void cb_a0();
+ void cb_a1();
+ void cb_a2();
+ void cb_a3();
+ void cb_a4();
+ void cb_a5();
+ void cb_a6();
+ void cb_a7();
+ void cb_a8();
+ void cb_a9();
+ void cb_aa();
+ void cb_ab();
+ void cb_ac();
+ void cb_ad();
+ void cb_ae();
+ void cb_af();
+ void cb_b0();
+ void cb_b1();
+ void cb_b2();
+ void cb_b3();
+ void cb_b4();
+ void cb_b5();
+ void cb_b6();
+ void cb_b7();
+ void cb_b8();
+ void cb_b9();
+ void cb_ba();
+ void cb_bb();
+ void cb_bc();
+ void cb_bd();
+ void cb_be();
+ void cb_bf();
+ void cb_c0();
+ void cb_c1();
+ void cb_c2();
+ void cb_c3();
+ void cb_c4();
+ void cb_c5();
+ void cb_c6();
+ void cb_c7();
+ void cb_c8();
+ void cb_c9();
+ void cb_ca();
+ void cb_cb();
+ void cb_cc();
+ void cb_cd();
+ void cb_ce();
+ void cb_cf();
+ void cb_d0();
+ void cb_d1();
+ void cb_d2();
+ void cb_d3();
+ void cb_d4();
+ void cb_d5();
+ void cb_d6();
+ void cb_d7();
+ void cb_d8();
+ void cb_d9();
+ void cb_da();
+ void cb_db();
+ void cb_dc();
+ void cb_dd();
+ void cb_de();
+ void cb_df();
+ void cb_e0();
+ void cb_e1();
+ void cb_e2();
+ void cb_e3();
+ void cb_e4();
+ void cb_e5();
+ void cb_e6();
+ void cb_e7();
+ void cb_e8();
+ void cb_e9();
+ void cb_ea();
+ void cb_eb();
+ void cb_ec();
+ void cb_ed();
+ void cb_ee();
+ void cb_ef();
+ void cb_f0();
+ void cb_f1();
+ void cb_f2();
+ void cb_f3();
+ void cb_f4();
+ void cb_f5();
+ void cb_f6();
+ void cb_f7();
+ void cb_f8();
+ void cb_f9();
+ void cb_fa();
+ void cb_fb();
+ void cb_fc();
+ void cb_fd();
+ void cb_fe();
+ void cb_ff();
+ void illegal_1();
+ void dd_00();
+ void dd_01();
+ void dd_02();
+ void dd_03();
+ void dd_04();
+ void dd_05();
+ void dd_06();
+ void dd_07();
+ void dd_08();
+ void dd_09();
+ void dd_0a();
+ void dd_0b();
+ void dd_0c();
+ void dd_0d();
+ void dd_0e();
+ void dd_0f();
+ void dd_10();
+ void dd_11();
+ void dd_12();
+ void dd_13();
+ void dd_14();
+ void dd_15();
+ void dd_16();
+ void dd_17();
+ void dd_18();
+ void dd_19();
+ void dd_1a();
+ void dd_1b();
+ void dd_1c();
+ void dd_1d();
+ void dd_1e();
+ void dd_1f();
+ void dd_20();
+ void dd_21();
+ void dd_22();
+ void dd_23();
+ void dd_24();
+ void dd_25();
+ void dd_26();
+ void dd_27();
+ void dd_28();
+ void dd_29();
+ void dd_2a();
+ void dd_2b();
+ void dd_2c();
+ void dd_2d();
+ void dd_2e();
+ void dd_2f();
+ void dd_30();
+ void dd_31();
+ void dd_32();
+ void dd_33();
+ void dd_34();
+ void dd_35();
+ void dd_36();
+ void dd_37();
+ void dd_38();
+ void dd_39();
+ void dd_3a();
+ void dd_3b();
+ void dd_3c();
+ void dd_3d();
+ void dd_3e();
+ void dd_3f();
+ void dd_40();
+ void dd_41();
+ void dd_42();
+ void dd_43();
+ void dd_44();
+ void dd_45();
+ void dd_46();
+ void dd_47();
+ void dd_48();
+ void dd_49();
+ void dd_4a();
+ void dd_4b();
+ void dd_4c();
+ void dd_4d();
+ void dd_4e();
+ void dd_4f();
+ void dd_50();
+ void dd_51();
+ void dd_52();
+ void dd_53();
+ void dd_54();
+ void dd_55();
+ void dd_56();
+ void dd_57();
+ void dd_58();
+ void dd_59();
+ void dd_5a();
+ void dd_5b();
+ void dd_5c();
+ void dd_5d();
+ void dd_5e();
+ void dd_5f();
+ void dd_60();
+ void dd_61();
+ void dd_62();
+ void dd_63();
+ void dd_64();
+ void dd_65();
+ void dd_66();
+ void dd_67();
+ void dd_68();
+ void dd_69();
+ void dd_6a();
+ void dd_6b();
+ void dd_6c();
+ void dd_6d();
+ void dd_6e();
+ void dd_6f();
+ void dd_70();
+ void dd_71();
+ void dd_72();
+ void dd_73();
+ void dd_74();
+ void dd_75();
+ void dd_76();
+ void dd_77();
+ void dd_78();
+ void dd_79();
+ void dd_7a();
+ void dd_7b();
+ void dd_7c();
+ void dd_7d();
+ void dd_7e();
+ void dd_7f();
+ void dd_80();
+ void dd_81();
+ void dd_82();
+ void dd_83();
+ void dd_84();
+ void dd_85();
+ void dd_86();
+ void dd_87();
+ void dd_88();
+ void dd_89();
+ void dd_8a();
+ void dd_8b();
+ void dd_8c();
+ void dd_8d();
+ void dd_8e();
+ void dd_8f();
+ void dd_90();
+ void dd_91();
+ void dd_92();
+ void dd_93();
+ void dd_94();
+ void dd_95();
+ void dd_96();
+ void dd_97();
+ void dd_98();
+ void dd_99();
+ void dd_9a();
+ void dd_9b();
+ void dd_9c();
+ void dd_9d();
+ void dd_9e();
+ void dd_9f();
+ void dd_a0();
+ void dd_a1();
+ void dd_a2();
+ void dd_a3();
+ void dd_a4();
+ void dd_a5();
+ void dd_a6();
+ void dd_a7();
+ void dd_a8();
+ void dd_a9();
+ void dd_aa();
+ void dd_ab();
+ void dd_ac();
+ void dd_ad();
+ void dd_ae();
+ void dd_af();
+ void dd_b0();
+ void dd_b1();
+ void dd_b2();
+ void dd_b3();
+ void dd_b4();
+ void dd_b5();
+ void dd_b6();
+ void dd_b7();
+ void dd_b8();
+ void dd_b9();
+ void dd_ba();
+ void dd_bb();
+ void dd_bc();
+ void dd_bd();
+ void dd_be();
+ void dd_bf();
+ void dd_c0();
+ void dd_c1();
+ void dd_c2();
+ void dd_c3();
+ void dd_c4();
+ void dd_c5();
+ void dd_c6();
+ void dd_c7();
+ void dd_c8();
+ void dd_c9();
+ void dd_ca();
+ void dd_cb();
+ void dd_cc();
+ void dd_cd();
+ void dd_ce();
+ void dd_cf();
+ void dd_d0();
+ void dd_d1();
+ void dd_d2();
+ void dd_d3();
+ void dd_d4();
+ void dd_d5();
+ void dd_d6();
+ void dd_d7();
+ void dd_d8();
+ void dd_d9();
+ void dd_da();
+ void dd_db();
+ void dd_dc();
+ void dd_dd();
+ void dd_de();
+ void dd_df();
+ void dd_e0();
+ void dd_e1();
+ void dd_e2();
+ void dd_e3();
+ void dd_e4();
+ void dd_e5();
+ void dd_e6();
+ void dd_e7();
+ void dd_e8();
+ void dd_e9();
+ void dd_ea();
+ void dd_eb();
+ void dd_ec();
+ void dd_ed();
+ void dd_ee();
+ void dd_ef();
+ void dd_f0();
+ void dd_f1();
+ void dd_f2();
+ void dd_f3();
+ void dd_f4();
+ void dd_f5();
+ void dd_f6();
+ void dd_f7();
+ void dd_f8();
+ void dd_f9();
+ void dd_fa();
+ void dd_fb();
+ void dd_fc();
+ void dd_fd();
+ void dd_fe();
+ void dd_ff();
+ void illegal_2();
+ void ed_00();
+ void ed_01();
+ void ed_02();
+ void ed_03();
+ void ed_04();
+ void ed_05();
+ void ed_06();
+ void ed_07();
+ void ed_08();
+ void ed_09();
+ void ed_0a();
+ void ed_0b();
+ void ed_0c();
+ void ed_0d();
+ void ed_0e();
+ void ed_0f();
+ void ed_10();
+ void ed_11();
+ void ed_12();
+ void ed_13();
+ void ed_14();
+ void ed_15();
+ void ed_16();
+ void ed_17();
+ void ed_18();
+ void ed_19();
+ void ed_1a();
+ void ed_1b();
+ void ed_1c();
+ void ed_1d();
+ void ed_1e();
+ void ed_1f();
+ void ed_20();
+ void ed_21();
+ void ed_22();
+ void ed_23();
+ void ed_24();
+ void ed_25();
+ void ed_26();
+ void ed_27();
+ void ed_28();
+ void ed_29();
+ void ed_2a();
+ void ed_2b();
+ void ed_2c();
+ void ed_2d();
+ void ed_2e();
+ void ed_2f();
+ void ed_30();
+ void ed_31();
+ void ed_32();
+ void ed_33();
+ void ed_34();
+ void ed_35();
+ void ed_36();
+ void ed_37();
+ void ed_38();
+ void ed_39();
+ void ed_3a();
+ void ed_3b();
+ void ed_3c();
+ void ed_3d();
+ void ed_3e();
+ void ed_3f();
+ void ed_40();
+ void ed_41();
+ void ed_42();
+ void ed_43();
+ void ed_44();
+ void ed_45();
+ void ed_46();
+ void ed_47();
+ void ed_48();
+ void ed_49();
+ void ed_4a();
+ void ed_4b();
+ void ed_4c();
+ void ed_4d();
+ void ed_4e();
+ void ed_4f();
+ void ed_50();
+ void ed_51();
+ void ed_52();
+ void ed_53();
+ void ed_54();
+ void ed_55();
+ void ed_56();
+ void ed_57();
+ void ed_58();
+ void ed_59();
+ void ed_5a();
+ void ed_5b();
+ void ed_5c();
+ void ed_5d();
+ void ed_5e();
+ void ed_5f();
+ void ed_60();
+ void ed_61();
+ void ed_62();
+ void ed_63();
+ void ed_64();
+ void ed_65();
+ void ed_66();
+ void ed_67();
+ void ed_68();
+ void ed_69();
+ void ed_6a();
+ void ed_6b();
+ void ed_6c();
+ void ed_6d();
+ void ed_6e();
+ void ed_6f();
+ void ed_70();
+ void ed_71();
+ void ed_72();
+ void ed_73();
+ void ed_74();
+ void ed_75();
+ void ed_76();
+ void ed_77();
+ void ed_78();
+ void ed_79();
+ void ed_7a();
+ void ed_7b();
+ void ed_7c();
+ void ed_7d();
+ void ed_7e();
+ void ed_7f();
+ void ed_80();
+ void ed_81();
+ void ed_82();
+ void ed_83();
+ void ed_84();
+ void ed_85();
+ void ed_86();
+ void ed_87();
+ void ed_88();
+ void ed_89();
+ void ed_8a();
+ void ed_8b();
+ void ed_8c();
+ void ed_8d();
+ void ed_8e();
+ void ed_8f();
+ void ed_90();
+ void ed_91();
+ void ed_92();
+ void ed_93();
+ void ed_94();
+ void ed_95();
+ void ed_96();
+ void ed_97();
+ void ed_98();
+ void ed_99();
+ void ed_9a();
+ void ed_9b();
+ void ed_9c();
+ void ed_9d();
+ void ed_9e();
+ void ed_9f();
+ void ed_a0();
+ void ed_a1();
+ void ed_a2();
+ void ed_a3();
+ void ed_a4();
+ void ed_a5();
+ void ed_a6();
+ void ed_a7();
+ void ed_a8();
+ void ed_a9();
+ void ed_aa();
+ void ed_ab();
+ void ed_ac();
+ void ed_ad();
+ void ed_ae();
+ void ed_af();
+ void ed_b0();
+ void ed_b1();
+ void ed_b2();
+ void ed_b3();
+ void ed_b4();
+ void ed_b5();
+ void ed_b6();
+ void ed_b7();
+ void ed_b8();
+ void ed_b9();
+ void ed_ba();
+ void ed_bb();
+ void ed_bc();
+ void ed_bd();
+ void ed_be();
+ void ed_bf();
+ void ed_c0();
+ void ed_c1();
+ void ed_c2();
+ void ed_c3();
+ void ed_c4();
+ void ed_c5();
+ void ed_c6();
+ void ed_c7();
+ void ed_c8();
+ void ed_c9();
+ void ed_ca();
+ void ed_cb();
+ void ed_cc();
+ void ed_cd();
+ void ed_ce();
+ void ed_cf();
+ void ed_d0();
+ void ed_d1();
+ void ed_d2();
+ void ed_d3();
+ void ed_d4();
+ void ed_d5();
+ void ed_d6();
+ void ed_d7();
+ void ed_d8();
+ void ed_d9();
+ void ed_da();
+ void ed_db();
+ void ed_dc();
+ void ed_dd();
+ void ed_de();
+ void ed_df();
+ void ed_e0();
+ void ed_e1();
+ void ed_e2();
+ void ed_e3();
+ void ed_e4();
+ void ed_e5();
+ void ed_e6();
+ void ed_e7();
+ void ed_e8();
+ void ed_e9();
+ void ed_ea();
+ void ed_eb();
+ void ed_ec();
+ void ed_ed();
+ void ed_ee();
+ void ed_ef();
+ void ed_f0();
+ void ed_f1();
+ void ed_f2();
+ void ed_f3();
+ void ed_f4();
+ void ed_f5();
+ void ed_f6();
+ void ed_f7();
+ void ed_f8();
+ void ed_f9();
+ void ed_fa();
+ void ed_fb();
+ void ed_fc();
+ void ed_fd();
+ void ed_fe();
+ void ed_ff();
+ void fd_00();
+ void fd_01();
+ void fd_02();
+ void fd_03();
+ void fd_04();
+ void fd_05();
+ void fd_06();
+ void fd_07();
+ void fd_08();
+ void fd_09();
+ void fd_0a();
+ void fd_0b();
+ void fd_0c();
+ void fd_0d();
+ void fd_0e();
+ void fd_0f();
+ void fd_10();
+ void fd_11();
+ void fd_12();
+ void fd_13();
+ void fd_14();
+ void fd_15();
+ void fd_16();
+ void fd_17();
+ void fd_18();
+ void fd_19();
+ void fd_1a();
+ void fd_1b();
+ void fd_1c();
+ void fd_1d();
+ void fd_1e();
+ void fd_1f();
+ void fd_20();
+ void fd_21();
+ void fd_22();
+ void fd_23();
+ void fd_24();
+ void fd_25();
+ void fd_26();
+ void fd_27();
+ void fd_28();
+ void fd_29();
+ void fd_2a();
+ void fd_2b();
+ void fd_2c();
+ void fd_2d();
+ void fd_2e();
+ void fd_2f();
+ void fd_30();
+ void fd_31();
+ void fd_32();
+ void fd_33();
+ void fd_34();
+ void fd_35();
+ void fd_36();
+ void fd_37();
+ void fd_38();
+ void fd_39();
+ void fd_3a();
+ void fd_3b();
+ void fd_3c();
+ void fd_3d();
+ void fd_3e();
+ void fd_3f();
+ void fd_40();
+ void fd_41();
+ void fd_42();
+ void fd_43();
+ void fd_44();
+ void fd_45();
+ void fd_46();
+ void fd_47();
+ void fd_48();
+ void fd_49();
+ void fd_4a();
+ void fd_4b();
+ void fd_4c();
+ void fd_4d();
+ void fd_4e();
+ void fd_4f();
+ void fd_50();
+ void fd_51();
+ void fd_52();
+ void fd_53();
+ void fd_54();
+ void fd_55();
+ void fd_56();
+ void fd_57();
+ void fd_58();
+ void fd_59();
+ void fd_5a();
+ void fd_5b();
+ void fd_5c();
+ void fd_5d();
+ void fd_5e();
+ void fd_5f();
+ void fd_60();
+ void fd_61();
+ void fd_62();
+ void fd_63();
+ void fd_64();
+ void fd_65();
+ void fd_66();
+ void fd_67();
+ void fd_68();
+ void fd_69();
+ void fd_6a();
+ void fd_6b();
+ void fd_6c();
+ void fd_6d();
+ void fd_6e();
+ void fd_6f();
+ void fd_70();
+ void fd_71();
+ void fd_72();
+ void fd_73();
+ void fd_74();
+ void fd_75();
+ void fd_76();
+ void fd_77();
+ void fd_78();
+ void fd_79();
+ void fd_7a();
+ void fd_7b();
+ void fd_7c();
+ void fd_7d();
+ void fd_7e();
+ void fd_7f();
+ void fd_80();
+ void fd_81();
+ void fd_82();
+ void fd_83();
+ void fd_84();
+ void fd_85();
+ void fd_86();
+ void fd_87();
+ void fd_88();
+ void fd_89();
+ void fd_8a();
+ void fd_8b();
+ void fd_8c();
+ void fd_8d();
+ void fd_8e();
+ void fd_8f();
+ void fd_90();
+ void fd_91();
+ void fd_92();
+ void fd_93();
+ void fd_94();
+ void fd_95();
+ void fd_96();
+ void fd_97();
+ void fd_98();
+ void fd_99();
+ void fd_9a();
+ void fd_9b();
+ void fd_9c();
+ void fd_9d();
+ void fd_9e();
+ void fd_9f();
+ void fd_a0();
+ void fd_a1();
+ void fd_a2();
+ void fd_a3();
+ void fd_a4();
+ void fd_a5();
+ void fd_a6();
+ void fd_a7();
+ void fd_a8();
+ void fd_a9();
+ void fd_aa();
+ void fd_ab();
+ void fd_ac();
+ void fd_ad();
+ void fd_ae();
+ void fd_af();
+ void fd_b0();
+ void fd_b1();
+ void fd_b2();
+ void fd_b3();
+ void fd_b4();
+ void fd_b5();
+ void fd_b6();
+ void fd_b7();
+ void fd_b8();
+ void fd_b9();
+ void fd_ba();
+ void fd_bb();
+ void fd_bc();
+ void fd_bd();
+ void fd_be();
+ void fd_bf();
+ void fd_c0();
+ void fd_c1();
+ void fd_c2();
+ void fd_c3();
+ void fd_c4();
+ void fd_c5();
+ void fd_c6();
+ void fd_c7();
+ void fd_c8();
+ void fd_c9();
+ void fd_ca();
+ void fd_cb();
+ void fd_cc();
+ void fd_cd();
+ void fd_ce();
+ void fd_cf();
+ void fd_d0();
+ void fd_d1();
+ void fd_d2();
+ void fd_d3();
+ void fd_d4();
+ void fd_d5();
+ void fd_d6();
+ void fd_d7();
+ void fd_d8();
+ void fd_d9();
+ void fd_da();
+ void fd_db();
+ void fd_dc();
+ void fd_dd();
+ void fd_de();
+ void fd_df();
+ void fd_e0();
+ void fd_e1();
+ void fd_e2();
+ void fd_e3();
+ void fd_e4();
+ void fd_e5();
+ void fd_e6();
+ void fd_e7();
+ void fd_e8();
+ void fd_e9();
+ void fd_ea();
+ void fd_eb();
+ void fd_ec();
+ void fd_ed();
+ void fd_ee();
+ void fd_ef();
+ void fd_f0();
+ void fd_f1();
+ void fd_f2();
+ void fd_f3();
+ void fd_f4();
+ void fd_f5();
+ void fd_f6();
+ void fd_f7();
+ void fd_f8();
+ void fd_f9();
+ void fd_fa();
+ void fd_fb();
+ void fd_fc();
+ void fd_fd();
+ void fd_fe();
+ void fd_ff();
+ void xycb_00();
+ void xycb_01();
+ void xycb_02();
+ void xycb_03();
+ void xycb_04();
+ void xycb_05();
+ void xycb_06();
+ void xycb_07();
+ void xycb_08();
+ void xycb_09();
+ void xycb_0a();
+ void xycb_0b();
+ void xycb_0c();
+ void xycb_0d();
+ void xycb_0e();
+ void xycb_0f();
+ void xycb_10();
+ void xycb_11();
+ void xycb_12();
+ void xycb_13();
+ void xycb_14();
+ void xycb_15();
+ void xycb_16();
+ void xycb_17();
+ void xycb_18();
+ void xycb_19();
+ void xycb_1a();
+ void xycb_1b();
+ void xycb_1c();
+ void xycb_1d();
+ void xycb_1e();
+ void xycb_1f();
+ void xycb_20();
+ void xycb_21();
+ void xycb_22();
+ void xycb_23();
+ void xycb_24();
+ void xycb_25();
+ void xycb_26();
+ void xycb_27();
+ void xycb_28();
+ void xycb_29();
+ void xycb_2a();
+ void xycb_2b();
+ void xycb_2c();
+ void xycb_2d();
+ void xycb_2e();
+ void xycb_2f();
+ void xycb_30();
+ void xycb_31();
+ void xycb_32();
+ void xycb_33();
+ void xycb_34();
+ void xycb_35();
+ void xycb_36();
+ void xycb_37();
+ void xycb_38();
+ void xycb_39();
+ void xycb_3a();
+ void xycb_3b();
+ void xycb_3c();
+ void xycb_3d();
+ void xycb_3e();
+ void xycb_3f();
+ void xycb_40();
+ void xycb_41();
+ void xycb_42();
+ void xycb_43();
+ void xycb_44();
+ void xycb_45();
+ void xycb_46();
+ void xycb_47();
+ void xycb_48();
+ void xycb_49();
+ void xycb_4a();
+ void xycb_4b();
+ void xycb_4c();
+ void xycb_4d();
+ void xycb_4e();
+ void xycb_4f();
+ void xycb_50();
+ void xycb_51();
+ void xycb_52();
+ void xycb_53();
+ void xycb_54();
+ void xycb_55();
+ void xycb_56();
+ void xycb_57();
+ void xycb_58();
+ void xycb_59();
+ void xycb_5a();
+ void xycb_5b();
+ void xycb_5c();
+ void xycb_5d();
+ void xycb_5e();
+ void xycb_5f();
+ void xycb_60();
+ void xycb_61();
+ void xycb_62();
+ void xycb_63();
+ void xycb_64();
+ void xycb_65();
+ void xycb_66();
+ void xycb_67();
+ void xycb_68();
+ void xycb_69();
+ void xycb_6a();
+ void xycb_6b();
+ void xycb_6c();
+ void xycb_6d();
+ void xycb_6e();
+ void xycb_6f();
+ void xycb_70();
+ void xycb_71();
+ void xycb_72();
+ void xycb_73();
+ void xycb_74();
+ void xycb_75();
+ void xycb_76();
+ void xycb_77();
+ void xycb_78();
+ void xycb_79();
+ void xycb_7a();
+ void xycb_7b();
+ void xycb_7c();
+ void xycb_7d();
+ void xycb_7e();
+ void xycb_7f();
+ void xycb_80();
+ void xycb_81();
+ void xycb_82();
+ void xycb_83();
+ void xycb_84();
+ void xycb_85();
+ void xycb_86();
+ void xycb_87();
+ void xycb_88();
+ void xycb_89();
+ void xycb_8a();
+ void xycb_8b();
+ void xycb_8c();
+ void xycb_8d();
+ void xycb_8e();
+ void xycb_8f();
+ void xycb_90();
+ void xycb_91();
+ void xycb_92();
+ void xycb_93();
+ void xycb_94();
+ void xycb_95();
+ void xycb_96();
+ void xycb_97();
+ void xycb_98();
+ void xycb_99();
+ void xycb_9a();
+ void xycb_9b();
+ void xycb_9c();
+ void xycb_9d();
+ void xycb_9e();
+ void xycb_9f();
+ void xycb_a0();
+ void xycb_a1();
+ void xycb_a2();
+ void xycb_a3();
+ void xycb_a4();
+ void xycb_a5();
+ void xycb_a6();
+ void xycb_a7();
+ void xycb_a8();
+ void xycb_a9();
+ void xycb_aa();
+ void xycb_ab();
+ void xycb_ac();
+ void xycb_ad();
+ void xycb_ae();
+ void xycb_af();
+ void xycb_b0();
+ void xycb_b1();
+ void xycb_b2();
+ void xycb_b3();
+ void xycb_b4();
+ void xycb_b5();
+ void xycb_b6();
+ void xycb_b7();
+ void xycb_b8();
+ void xycb_b9();
+ void xycb_ba();
+ void xycb_bb();
+ void xycb_bc();
+ void xycb_bd();
+ void xycb_be();
+ void xycb_bf();
+ void xycb_c0();
+ void xycb_c1();
+ void xycb_c2();
+ void xycb_c3();
+ void xycb_c4();
+ void xycb_c5();
+ void xycb_c6();
+ void xycb_c7();
+ void xycb_c8();
+ void xycb_c9();
+ void xycb_ca();
+ void xycb_cb();
+ void xycb_cc();
+ void xycb_cd();
+ void xycb_ce();
+ void xycb_cf();
+ void xycb_d0();
+ void xycb_d1();
+ void xycb_d2();
+ void xycb_d3();
+ void xycb_d4();
+ void xycb_d5();
+ void xycb_d6();
+ void xycb_d7();
+ void xycb_d8();
+ void xycb_d9();
+ void xycb_da();
+ void xycb_db();
+ void xycb_dc();
+ void xycb_dd();
+ void xycb_de();
+ void xycb_df();
+ void xycb_e0();
+ void xycb_e1();
+ void xycb_e2();
+ void xycb_e3();
+ void xycb_e4();
+ void xycb_e5();
+ void xycb_e6();
+ void xycb_e7();
+ void xycb_e8();
+ void xycb_e9();
+ void xycb_ea();
+ void xycb_eb();
+ void xycb_ec();
+ void xycb_ed();
+ void xycb_ee();
+ void xycb_ef();
+ void xycb_f0();
+ void xycb_f1();
+ void xycb_f2();
+ void xycb_f3();
+ void xycb_f4();
+ void xycb_f5();
+ void xycb_f6();
+ void xycb_f7();
+ void xycb_f8();
+ void xycb_f9();
+ void xycb_fa();
+ void xycb_fb();
+ void xycb_fc();
+ void xycb_fd();
+ void xycb_fe();
+ void xycb_ff();
+//};
+
+
+//DECLARE_DEVICE_TYPE(Z180, z180_device)
+
+#endif // MAME_CPU_Z180_Z180_H
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+/**********************************************************
+ * opcodes with CB prefix
+ * rotate, shift and bit operations
+ **********************************************************/
+OP(cb,00) { _B = RLC(_B); } /* RLC B */
+OP(cb,01) { _C = RLC(_C); } /* RLC C */
+OP(cb,02) { _D = RLC(_D); } /* RLC D */
+OP(cb,03) { _E = RLC(_E); } /* RLC E */
+OP(cb,04) { _H = RLC(_H); } /* RLC H */
+OP(cb,05) { _L = RLC(_L); } /* RLC L */
+OP(cb,06) { WM( _HL, RLC(RM(_HL)) ); } /* RLC (HL) */
+OP(cb,07) { _A = RLC(_A); } /* RLC A */
+
+OP(cb,08) { _B = RRC(_B); } /* RRC B */
+OP(cb,09) { _C = RRC(_C); } /* RRC C */
+OP(cb,0a) { _D = RRC(_D); } /* RRC D */
+OP(cb,0b) { _E = RRC(_E); } /* RRC E */
+OP(cb,0c) { _H = RRC(_H); } /* RRC H */
+OP(cb,0d) { _L = RRC(_L); } /* RRC L */
+OP(cb,0e) { WM( _HL, RRC(RM(_HL)) ); } /* RRC (HL) */
+OP(cb,0f) { _A = RRC(_A); } /* RRC A */
+
+OP(cb,10) { _B = RL(_B); } /* RL B */
+OP(cb,11) { _C = RL(_C); } /* RL C */
+OP(cb,12) { _D = RL(_D); } /* RL D */
+OP(cb,13) { _E = RL(_E); } /* RL E */
+OP(cb,14) { _H = RL(_H); } /* RL H */
+OP(cb,15) { _L = RL(_L); } /* RL L */
+OP(cb,16) { WM( _HL, RL(RM(_HL)) ); } /* RL (HL) */
+OP(cb,17) { _A = RL(_A); } /* RL A */
+
+OP(cb,18) { _B = RR(_B); } /* RR B */
+OP(cb,19) { _C = RR(_C); } /* RR C */
+OP(cb,1a) { _D = RR(_D); } /* RR D */
+OP(cb,1b) { _E = RR(_E); } /* RR E */
+OP(cb,1c) { _H = RR(_H); } /* RR H */
+OP(cb,1d) { _L = RR(_L); } /* RR L */
+OP(cb,1e) { WM( _HL, RR(RM(_HL)) ); } /* RR (HL) */
+OP(cb,1f) { _A = RR(_A); } /* RR A */
+
+OP(cb,20) { _B = SLA(_B); } /* SLA B */
+OP(cb,21) { _C = SLA(_C); } /* SLA C */
+OP(cb,22) { _D = SLA(_D); } /* SLA D */
+OP(cb,23) { _E = SLA(_E); } /* SLA E */
+OP(cb,24) { _H = SLA(_H); } /* SLA H */
+OP(cb,25) { _L = SLA(_L); } /* SLA L */
+OP(cb,26) { WM( _HL, SLA(RM(_HL)) ); } /* SLA (HL) */
+OP(cb,27) { _A = SLA(_A); } /* SLA A */
+
+OP(cb,28) { _B = SRA(_B); } /* SRA B */
+OP(cb,29) { _C = SRA(_C); } /* SRA C */
+OP(cb,2a) { _D = SRA(_D); } /* SRA D */
+OP(cb,2b) { _E = SRA(_E); } /* SRA E */
+OP(cb,2c) { _H = SRA(_H); } /* SRA H */
+OP(cb,2d) { _L = SRA(_L); } /* SRA L */
+OP(cb,2e) { WM( _HL, SRA(RM(_HL)) ); } /* SRA (HL) */
+OP(cb,2f) { _A = SRA(_A); } /* SRA A */
+
+OP(cb,30) { _B = SLL(_B); } /* SLL B */
+OP(cb,31) { _C = SLL(_C); } /* SLL C */
+OP(cb,32) { _D = SLL(_D); } /* SLL D */
+OP(cb,33) { _E = SLL(_E); } /* SLL E */
+OP(cb,34) { _H = SLL(_H); } /* SLL H */
+OP(cb,35) { _L = SLL(_L); } /* SLL L */
+OP(cb,36) { WM( _HL, SLL(RM(_HL)) ); } /* SLL (HL) */
+OP(cb,37) { _A = SLL(_A); } /* SLL A */
+
+OP(cb,38) { _B = SRL(_B); } /* SRL B */
+OP(cb,39) { _C = SRL(_C); } /* SRL C */
+OP(cb,3a) { _D = SRL(_D); } /* SRL D */
+OP(cb,3b) { _E = SRL(_E); } /* SRL E */
+OP(cb,3c) { _H = SRL(_H); } /* SRL H */
+OP(cb,3d) { _L = SRL(_L); } /* SRL L */
+OP(cb,3e) { WM( _HL, SRL(RM(_HL)) ); } /* SRL (HL) */
+OP(cb,3f) { _A = SRL(_A); } /* SRL A */
+
+OP(cb,40) { BIT(0,_B); } /* BIT 0,B */
+OP(cb,41) { BIT(0,_C); } /* BIT 0,C */
+OP(cb,42) { BIT(0,_D); } /* BIT 0,D */
+OP(cb,43) { BIT(0,_E); } /* BIT 0,E */
+OP(cb,44) { BIT(0,_H); } /* BIT 0,H */
+OP(cb,45) { BIT(0,_L); } /* BIT 0,L */
+OP(cb,46) { BIT(0,RM(_HL)); } /* BIT 0,(HL) */
+OP(cb,47) { BIT(0,_A); } /* BIT 0,A */
+
+OP(cb,48) { BIT(1,_B); } /* BIT 1,B */
+OP(cb,49) { BIT(1,_C); } /* BIT 1,C */
+OP(cb,4a) { BIT(1,_D); } /* BIT 1,D */
+OP(cb,4b) { BIT(1,_E); } /* BIT 1,E */
+OP(cb,4c) { BIT(1,_H); } /* BIT 1,H */
+OP(cb,4d) { BIT(1,_L); } /* BIT 1,L */
+OP(cb,4e) { BIT(1,RM(_HL)); } /* BIT 1,(HL) */
+OP(cb,4f) { BIT(1,_A); } /* BIT 1,A */
+
+OP(cb,50) { BIT(2,_B); } /* BIT 2,B */
+OP(cb,51) { BIT(2,_C); } /* BIT 2,C */
+OP(cb,52) { BIT(2,_D); } /* BIT 2,D */
+OP(cb,53) { BIT(2,_E); } /* BIT 2,E */
+OP(cb,54) { BIT(2,_H); } /* BIT 2,H */
+OP(cb,55) { BIT(2,_L); } /* BIT 2,L */
+OP(cb,56) { BIT(2,RM(_HL)); } /* BIT 2,(HL) */
+OP(cb,57) { BIT(2,_A); } /* BIT 2,A */
+
+OP(cb,58) { BIT(3,_B); } /* BIT 3,B */
+OP(cb,59) { BIT(3,_C); } /* BIT 3,C */
+OP(cb,5a) { BIT(3,_D); } /* BIT 3,D */
+OP(cb,5b) { BIT(3,_E); } /* BIT 3,E */
+OP(cb,5c) { BIT(3,_H); } /* BIT 3,H */
+OP(cb,5d) { BIT(3,_L); } /* BIT 3,L */
+OP(cb,5e) { BIT(3,RM(_HL)); } /* BIT 3,(HL) */
+OP(cb,5f) { BIT(3,_A); } /* BIT 3,A */
+
+OP(cb,60) { BIT(4,_B); } /* BIT 4,B */
+OP(cb,61) { BIT(4,_C); } /* BIT 4,C */
+OP(cb,62) { BIT(4,_D); } /* BIT 4,D */
+OP(cb,63) { BIT(4,_E); } /* BIT 4,E */
+OP(cb,64) { BIT(4,_H); } /* BIT 4,H */
+OP(cb,65) { BIT(4,_L); } /* BIT 4,L */
+OP(cb,66) { BIT(4,RM(_HL)); } /* BIT 4,(HL) */
+OP(cb,67) { BIT(4,_A); } /* BIT 4,A */
+
+OP(cb,68) { BIT(5,_B); } /* BIT 5,B */
+OP(cb,69) { BIT(5,_C); } /* BIT 5,C */
+OP(cb,6a) { BIT(5,_D); } /* BIT 5,D */
+OP(cb,6b) { BIT(5,_E); } /* BIT 5,E */
+OP(cb,6c) { BIT(5,_H); } /* BIT 5,H */
+OP(cb,6d) { BIT(5,_L); } /* BIT 5,L */
+OP(cb,6e) { BIT(5,RM(_HL)); } /* BIT 5,(HL) */
+OP(cb,6f) { BIT(5,_A); } /* BIT 5,A */
+
+OP(cb,70) { BIT(6,_B); } /* BIT 6,B */
+OP(cb,71) { BIT(6,_C); } /* BIT 6,C */
+OP(cb,72) { BIT(6,_D); } /* BIT 6,D */
+OP(cb,73) { BIT(6,_E); } /* BIT 6,E */
+OP(cb,74) { BIT(6,_H); } /* BIT 6,H */
+OP(cb,75) { BIT(6,_L); } /* BIT 6,L */
+OP(cb,76) { BIT(6,RM(_HL)); } /* BIT 6,(HL) */
+OP(cb,77) { BIT(6,_A); } /* BIT 6,A */
+
+OP(cb,78) { BIT(7,_B); } /* BIT 7,B */
+OP(cb,79) { BIT(7,_C); } /* BIT 7,C */
+OP(cb,7a) { BIT(7,_D); } /* BIT 7,D */
+OP(cb,7b) { BIT(7,_E); } /* BIT 7,E */
+OP(cb,7c) { BIT(7,_H); } /* BIT 7,H */
+OP(cb,7d) { BIT(7,_L); } /* BIT 7,L */
+OP(cb,7e) { BIT(7,RM(_HL)); } /* BIT 7,(HL) */
+OP(cb,7f) { BIT(7,_A); } /* BIT 7,A */
+
+OP(cb,80) { _B = RES(0,_B); } /* RES 0,B */
+OP(cb,81) { _C = RES(0,_C); } /* RES 0,C */
+OP(cb,82) { _D = RES(0,_D); } /* RES 0,D */
+OP(cb,83) { _E = RES(0,_E); } /* RES 0,E */
+OP(cb,84) { _H = RES(0,_H); } /* RES 0,H */
+OP(cb,85) { _L = RES(0,_L); } /* RES 0,L */
+OP(cb,86) { WM( _HL, RES(0,RM(_HL)) ); } /* RES 0,(HL) */
+OP(cb,87) { _A = RES(0,_A); } /* RES 0,A */
+
+OP(cb,88) { _B = RES(1,_B); } /* RES 1,B */
+OP(cb,89) { _C = RES(1,_C); } /* RES 1,C */
+OP(cb,8a) { _D = RES(1,_D); } /* RES 1,D */
+OP(cb,8b) { _E = RES(1,_E); } /* RES 1,E */
+OP(cb,8c) { _H = RES(1,_H); } /* RES 1,H */
+OP(cb,8d) { _L = RES(1,_L); } /* RES 1,L */
+OP(cb,8e) { WM( _HL, RES(1,RM(_HL)) ); } /* RES 1,(HL) */
+OP(cb,8f) { _A = RES(1,_A); } /* RES 1,A */
+
+OP(cb,90) { _B = RES(2,_B); } /* RES 2,B */
+OP(cb,91) { _C = RES(2,_C); } /* RES 2,C */
+OP(cb,92) { _D = RES(2,_D); } /* RES 2,D */
+OP(cb,93) { _E = RES(2,_E); } /* RES 2,E */
+OP(cb,94) { _H = RES(2,_H); } /* RES 2,H */
+OP(cb,95) { _L = RES(2,_L); } /* RES 2,L */
+OP(cb,96) { WM( _HL, RES(2,RM(_HL)) ); } /* RES 2,(HL) */
+OP(cb,97) { _A = RES(2,_A); } /* RES 2,A */
+
+OP(cb,98) { _B = RES(3,_B); } /* RES 3,B */
+OP(cb,99) { _C = RES(3,_C); } /* RES 3,C */
+OP(cb,9a) { _D = RES(3,_D); } /* RES 3,D */
+OP(cb,9b) { _E = RES(3,_E); } /* RES 3,E */
+OP(cb,9c) { _H = RES(3,_H); } /* RES 3,H */
+OP(cb,9d) { _L = RES(3,_L); } /* RES 3,L */
+OP(cb,9e) { WM( _HL, RES(3,RM(_HL)) ); } /* RES 3,(HL) */
+OP(cb,9f) { _A = RES(3,_A); } /* RES 3,A */
+
+OP(cb,a0) { _B = RES(4,_B); } /* RES 4,B */
+OP(cb,a1) { _C = RES(4,_C); } /* RES 4,C */
+OP(cb,a2) { _D = RES(4,_D); } /* RES 4,D */
+OP(cb,a3) { _E = RES(4,_E); } /* RES 4,E */
+OP(cb,a4) { _H = RES(4,_H); } /* RES 4,H */
+OP(cb,a5) { _L = RES(4,_L); } /* RES 4,L */
+OP(cb,a6) { WM( _HL, RES(4,RM(_HL)) ); } /* RES 4,(HL) */
+OP(cb,a7) { _A = RES(4,_A); } /* RES 4,A */
+
+OP(cb,a8) { _B = RES(5,_B); } /* RES 5,B */
+OP(cb,a9) { _C = RES(5,_C); } /* RES 5,C */
+OP(cb,aa) { _D = RES(5,_D); } /* RES 5,D */
+OP(cb,ab) { _E = RES(5,_E); } /* RES 5,E */
+OP(cb,ac) { _H = RES(5,_H); } /* RES 5,H */
+OP(cb,ad) { _L = RES(5,_L); } /* RES 5,L */
+OP(cb,ae) { WM( _HL, RES(5,RM(_HL)) ); } /* RES 5,(HL) */
+OP(cb,af) { _A = RES(5,_A); } /* RES 5,A */
+
+OP(cb,b0) { _B = RES(6,_B); } /* RES 6,B */
+OP(cb,b1) { _C = RES(6,_C); } /* RES 6,C */
+OP(cb,b2) { _D = RES(6,_D); } /* RES 6,D */
+OP(cb,b3) { _E = RES(6,_E); } /* RES 6,E */
+OP(cb,b4) { _H = RES(6,_H); } /* RES 6,H */
+OP(cb,b5) { _L = RES(6,_L); } /* RES 6,L */
+OP(cb,b6) { WM( _HL, RES(6,RM(_HL)) ); } /* RES 6,(HL) */
+OP(cb,b7) { _A = RES(6,_A); } /* RES 6,A */
+
+OP(cb,b8) { _B = RES(7,_B); } /* RES 7,B */
+OP(cb,b9) { _C = RES(7,_C); } /* RES 7,C */
+OP(cb,ba) { _D = RES(7,_D); } /* RES 7,D */
+OP(cb,bb) { _E = RES(7,_E); } /* RES 7,E */
+OP(cb,bc) { _H = RES(7,_H); } /* RES 7,H */
+OP(cb,bd) { _L = RES(7,_L); } /* RES 7,L */
+OP(cb,be) { WM( _HL, RES(7,RM(_HL)) ); } /* RES 7,(HL) */
+OP(cb,bf) { _A = RES(7,_A); } /* RES 7,A */
+
+OP(cb,c0) { _B = SET(0,_B); } /* SET 0,B */
+OP(cb,c1) { _C = SET(0,_C); } /* SET 0,C */
+OP(cb,c2) { _D = SET(0,_D); } /* SET 0,D */
+OP(cb,c3) { _E = SET(0,_E); } /* SET 0,E */
+OP(cb,c4) { _H = SET(0,_H); } /* SET 0,H */
+OP(cb,c5) { _L = SET(0,_L); } /* SET 0,L */
+OP(cb,c6) { WM( _HL, SET(0,RM(_HL)) ); } /* SET 0,(HL) */
+OP(cb,c7) { _A = SET(0,_A); } /* SET 0,A */
+
+OP(cb,c8) { _B = SET(1,_B); } /* SET 1,B */
+OP(cb,c9) { _C = SET(1,_C); } /* SET 1,C */
+OP(cb,ca) { _D = SET(1,_D); } /* SET 1,D */
+OP(cb,cb) { _E = SET(1,_E); } /* SET 1,E */
+OP(cb,cc) { _H = SET(1,_H); } /* SET 1,H */
+OP(cb,cd) { _L = SET(1,_L); } /* SET 1,L */
+OP(cb,ce) { WM( _HL, SET(1,RM(_HL)) ); } /* SET 1,(HL) */
+OP(cb,cf) { _A = SET(1,_A); } /* SET 1,A */
+
+OP(cb,d0) { _B = SET(2,_B); } /* SET 2,B */
+OP(cb,d1) { _C = SET(2,_C); } /* SET 2,C */
+OP(cb,d2) { _D = SET(2,_D); } /* SET 2,D */
+OP(cb,d3) { _E = SET(2,_E); } /* SET 2,E */
+OP(cb,d4) { _H = SET(2,_H); } /* SET 2,H */
+OP(cb,d5) { _L = SET(2,_L); } /* SET 2,L */
+OP(cb,d6) { WM( _HL, SET(2,RM(_HL)) ); }/* SET 2,(HL) */
+OP(cb,d7) { _A = SET(2,_A); } /* SET 2,A */
+
+OP(cb,d8) { _B = SET(3,_B); } /* SET 3,B */
+OP(cb,d9) { _C = SET(3,_C); } /* SET 3,C */
+OP(cb,da) { _D = SET(3,_D); } /* SET 3,D */
+OP(cb,db) { _E = SET(3,_E); } /* SET 3,E */
+OP(cb,dc) { _H = SET(3,_H); } /* SET 3,H */
+OP(cb,dd) { _L = SET(3,_L); } /* SET 3,L */
+OP(cb,de) { WM( _HL, SET(3,RM(_HL)) ); } /* SET 3,(HL) */
+OP(cb,df) { _A = SET(3,_A); } /* SET 3,A */
+
+OP(cb,e0) { _B = SET(4,_B); } /* SET 4,B */
+OP(cb,e1) { _C = SET(4,_C); } /* SET 4,C */
+OP(cb,e2) { _D = SET(4,_D); } /* SET 4,D */
+OP(cb,e3) { _E = SET(4,_E); } /* SET 4,E */
+OP(cb,e4) { _H = SET(4,_H); } /* SET 4,H */
+OP(cb,e5) { _L = SET(4,_L); } /* SET 4,L */
+OP(cb,e6) { WM( _HL, SET(4,RM(_HL)) ); } /* SET 4,(HL) */
+OP(cb,e7) { _A = SET(4,_A); } /* SET 4,A */
+
+OP(cb,e8) { _B = SET(5,_B); } /* SET 5,B */
+OP(cb,e9) { _C = SET(5,_C); } /* SET 5,C */
+OP(cb,ea) { _D = SET(5,_D); } /* SET 5,D */
+OP(cb,eb) { _E = SET(5,_E); } /* SET 5,E */
+OP(cb,ec) { _H = SET(5,_H); } /* SET 5,H */
+OP(cb,ed) { _L = SET(5,_L); } /* SET 5,L */
+OP(cb,ee) { WM( _HL, SET(5,RM(_HL)) ); } /* SET 5,(HL) */
+OP(cb,ef) { _A = SET(5,_A); } /* SET 5,A */
+
+OP(cb,f0) { _B = SET(6,_B); } /* SET 6,B */
+OP(cb,f1) { _C = SET(6,_C); } /* SET 6,C */
+OP(cb,f2) { _D = SET(6,_D); } /* SET 6,D */
+OP(cb,f3) { _E = SET(6,_E); } /* SET 6,E */
+OP(cb,f4) { _H = SET(6,_H); } /* SET 6,H */
+OP(cb,f5) { _L = SET(6,_L); } /* SET 6,L */
+OP(cb,f6) { WM( _HL, SET(6,RM(_HL)) ); } /* SET 6,(HL) */
+OP(cb,f7) { _A = SET(6,_A); } /* SET 6,A */
+
+OP(cb,f8) { _B = SET(7,_B); } /* SET 7,B */
+OP(cb,f9) { _C = SET(7,_C); } /* SET 7,C */
+OP(cb,fa) { _D = SET(7,_D); } /* SET 7,D */
+OP(cb,fb) { _E = SET(7,_E); } /* SET 7,E */
+OP(cb,fc) { _H = SET(7,_H); } /* SET 7,H */
+OP(cb,fd) { _L = SET(7,_L); } /* SET 7,L */
+OP(cb,fe) { WM( _HL, SET(7,RM(_HL)) ); } /* SET 7,(HL) */
+OP(cb,ff) { _A = SET(7,_A); } /* SET 7,A */
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+/*****************************************************************************
+ *
+ * z180dasm.c
+ * Portable Z8x180 disassembler
+ *
+ *****************************************************************************/
+
+#include "emu.h"
+#include "z180dasm.h"
+
+const char *const /*z180_disassembler::*/s_mnemonic[] = {
+ "adc" ,"add" ,"and" ,"bit" ,"call" ,"ccf" ,"cp" ,"cpd" ,
+ "cpdr" ,"cpi" ,"cpir" ,"cpl" ,"daa" ,"db" ,"dec" ,"di" ,
+ "djnz" ,"ei" ,"ex" ,"exx" ,"halt" ,"im" ,"in" ,"in0" ,
+ "inc" ,"ind" ,"indr" ,"ini" ,"inir" ,"jp" ,"jr" ,"ld" ,
+ "ldd" ,"lddr" ,"ldi" ,"ldir" ,"mlt" ,"neg" ,"nop" ,"or" ,
+ "otdm" ,"otdmr","otdr" ,"otim" ,"otimr","otir" ,"out" ,"out0" ,
+ "outd" ,"outi" ,"pop" ,"push" ,"res" ,"ret" ,"reti" ,"retn" ,
+ "rl" ,"rla" ,"rlc" ,"rlca" ,"rld" ,"rr" ,"rra" ,"rrc" ,
+ "rrca" ,"rrd" ,"rst" ,"sbc" ,"scf" ,"set" ,"sla" ,"sll" ,
+ "slp" ,"sra" ,"srl" ,"sub" ,"tst" ,"tstio","xor "
+};
+
+const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_xx_cb[256]= {
+ {zRLC,"b=Y"}, {zRLC,"c=Y"}, {zRLC,"d=Y"}, {zRLC,"e=Y"},
+ {zRLC,"h=Y"}, {zRLC,"l=Y"}, {zRLC,"Y"}, {zRLC,"a=Y"},
+ {zRRC,"b=Y"}, {zRRC,"c=Y"}, {zRRC,"d=Y"}, {zRRC,"e=Y"},
+ {zRRC,"h=Y"}, {zRRC,"l=Y"}, {zRRC,"Y"}, {zRRC,"a=Y"},
+ {zRL,"b=Y"}, {zRL,"c=Y"}, {zRL,"d=Y"}, {zRL,"e=Y"},
+ {zRL,"h=Y"}, {zRL,"l=Y"}, {zRL,"Y"}, {zRL,"a=Y"},
+ {zRR,"b=Y"}, {zRR,"c=Y"}, {zRR,"d=Y"}, {zRR,"e=Y"},
+ {zRR,"h=Y"}, {zRR,"l=Y"}, {zRR,"Y"}, {zRR,"a=Y"},
+ {zSLA,"b=Y"}, {zSLA,"c=Y"}, {zSLA,"d=Y"}, {zSLA,"e=Y"},
+ {zSLA,"h=Y"}, {zSLA,"l=Y"}, {zSLA,"Y"}, {zSLA,"a=Y"},
+ {zSRA,"b=Y"}, {zSRA,"c=Y"}, {zSRA,"d=Y"}, {zSRA,"e=Y"},
+ {zSRA,"h=Y"}, {zSRA,"l=Y"}, {zSRA,"Y"}, {zSRA,"a=Y"},
+ {zSLL,"b=Y"}, {zSLL,"c=Y"}, {zSLL,"d=Y"}, {zSLL,"e=Y"},
+ {zSLL,"h=Y"}, {zSLL,"l=Y"}, {zSLL,"Y"}, {zSLL,"a=Y"},
+ {zSRL,"b=Y"}, {zSRL,"c=Y"}, {zSRL,"d=Y"}, {zSRL,"e=Y"},
+ {zSRL,"h=Y"}, {zSRL,"l=Y"}, {zSRL,"Y"}, {zSRL,"a=Y"},
+ {zBIT,"b=0,Y"}, {zBIT,"c=0,Y"}, {zBIT,"d=0,Y"}, {zBIT,"e=0,Y"},
+ {zBIT,"h=0,Y"}, {zBIT,"l=0,Y"}, {zBIT,"0,Y"}, {zBIT,"a=0,Y"},
+ {zBIT,"b=1,Y"}, {zBIT,"c=1,Y"}, {zBIT,"d=1,Y"}, {zBIT,"e=1,Y"},
+ {zBIT,"h=1,Y"}, {zBIT,"l=1,Y"}, {zBIT,"1,Y"}, {zBIT,"a=1,Y"},
+ {zBIT,"b=2,Y"}, {zBIT,"c=2,Y"}, {zBIT,"d=2,Y"}, {zBIT,"e=2,Y"},
+ {zBIT,"h=2,Y"}, {zBIT,"l=2,Y"}, {zBIT,"2,Y"}, {zBIT,"a=2,Y"},
+ {zBIT,"b=3,Y"}, {zBIT,"c=3,Y"}, {zBIT,"d=3,Y"}, {zBIT,"e=3,Y"},
+ {zBIT,"h=3,Y"}, {zBIT,"l=3,Y"}, {zBIT,"3,Y"}, {zBIT,"a=3,Y"},
+ {zBIT,"b=4,Y"}, {zBIT,"c=4,Y"}, {zBIT,"d=4,Y"}, {zBIT,"e=4,Y"},
+ {zBIT,"h=4,Y"}, {zBIT,"l=4,Y"}, {zBIT,"4,Y"}, {zBIT,"a=4,Y"},
+ {zBIT,"b=5,Y"}, {zBIT,"c=5,Y"}, {zBIT,"d=5,Y"}, {zBIT,"e=5,Y"},
+ {zBIT,"h=5,Y"}, {zBIT,"l=5,Y"}, {zBIT,"5,Y"}, {zBIT,"a=5,Y"},
+ {zBIT,"b=6,Y"}, {zBIT,"c=6,Y"}, {zBIT,"d=6,Y"}, {zBIT,"e=6,Y"},
+ {zBIT,"h=6,Y"}, {zBIT,"l=6,Y"}, {zBIT,"6,Y"}, {zBIT,"a=6,Y"},
+ {zBIT,"b=7,Y"}, {zBIT,"c=7,Y"}, {zBIT,"d=7,Y"}, {zBIT,"e=7,Y"},
+ {zBIT,"h=7,Y"}, {zBIT,"l=7,Y"}, {zBIT,"7,Y"}, {zBIT,"a=7,Y"},
+ {zRES,"b=0,Y"}, {zRES,"c=0,Y"}, {zRES,"d=0,Y"}, {zRES,"e=0,Y"},
+ {zRES,"h=0,Y"}, {zRES,"l=0,Y"}, {zRES,"0,Y"}, {zRES,"a=0,Y"},
+ {zRES,"b=1,Y"}, {zRES,"c=1,Y"}, {zRES,"d=1,Y"}, {zRES,"e=1,Y"},
+ {zRES,"h=1,Y"}, {zRES,"l=1,Y"}, {zRES,"1,Y"}, {zRES,"a=1,Y"},
+ {zRES,"b=2,Y"}, {zRES,"c=2,Y"}, {zRES,"d=2,Y"}, {zRES,"e=2,Y"},
+ {zRES,"h=2,Y"}, {zRES,"l=2,Y"}, {zRES,"2,Y"}, {zRES,"a=2,Y"},
+ {zRES,"b=3,Y"}, {zRES,"c=3,Y"}, {zRES,"d=3,Y"}, {zRES,"e=3,Y"},
+ {zRES,"h=3,Y"}, {zRES,"l=3,Y"}, {zRES,"3,Y"}, {zRES,"a=3,Y"},
+ {zRES,"b=4,Y"}, {zRES,"c=4,Y"}, {zRES,"d=4,Y"}, {zRES,"e=4,Y"},
+ {zRES,"h=4,Y"}, {zRES,"l=4,Y"}, {zRES,"4,Y"}, {zRES,"a=4,Y"},
+ {zRES,"b=5,Y"}, {zRES,"c=5,Y"}, {zRES,"d=5,Y"}, {zRES,"e=5,Y"},
+ {zRES,"h=5,Y"}, {zRES,"l=5,Y"}, {zRES,"5,Y"}, {zRES,"a=5,Y"},
+ {zRES,"b=6,Y"}, {zRES,"c=6,Y"}, {zRES,"d=6,Y"}, {zRES,"e=6,Y"},
+ {zRES,"h=6,Y"}, {zRES,"l=6,Y"}, {zRES,"6,Y"}, {zRES,"a=6,Y"},
+ {zRES,"b=7,Y"}, {zRES,"c=7,Y"}, {zRES,"d=7,Y"}, {zRES,"e=7,Y"},
+ {zRES,"h=7,Y"}, {zRES,"l=7,Y"}, {zRES,"7,Y"}, {zRES,"a=7,Y"},
+ {zSET,"b=0,Y"}, {zSET,"c=0,Y"}, {zSET,"d=0,Y"}, {zSET,"e=0,Y"},
+ {zSET,"h=0,Y"}, {zSET,"l=0,Y"}, {zSET,"0,Y"}, {zSET,"a=0,Y"},
+ {zSET,"b=1,Y"}, {zSET,"c=1,Y"}, {zSET,"d=1,Y"}, {zSET,"e=1,Y"},
+ {zSET,"h=1,Y"}, {zSET,"l=1,Y"}, {zSET,"1,Y"}, {zSET,"a=1,Y"},
+ {zSET,"b=2,Y"}, {zSET,"c=2,Y"}, {zSET,"d=2,Y"}, {zSET,"e=2,Y"},
+ {zSET,"h=2,Y"}, {zSET,"l=2,Y"}, {zSET,"2,Y"}, {zSET,"a=2,Y"},
+ {zSET,"b=3,Y"}, {zSET,"c=3,Y"}, {zSET,"d=3,Y"}, {zSET,"e=3,Y"},
+ {zSET,"h=3,Y"}, {zSET,"l=3,Y"}, {zSET,"3,Y"}, {zSET,"a=3,Y"},
+ {zSET,"b=4,Y"}, {zSET,"c=4,Y"}, {zSET,"d=4,Y"}, {zSET,"e=4,Y"},
+ {zSET,"h=4,Y"}, {zSET,"l=4,Y"}, {zSET,"4,Y"}, {zSET,"a=4,Y"},
+ {zSET,"b=5,Y"}, {zSET,"c=5,Y"}, {zSET,"d=5,Y"}, {zSET,"e=5,Y"},
+ {zSET,"h=5,Y"}, {zSET,"l=5,Y"}, {zSET,"5,Y"}, {zSET,"a=5,Y"},
+ {zSET,"b=6,Y"}, {zSET,"c=6,Y"}, {zSET,"d=6,Y"}, {zSET,"e=6,Y"},
+ {zSET,"h=6,Y"}, {zSET,"l=6,Y"}, {zSET,"6,Y"}, {zSET,"a=6,Y"},
+ {zSET,"b=7,Y"}, {zSET,"c=7,Y"}, {zSET,"d=7,Y"}, {zSET,"e=7,Y"},
+ {zSET,"h=7,Y"}, {zSET,"l=7,Y"}, {zSET,"7,Y"}, {zSET,"a=7,Y"}
+};
+
+const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_cb[256] = {
+ {zRLC,"b"}, {zRLC,"c"}, {zRLC,"d"}, {zRLC,"e"},
+ {zRLC,"h"}, {zRLC,"l"}, {zRLC,"(hl)"}, {zRLC,"a"},
+ {zRRC,"b"}, {zRRC,"c"}, {zRRC,"d"}, {zRRC,"e"},
+ {zRRC,"h"}, {zRRC,"l"}, {zRRC,"(hl)"}, {zRRC,"a"},
+ {zRL,"b"}, {zRL,"c"}, {zRL,"d"}, {zRL,"e"},
+ {zRL,"h"}, {zRL,"l"}, {zRL,"(hl)"}, {zRL,"a"},
+ {zRR,"b"}, {zRR,"c"}, {zRR,"d"}, {zRR,"e"},
+ {zRR,"h"}, {zRR,"l"}, {zRR,"(hl)"}, {zRR,"a"},
+ {zSLA,"b"}, {zSLA,"c"}, {zSLA,"d"}, {zSLA,"e"},
+ {zSLA,"h"}, {zSLA,"l"}, {zSLA,"(hl)"}, {zSLA,"a"},
+ {zSRA,"b"}, {zSRA,"c"}, {zSRA,"d"}, {zSRA,"e"},
+ {zSRA,"h"}, {zSRA,"l"}, {zSRA,"(hl)"}, {zSRA,"a"},
+ {zSLL,"b"}, {zSLL,"c"}, {zSLL,"d"}, {zSLL,"e"},
+ {zSLL,"h"}, {zSLL,"l"}, {zSLL,"(hl)"}, {zSLL,"a"},
+ {zSRL,"b"}, {zSRL,"c"}, {zSRL,"d"}, {zSRL,"e"},
+ {zSRL,"h"}, {zSRL,"l"}, {zSRL,"(hl)"}, {zSRL,"a"},
+ {zBIT,"0,b"}, {zBIT,"0,c"}, {zBIT,"0,d"}, {zBIT,"0,e"},
+ {zBIT,"0,h"}, {zBIT,"0,l"}, {zBIT,"0,(hl)"},{zBIT,"0,a"},
+ {zBIT,"1,b"}, {zBIT,"1,c"}, {zBIT,"1,d"}, {zBIT,"1,e"},
+ {zBIT,"1,h"}, {zBIT,"1,l"}, {zBIT,"1,(hl)"},{zBIT,"1,a"},
+ {zBIT,"2,b"}, {zBIT,"2,c"}, {zBIT,"2,d"}, {zBIT,"2,e"},
+ {zBIT,"2,h"}, {zBIT,"2,l"}, {zBIT,"2,(hl)"},{zBIT,"2,a"},
+ {zBIT,"3,b"}, {zBIT,"3,c"}, {zBIT,"3,d"}, {zBIT,"3,e"},
+ {zBIT,"3,h"}, {zBIT,"3,l"}, {zBIT,"3,(hl)"},{zBIT,"3,a"},
+ {zBIT,"4,b"}, {zBIT,"4,c"}, {zBIT,"4,d"}, {zBIT,"4,e"},
+ {zBIT,"4,h"}, {zBIT,"4,l"}, {zBIT,"4,(hl)"},{zBIT,"4,a"},
+ {zBIT,"5,b"}, {zBIT,"5,c"}, {zBIT,"5,d"}, {zBIT,"5,e"},
+ {zBIT,"5,h"}, {zBIT,"5,l"}, {zBIT,"5,(hl)"},{zBIT,"5,a"},
+ {zBIT,"6,b"}, {zBIT,"6,c"}, {zBIT,"6,d"}, {zBIT,"6,e"},
+ {zBIT,"6,h"}, {zBIT,"6,l"}, {zBIT,"6,(hl)"},{zBIT,"6,a"},
+ {zBIT,"7,b"}, {zBIT,"7,c"}, {zBIT,"7,d"}, {zBIT,"7,e"},
+ {zBIT,"7,h"}, {zBIT,"7,l"}, {zBIT,"7,(hl)"},{zBIT,"7,a"},
+ {zRES,"0,b"}, {zRES,"0,c"}, {zRES,"0,d"}, {zRES,"0,e"},
+ {zRES,"0,h"}, {zRES,"0,l"}, {zRES,"0,(hl)"},{zRES,"0,a"},
+ {zRES,"1,b"}, {zRES,"1,c"}, {zRES,"1,d"}, {zRES,"1,e"},
+ {zRES,"1,h"}, {zRES,"1,l"}, {zRES,"1,(hl)"},{zRES,"1,a"},
+ {zRES,"2,b"}, {zRES,"2,c"}, {zRES,"2,d"}, {zRES,"2,e"},
+ {zRES,"2,h"}, {zRES,"2,l"}, {zRES,"2,(hl)"},{zRES,"2,a"},
+ {zRES,"3,b"}, {zRES,"3,c"}, {zRES,"3,d"}, {zRES,"3,e"},
+ {zRES,"3,h"}, {zRES,"3,l"}, {zRES,"3,(hl)"},{zRES,"3,a"},
+ {zRES,"4,b"}, {zRES,"4,c"}, {zRES,"4,d"}, {zRES,"4,e"},
+ {zRES,"4,h"}, {zRES,"4,l"}, {zRES,"4,(hl)"},{zRES,"4,a"},
+ {zRES,"5,b"}, {zRES,"5,c"}, {zRES,"5,d"}, {zRES,"5,e"},
+ {zRES,"5,h"}, {zRES,"5,l"}, {zRES,"5,(hl)"},{zRES,"5,a"},
+ {zRES,"6,b"}, {zRES,"6,c"}, {zRES,"6,d"}, {zRES,"6,e"},
+ {zRES,"6,h"}, {zRES,"6,l"}, {zRES,"6,(hl)"},{zRES,"6,a"},
+ {zRES,"7,b"}, {zRES,"7,c"}, {zRES,"7,d"}, {zRES,"7,e"},
+ {zRES,"7,h"}, {zRES,"7,l"}, {zRES,"7,(hl)"},{zRES,"7,a"},
+ {zSET,"0,b"}, {zSET,"0,c"}, {zSET,"0,d"}, {zSET,"0,e"},
+ {zSET,"0,h"}, {zSET,"0,l"}, {zSET,"0,(hl)"},{zSET,"0,a"},
+ {zSET,"1,b"}, {zSET,"1,c"}, {zSET,"1,d"}, {zSET,"1,e"},
+ {zSET,"1,h"}, {zSET,"1,l"}, {zSET,"1,(hl)"},{zSET,"1,a"},
+ {zSET,"2,b"}, {zSET,"2,c"}, {zSET,"2,d"}, {zSET,"2,e"},
+ {zSET,"2,h"}, {zSET,"2,l"}, {zSET,"2,(hl)"},{zSET,"2,a"},
+ {zSET,"3,b"}, {zSET,"3,c"}, {zSET,"3,d"}, {zSET,"3,e"},
+ {zSET,"3,h"}, {zSET,"3,l"}, {zSET,"3,(hl)"},{zSET,"3,a"},
+ {zSET,"4,b"}, {zSET,"4,c"}, {zSET,"4,d"}, {zSET,"4,e"},
+ {zSET,"4,h"}, {zSET,"4,l"}, {zSET,"4,(hl)"},{zSET,"4,a"},
+ {zSET,"5,b"}, {zSET,"5,c"}, {zSET,"5,d"}, {zSET,"5,e"},
+ {zSET,"5,h"}, {zSET,"5,l"}, {zSET,"5,(hl)"},{zSET,"5,a"},
+ {zSET,"6,b"}, {zSET,"6,c"}, {zSET,"6,d"}, {zSET,"6,e"},
+ {zSET,"6,h"}, {zSET,"6,l"}, {zSET,"6,(hl)"},{zSET,"6,a"},
+ {zSET,"7,b"}, {zSET,"7,c"}, {zSET,"7,d"}, {zSET,"7,e"},
+ {zSET,"7,h"}, {zSET,"7,l"}, {zSET,"7,(hl)"},{zSET,"7,a"}
+};
+
+const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_ed[256]= {
+ {zIN0,"b,(B)"}, {zOUT0,"(B),b"},{zDB,"?"}, {zDB,"?"},
+ {zTST,"b"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zIN0,"c,(B)"}, {zOUT0,"(B),c"},{zDB,"?"}, {zDB,"?"},
+ {zTST,"c"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zIN0,"d,(B)"}, {zOUT0,"(B),d"},{zDB,"?"}, {zDB,"?"},
+ {zTST,"d"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zIN0,"e,(B)"}, {zOUT0,"(B),e"},{zDB,"?"}, {zDB,"?"},
+ {zTST,"e"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zIN0,"h,(B)"}, {zOUT0,"(B),h"},{zDB,"?"}, {zDB,"?"},
+ {zTST,"h"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zIN0,"l,(B)"}, {zOUT0,"(B),l"},{zDB,"?"}, {zDB,"?"},
+ {zTST,"l"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zIN0,"f,(B)"}, {zOUT0,"(B),0"},{zDB,"?"}, {zDB,"?"},
+ {zTST,"(hl)"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zIN0,"a,(B)"}, {zOUT0,"(B),a"},{zDB,"?"}, {zDB,"?"},
+ {zTST,"a"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zIN,"b,(c)"}, {zOUT,"(c),b"}, {zSBC,"hl,bc"}, {zLD,"(W),bc"},
+ {zNEG,/*nullptr*/NULL}, {zRETN,/*nullptr*/NULL}, {zIM,"0"}, {zLD,"i,a"},
+ {zIN,"c,(c)"}, {zOUT,"(c),c"}, {zADC,"hl,bc"}, {zLD,"bc,(W)"},
+ {zMLT,"bc"}, {zRETI,/*nullptr*/NULL}, {zIM,"0"}, {zLD,"r,a"},
+ {zIN,"d,(c)"}, {zOUT,"(c),d"}, {zSBC,"hl,de"}, {zLD,"(W),de"},
+ {zNEG,"*"}, {zRETN,/*nullptr*/NULL}, {zIM,"1"}, {zLD,"a,i"},
+ {zIN,"e,(c)"}, {zOUT,"(c),e"}, {zADC,"hl,de"}, {zLD,"de,(W)"},
+ {zMLT,"de"}, {zRETI,/*nullptr*/NULL}, {zIM,"2"}, {zLD,"a,r"},
+ {zIN,"h,(c)"}, {zOUT,"(c),h"}, {zSBC,"hl,hl"}, {zLD,"(W),hl"},
+ {zTST,"B"}, {zRETN,/*nullptr*/NULL}, {zIM,"0"}, {zRRD,"(hl)"},
+ {zIN,"l,(c)"}, {zOUT,"(c),l"}, {zADC,"hl,hl"}, {zLD,"hl,(W)"},
+ {zMLT,"hl"}, {zRETI,/*nullptr*/NULL}, {zIM,"0"}, {zRLD,"(hl)"},
+ {zIN,"0,(c)"}, {zOUT,"(c),0"}, {zSBC,"hl,sp"}, {zLD,"(W),sp"},
+ {zTSTIO,"B"}, {zRETN,/*nullptr*/NULL}, {zSLP,/*nullptr*/NULL}, {zDB,"?"},
+ {zIN,"a,(c)"}, {zOUT,"(c),a"}, {zADC,"hl,sp"}, {zLD,"sp,(W)"},
+ {zMLT,"sp"}, {zRETI,/*nullptr*/NULL}, {zIM,"2"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zOTIM,/*nullptr*/NULL},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zOTDM,/*nullptr*/NULL},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zOTIMR,/*nullptr*/NULL},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zOTDMR,/*nullptr*/NULL},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zLDI,/*nullptr*/NULL}, {zCPI,/*nullptr*/NULL}, {zINI,/*nullptr*/NULL}, {zOUTI,/*nullptr*/NULL},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zLDD,/*nullptr*/NULL}, {zCPD,/*nullptr*/NULL}, {zIND,/*nullptr*/NULL}, {zOUTD,/*nullptr*/NULL},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zLDIR,/*nullptr*/NULL}, {zCPIR,/*nullptr*/NULL}, {zINIR,/*nullptr*/NULL}, {zOTIR,/*nullptr*/NULL},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zLDDR,/*nullptr*/NULL}, {zCPDR,/*nullptr*/NULL}, {zINDR,/*nullptr*/NULL}, {zOTDR,/*nullptr*/NULL},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}
+};
+
+const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_xx[256]= {
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zADD,"I,bc"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zADD,"I,de"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zLD,"I,N"}, {zLD,"(W),I"}, {zINC,"I"},
+ {zINC,"Ih"}, {zDEC,"Ih"}, {zLD,"Ih,B"}, {zDB,"?"},
+ {zDB,"?"}, {zADD,"I,I"}, {zLD,"I,(W)"}, {zDEC,"I"},
+ {zINC,"Il"}, {zDEC,"Il"}, {zLD,"Il,B"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zINC,"X"}, {zDEC,"X"}, {zLD,"X,B"}, {zDB,"?"},
+ {zDB,"?"}, {zADD,"I,sp"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zLD,"b,Ih"}, {zLD,"b,Il"}, {zLD,"b,X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zLD,"c,Ih"}, {zLD,"c,Il"}, {zLD,"c,X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zLD,"d,Ih"}, {zLD,"d,Il"}, {zLD,"d,X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zLD,"e,Ih"}, {zLD,"e,Il"}, {zLD,"e,X"}, {zDB,"?"},
+ {zLD,"Ih,b"}, {zLD,"Ih,c"}, {zLD,"Ih,d"}, {zLD,"Ih,e"},
+ {zLD,"Ih,Ih"}, {zLD,"Ih,Il"}, {zLD,"h,X"}, {zLD,"Ih,a"},
+ {zLD,"Il,b"}, {zLD,"Il,c"}, {zLD,"Il,d"}, {zLD,"Il,e"},
+ {zLD,"Il,Ih"}, {zLD,"Il,Il"}, {zLD,"l,X"}, {zLD,"Il,a"},
+ {zLD,"X,b"}, {zLD,"X,c"}, {zLD,"X,d"}, {zLD,"X,e"},
+ {zLD,"X,h"}, {zLD,"X,l"}, {zDB,"?"}, {zLD,"X,a"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zLD,"a,Ih"}, {zLD,"a,Il"}, {zLD,"a,X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zADD,"a,Ih"}, {zADD,"a,Il"}, {zADD,"a,X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zADC,"a,Ih"}, {zADC,"a,Il"}, {zADC,"a,X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zSUB,"Ih"}, {zSUB,"Il"}, {zSUB,"X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zSBC,"a,Ih"}, {zSBC,"a,Il"}, {zSBC,"a,X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zAND,"Ih"}, {zAND,"Il"}, {zAND,"X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zXOR,"Ih"}, {zXOR,"Il"}, {zXOR,"X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zOR,"Ih"}, {zOR,"Il"}, {zOR,"X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zCP,"Ih"}, {zCP,"Il"}, {zCP,"X"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"cb"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zPOP,"I"}, {zDB,"?"}, {zEX,"(sp),I"},
+ {zDB,"?"}, {zPUSH,"I"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zJP,"(I)"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zLD,"sp,I"}, {zDB,"?"}, {zDB,"?"},
+ {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}
+};
+
+const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_main[256]= {
+ {zNOP,/*nullptr*/NULL}, {zLD,"bc,N"}, {zLD,"(bc),a"}, {zINC,"bc"},
+ {zINC,"b"}, {zDEC,"b"}, {zLD,"b,B"}, {zRLCA,/*nullptr*/NULL},
+ {zEX,"af,af'"}, {zADD,"hl,bc"}, {zLD,"a,(bc)"}, {zDEC,"bc"},
+ {zINC,"c"}, {zDEC,"c"}, {zLD,"c,B"}, {zRRCA,/*nullptr*/NULL},
+ {zDJNZ,"O"}, {zLD,"de,N"}, {zLD,"(de),a"}, {zINC,"de"},
+ {zINC,"d"}, {zDEC,"d"}, {zLD,"d,B"}, {zRLA,/*nullptr*/NULL},
+ {zJR,"O"}, {zADD,"hl,de"}, {zLD,"a,(de)"}, {zDEC,"de"},
+ {zINC,"e"}, {zDEC,"e"}, {zLD,"e,B"}, {zRRA,/*nullptr*/NULL},
+ {zJR,"nz,O"}, {zLD,"hl,N"}, {zLD,"(W),hl"}, {zINC,"hl"},
+ {zINC,"h"}, {zDEC,"h"}, {zLD,"h,B"}, {zDAA,/*nullptr*/NULL},
+ {zJR,"z,O"}, {zADD,"hl,hl"}, {zLD,"hl,(W)"}, {zDEC,"hl"},
+ {zINC,"l"}, {zDEC,"l"}, {zLD,"l,B"}, {zCPL,/*nullptr*/NULL},
+ {zJR,"nc,O"}, {zLD,"sp,N"}, {zLD,"(W),a"}, {zINC,"sp"},
+ {zINC,"(hl)"}, {zDEC,"(hl)"}, {zLD,"(hl),B"}, {zSCF,/*nullptr*/NULL},
+ {zJR,"c,O"}, {zADD,"hl,sp"}, {zLD,"a,(W)"}, {zDEC,"sp"},
+ {zINC,"a"}, {zDEC,"a"}, {zLD,"a,B"}, {zCCF,/*nullptr*/NULL},
+ {zLD,"b,b"}, {zLD,"b,c"}, {zLD,"b,d"}, {zLD,"b,e"},
+ {zLD,"b,h"}, {zLD,"b,l"}, {zLD,"b,(hl)"}, {zLD,"b,a"},
+ {zLD,"c,b"}, {zLD,"c,c"}, {zLD,"c,d"}, {zLD,"c,e"},
+ {zLD,"c,h"}, {zLD,"c,l"}, {zLD,"c,(hl)"}, {zLD,"c,a"},
+ {zLD,"d,b"}, {zLD,"d,c"}, {zLD,"d,d"}, {zLD,"d,e"},
+ {zLD,"d,h"}, {zLD,"d,l"}, {zLD,"d,(hl)"}, {zLD,"d,a"},
+ {zLD,"e,b"}, {zLD,"e,c"}, {zLD,"e,d"}, {zLD,"e,e"},
+ {zLD,"e,h"}, {zLD,"e,l"}, {zLD,"e,(hl)"}, {zLD,"e,a"},
+ {zLD,"h,b"}, {zLD,"h,c"}, {zLD,"h,d"}, {zLD,"h,e"},
+ {zLD,"h,h"}, {zLD,"h,l"}, {zLD,"h,(hl)"}, {zLD,"h,a"},
+ {zLD,"l,b"}, {zLD,"l,c"}, {zLD,"l,d"}, {zLD,"l,e"},
+ {zLD,"l,h"}, {zLD,"l,l"}, {zLD,"l,(hl)"}, {zLD,"l,a"},
+ {zLD,"(hl),b"}, {zLD,"(hl),c"}, {zLD,"(hl),d"}, {zLD,"(hl),e"},
+ {zLD,"(hl),h"}, {zLD,"(hl),l"}, {zHLT,/*nullptr*/NULL}, {zLD,"(hl),a"},
+ {zLD,"a,b"}, {zLD,"a,c"}, {zLD,"a,d"}, {zLD,"a,e"},
+ {zLD,"a,h"}, {zLD,"a,l"}, {zLD,"a,(hl)"}, {zLD,"a,a"},
+ {zADD,"a,b"}, {zADD,"a,c"}, {zADD,"a,d"}, {zADD,"a,e"},
+ {zADD,"a,h"}, {zADD,"a,l"}, {zADD,"a,(hl)"},{zADD,"a,a"},
+ {zADC,"a,b"}, {zADC,"a,c"}, {zADC,"a,d"}, {zADC,"a,e"},
+ {zADC,"a,h"}, {zADC,"a,l"}, {zADC,"a,(hl)"},{zADC,"a,a"},
+ {zSUB,"b"}, {zSUB,"c"}, {zSUB,"d"}, {zSUB,"e"},
+ {zSUB,"h"}, {zSUB,"l"}, {zSUB,"(hl)"}, {zSUB,"a"},
+ {zSBC,"a,b"}, {zSBC,"a,c"}, {zSBC,"a,d"}, {zSBC,"a,e"},
+ {zSBC,"a,h"}, {zSBC,"a,l"}, {zSBC,"a,(hl)"},{zSBC,"a,a"},
+ {zAND,"b"}, {zAND,"c"}, {zAND,"d"}, {zAND,"e"},
+ {zAND,"h"}, {zAND,"l"}, {zAND,"(hl)"}, {zAND,"a"},
+ {zXOR,"b"}, {zXOR,"c"}, {zXOR,"d"}, {zXOR,"e"},
+ {zXOR,"h"}, {zXOR,"l"}, {zXOR,"(hl)"}, {zXOR,"a"},
+ {zOR,"b"}, {zOR,"c"}, {zOR,"d"}, {zOR,"e"},
+ {zOR,"h"}, {zOR,"l"}, {zOR,"(hl)"}, {zOR,"a"},
+ {zCP,"b"}, {zCP,"c"}, {zCP,"d"}, {zCP,"e"},
+ {zCP,"h"}, {zCP,"l"}, {zCP,"(hl)"}, {zCP,"a"},
+ {zRET,"nz"}, {zPOP,"bc"}, {zJP,"nz,A"}, {zJP,"A"},
+ {zCALL,"nz,A"}, {zPUSH,"bc"}, {zADD,"a,B"}, {zRST,"V"},
+ {zRET,"z"}, {zRET,/*nullptr*/NULL}, {zJP,"z,A"}, {zDB,"cb"},
+ {zCALL,"z,A"}, {zCALL,"A"}, {zADC,"a,B"}, {zRST,"V"},
+ {zRET,"nc"}, {zPOP,"de"}, {zJP,"nc,A"}, {zOUT,"(P),a"},
+ {zCALL,"nc,A"}, {zPUSH,"de"}, {zSUB,"B"}, {zRST,"V"},
+ {zRET,"c"}, {zEXX,/*nullptr*/NULL}, {zJP,"c,A"}, {zIN,"a,(P)"},
+ {zCALL,"c,A"}, {zDB,"dd"}, {zSBC,"a,B"}, {zRST,"V"},
+ {zRET,"po"}, {zPOP,"hl"}, {zJP,"po,A"}, {zEX,"(sp),hl"},
+ {zCALL,"po,A"}, {zPUSH,"hl"}, {zAND,"B"}, {zRST,"V"},
+ {zRET,"pe"}, {zJP,"(hl)"}, {zJP,"pe,A"}, {zEX,"de,hl"},
+ {zCALL,"pe,A"}, {zDB,"ed"}, {zXOR,"B"}, {zRST,"V"},
+ {zRET,"p"}, {zPOP,"af"}, {zJP,"p,A"}, {zDI,/*nullptr*/NULL},
+ {zCALL,"p,A"}, {zPUSH,"af"}, {zOR,"B"}, {zRST,"V"},
+ {zRET,"m"}, {zLD,"sp,hl"}, {zJP,"m,A"}, {zEI,/*nullptr*/NULL},
+ {zCALL,"m,A"}, {zDB,"fd"}, {zCP,"B"}, {zRST,"V"}
+};
+
+char /*z180_disassembler::*/sign(int8_t offset)
+{
+ return (offset < 0)? '-':'+';
+}
+
+int /*z180_disassembler::*/offs(int8_t offset)
+{
+ if (offset < 0) return -offset;
+ return offset;
+}
+
+/****************************************************************************
+ * Disassemble opcode at PC and return number of bytes it takes
+ ****************************************************************************/
+//offs_t /*z180_disassembler::*/disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms)
+offs_t /*z180_disassembler::*/disassemble(FILE *stream, offs_t pc)
+{
+ const z80dasm *d;
+ const char *src, *ixy;
+ int8_t offset = 0;
+ uint8_t op, op1 = 0;
+ uint16_t ea;
+ offs_t pos = pc;
+ uint32_t flags = 0;
+
+ ixy = "oops!!";
+
+ op = opcodes_r8(pos++);
+
+ switch (op)
+ {
+ case 0xcb:
+ op = opcodes_r8(pos++);
+ d = &mnemonic_cb[op];
+ break;
+ case 0xed:
+ op1 = opcodes_r8(pos++);
+ d = &mnemonic_ed[op1];
+ break;
+ case 0xdd:
+ ixy = "ix";
+ op1 = opcodes_r8(pos++);
+ if( op1 == 0xcb )
+ {
+ offset = (int8_t) params_r8(pos++);
+ op1 = params_r8(pos++); /* fourth byte from opbase.ram! */
+ d = &mnemonic_xx_cb[op1];
+ }
+ else d = &mnemonic_xx[op1];
+ break;
+ case 0xfd:
+ ixy = "iy";
+ op1 = opcodes_r8(pos++);
+ if( op1 == 0xcb )
+ {
+ offset = (int8_t) params_r8(pos++);
+ op1 = params_r8(pos++); /* fourth byte from opbase.ram! */
+ d = &mnemonic_xx_cb[op1];
+ }
+ else d = &mnemonic_xx[op1];
+ break;
+ default:
+ d = &mnemonic_main[op];
+ break;
+ }
+
+ if( d->arguments )
+ {
+ fprintf(stream, "%-5s ", s_mnemonic[d->mnemonic]);
+ src = d->arguments;
+ while( *src )
+ {
+ switch( *src )
+ {
+ case '?': /* illegal opcode */
+ fprintf(stream, "$%02x,$%02x", op, op1);
+ break;
+ case 'A':
+ ea = params_r16(pos);
+ pos += 2;
+ fprintf(stream, "$%04X", ea);
+ break;
+ case 'B': /* Byte op arg */
+ ea = params_r8(pos++);
+ fprintf(stream, "$%02X", ea);
+ break;
+ case 'N': /* Immediate 16 bit */
+ ea = params_r16(pos);
+ pos += 2;
+ fprintf(stream, "$%04X", ea);
+ break;
+ case 'O': /* Offset relative to PC */
+ offset = (int8_t) params_r8(pos++);
+ fprintf(stream, "$%05X", pc + offset + 2);
+ break;
+ case 'P': /* Port number */
+ ea = params_r8(pos++);
+ fprintf(stream, "$%02X", ea);
+ break;
+ case 'V': /* Restart vector */
+ ea = op & 0x38;
+ fprintf(stream, "$%02X", ea);
+ break;
+ case 'W': /* Memory address word */
+ ea = params_r16(pos);
+ pos += 2;
+ fprintf(stream, "$%05X", ea);
+ break;
+ case 'X':
+ offset = (int8_t) params_r8(pos++);
+ case 'Y':
+ fprintf(stream,"(%s%c$%02x)", ixy, sign(offset), offs(offset));
+ break;
+ case 'I':
+ fprintf(stream, "%s", ixy);
+ break;
+ default:
+ fputc(*src, stream);
+ }
+ src++;
+ }
+ }
+ else
+ {
+ fprintf(stream, "%s", s_mnemonic[d->mnemonic]);
+ }
+
+ if (d->mnemonic == zCALL || d->mnemonic == zCPDR || d->mnemonic == zCPIR || d->mnemonic == zDJNZ ||
+ d->mnemonic == zHLT || d->mnemonic == zINDR || d->mnemonic == zINIR || d->mnemonic == zLDDR ||
+ d->mnemonic == zLDIR || d->mnemonic == zOTDR || d->mnemonic == zOTIR || d->mnemonic == zRST)
+ flags = STEP_OVER;
+ else if (d->mnemonic == zRETN || d->mnemonic == zRET || d->mnemonic == zRETI)
+ flags = STEP_OUT;
+
+ return (pos - pc) | flags | SUPPORTED;
+}
+
+//u32 /*z180_disassembler::*/opcode_alignment() const
+//{
+// return 1;
+//}
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+/*****************************************************************************
+ *
+ * z180dasm.c
+ * Portable Z8x180 disassembler
+ *
+ *****************************************************************************/
+
+#ifndef MAME_CPU_Z180_Z180DASM_H
+#define MAME_CPU_Z180_Z180DASM_H
+
+//#pragma once
+#include <stdio.h>
+
+//class z180_disassembler : public util::disasm_interface
+//{
+//public:
+// z180_disassembler() = default;
+// virtual ~z180_disassembler() = default;
+//
+// virtual u32 opcode_alignment() const override;
+// virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override;
+offs_t disassemble(FILE *stream, offs_t pc);
+//
+//private:
+ typedef struct z80dasm {
+ uint8_t mnemonic;
+ const char *arguments;
+ } z80dasm;
+
+ enum e_mnemonics {
+ zADC ,zADD ,zAND ,zBIT ,zCALL ,zCCF ,zCP ,zCPD ,
+ zCPDR ,zCPI ,zCPIR ,zCPL ,zDAA ,zDB ,zDEC ,zDI ,
+ zDJNZ ,zEI ,zEX ,zEXX ,zHLT ,zIM ,zIN ,zIN0 ,
+ zINC ,zIND ,zINDR ,zINI ,zINIR ,zJP ,zJR ,zLD ,
+ zLDD ,zLDDR ,zLDI ,zLDIR ,zMLT ,zNEG ,zNOP ,zOR ,
+ zOTDM ,zOTDMR ,zOTDR ,zOTIM ,zOTIMR ,zOTIR ,zOUT ,zOUT0 ,
+ zOUTD ,zOUTI ,zPOP ,zPUSH ,zRES ,zRET ,zRETI ,zRETN ,
+ zRL ,zRLA ,zRLC ,zRLCA ,zRLD ,zRR ,zRRA ,zRRC ,
+ zRRCA ,zRRD ,zRST ,zSBC ,zSCF ,zSET ,zSLA ,zSLL ,
+ zSLP ,zSRA ,zSRL ,zSUB ,zTST ,zTSTIO ,zXOR
+ };
+
+// static const char *const s_mnemonic[];
+extern const char *const /*z180_disassembler::*/s_mnemonic[];
+// static const z80dasm mnemonic_xx_cb[256];
+extern const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_xx_cb[256];
+// static const z80dasm mnemonic_cb[256];
+extern const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_cb[256];
+// static const z80dasm mnemonic_ed[256];
+extern const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_ed[256];
+// static const z80dasm mnemonic_xx[256];
+extern const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_xx[256];
+// static const z80dasm mnemonic_main[256];
+extern const /*z180_disassembler::*/z80dasm /*z180_disassembler::*/mnemonic_main[256];
+
+// static char sign(int8_t offset);
+// static int offs(int8_t offset);
+//};
+
+#endif
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+OP(illegal,1) {
+ logerror("Z180 '%s' ill. opcode $%02x $%02x\n",
+ tag(), m_ocache_read_byte((_PCD-1)&0xffff), m_ocache_read_byte(_PCD));
+}
+
+/**********************************************************
+ * IX register related opcodes (DD prefix)
+ **********************************************************/
+OP(dd,00) { illegal_1(); op_00(); } /* DB DD */
+OP(dd,01) { illegal_1(); op_01(); } /* DB DD */
+OP(dd,02) { illegal_1(); op_02(); } /* DB DD */
+OP(dd,03) { illegal_1(); op_03(); } /* DB DD */
+OP(dd,04) { illegal_1(); op_04(); } /* DB DD */
+OP(dd,05) { illegal_1(); op_05(); } /* DB DD */
+OP(dd,06) { illegal_1(); op_06(); } /* DB DD */
+OP(dd,07) { illegal_1(); op_07(); } /* DB DD */
+
+OP(dd,08) { illegal_1(); op_08(); } /* DB DD */
+OP(dd,09) { m_R++; ADD16(IX,BC); } /* ADD IX,BC */
+OP(dd,0a) { illegal_1(); op_0a(); } /* DB DD */
+OP(dd,0b) { illegal_1(); op_0b(); } /* DB DD */
+OP(dd,0c) { illegal_1(); op_0c(); } /* DB DD */
+OP(dd,0d) { illegal_1(); op_0d(); } /* DB DD */
+OP(dd,0e) { illegal_1(); op_0e(); } /* DB DD */
+OP(dd,0f) { illegal_1(); op_0f(); } /* DB DD */
+
+OP(dd,10) { illegal_1(); op_10(); } /* DB DD */
+OP(dd,11) { illegal_1(); op_11(); } /* DB DD */
+OP(dd,12) { illegal_1(); op_12(); } /* DB DD */
+OP(dd,13) { illegal_1(); op_13(); } /* DB DD */
+OP(dd,14) { illegal_1(); op_14(); } /* DB DD */
+OP(dd,15) { illegal_1(); op_15(); } /* DB DD */
+OP(dd,16) { illegal_1(); op_16(); } /* DB DD */
+OP(dd,17) { illegal_1(); op_17(); } /* DB DD */
+
+OP(dd,18) { illegal_1(); op_18(); } /* DB DD */
+OP(dd,19) { m_R++; ADD16(IX,DE); } /* ADD IX,DE */
+OP(dd,1a) { illegal_1(); op_1a(); } /* DB DD */
+OP(dd,1b) { illegal_1(); op_1b(); } /* DB DD */
+OP(dd,1c) { illegal_1(); op_1c(); } /* DB DD */
+OP(dd,1d) { illegal_1(); op_1d(); } /* DB DD */
+OP(dd,1e) { illegal_1(); op_1e(); } /* DB DD */
+OP(dd,1f) { illegal_1(); op_1f(); } /* DB DD */
+
+OP(dd,20) { illegal_1(); op_20(); } /* DB DD */
+OP(dd,21) { m_R++; _IX = ARG16(); } /* LD IX,w */
+OP(dd,22) { m_R++; m_ea = ARG16(); WM16( m_ea, &m_IX ); } /* LD (w),IX */
+OP(dd,23) { m_R++; _IX++; } /* INC IX */
+OP(dd,24) { m_R++; _HX = INC(_HX); } /* INC HX */
+OP(dd,25) { m_R++; _HX = DEC(_HX); } /* DEC HX */
+OP(dd,26) { m_R++; _HX = ARG(); } /* LD HX,n */
+OP(dd,27) { illegal_1(); op_27(); } /* DB DD */
+
+OP(dd,28) { illegal_1(); op_28(); } /* DB DD */
+OP(dd,29) { m_R++; ADD16(IX,IX); } /* ADD IX,IX */
+OP(dd,2a) { m_R++; m_ea = ARG16(); RM16( m_ea, &m_IX ); } /* LD IX,(w) */
+OP(dd,2b) { m_R++; _IX--; } /* DEC IX */
+OP(dd,2c) { m_R++; _LX = INC(_LX); } /* INC LX */
+OP(dd,2d) { m_R++; _LX = DEC(_LX); } /* DEC LX */
+OP(dd,2e) { m_R++; _LX = ARG(); } /* LD LX,n */
+OP(dd,2f) { illegal_1(); op_2f(); } /* DB DD */
+
+OP(dd,30) { illegal_1(); op_30(); } /* DB DD */
+OP(dd,31) { illegal_1(); op_31(); } /* DB DD */
+OP(dd,32) { illegal_1(); op_32(); } /* DB DD */
+OP(dd,33) { illegal_1(); op_33(); } /* DB DD */
+OP(dd,34) { m_R++; EAX(); WM( m_ea, INC(RM(m_ea)) ); } /* INC (IX+o) */
+OP(dd,35) { m_R++; EAX(); WM( m_ea, DEC(RM(m_ea)) ); } /* DEC (IX+o) */
+OP(dd,36) { m_R++; EAX(); WM( m_ea, ARG() ); } /* LD (IX+o),n */
+OP(dd,37) { illegal_1(); op_37(); } /* DB DD */
+
+OP(dd,38) { illegal_1(); op_38(); } /* DB DD */
+OP(dd,39) { m_R++; ADD16(IX,SP); } /* ADD IX,SP */
+OP(dd,3a) { illegal_1(); op_3a(); } /* DB DD */
+OP(dd,3b) { illegal_1(); op_3b(); } /* DB DD */
+OP(dd,3c) { illegal_1(); op_3c(); } /* DB DD */
+OP(dd,3d) { illegal_1(); op_3d(); } /* DB DD */
+OP(dd,3e) { illegal_1(); op_3e(); } /* DB DD */
+OP(dd,3f) { illegal_1(); op_3f(); } /* DB DD */
+
+OP(dd,40) { illegal_1(); op_40(); } /* DB DD */
+OP(dd,41) { illegal_1(); op_41(); } /* DB DD */
+OP(dd,42) { illegal_1(); op_42(); } /* DB DD */
+OP(dd,43) { illegal_1(); op_43(); } /* DB DD */
+OP(dd,44) { m_R++; _B = _HX; } /* LD B,HX */
+OP(dd,45) { m_R++; _B = _LX; } /* LD B,LX */
+OP(dd,46) { m_R++; EAX(); _B = RM(m_ea); } /* LD B,(IX+o) */
+OP(dd,47) { illegal_1(); op_47(); } /* DB DD */
+
+OP(dd,48) { illegal_1(); op_48(); } /* DB DD */
+OP(dd,49) { illegal_1(); op_49(); } /* DB DD */
+OP(dd,4a) { illegal_1(); op_4a(); } /* DB DD */
+OP(dd,4b) { illegal_1(); op_4b(); } /* DB DD */
+OP(dd,4c) { m_R++; _C = _HX; } /* LD C,HX */
+OP(dd,4d) { m_R++; _C = _LX; } /* LD C,LX */
+OP(dd,4e) { m_R++; EAX(); _C = RM(m_ea); } /* LD C,(IX+o) */
+OP(dd,4f) { illegal_1(); op_4f(); } /* DB DD */
+
+OP(dd,50) { illegal_1(); op_50(); } /* DB DD */
+OP(dd,51) { illegal_1(); op_51(); } /* DB DD */
+OP(dd,52) { illegal_1(); op_52(); } /* DB DD */
+OP(dd,53) { illegal_1(); op_53(); } /* DB DD */
+OP(dd,54) { m_R++; _D = _HX; } /* LD D,HX */
+OP(dd,55) { m_R++; _D = _LX; } /* LD D,LX */
+OP(dd,56) { m_R++; EAX(); _D = RM(m_ea); } /* LD D,(IX+o) */
+OP(dd,57) { illegal_1(); op_57(); } /* DB DD */
+
+OP(dd,58) { illegal_1(); op_58(); } /* DB DD */
+OP(dd,59) { illegal_1(); op_59(); } /* DB DD */
+OP(dd,5a) { illegal_1(); op_5a(); } /* DB DD */
+OP(dd,5b) { illegal_1(); op_5b(); } /* DB DD */
+OP(dd,5c) { m_R++; _E = _HX; } /* LD E,HX */
+OP(dd,5d) { m_R++; _E = _LX; } /* LD E,LX */
+OP(dd,5e) { m_R++; EAX(); _E = RM(m_ea); } /* LD E,(IX+o) */
+OP(dd,5f) { illegal_1(); op_5f(); } /* DB DD */
+
+OP(dd,60) { m_R++; _HX = _B; } /* LD HX,B */
+OP(dd,61) { m_R++; _HX = _C; } /* LD HX,C */
+OP(dd,62) { m_R++; _HX = _D; } /* LD HX,D */
+OP(dd,63) { m_R++; _HX = _E; } /* LD HX,E */
+OP(dd,64) { } /* LD HX,HX */
+OP(dd,65) { m_R++; _HX = _LX; } /* LD HX,LX */
+OP(dd,66) { m_R++; EAX(); _H = RM(m_ea); } /* LD H,(IX+o) */
+OP(dd,67) { m_R++; _HX = _A; } /* LD HX,A */
+
+OP(dd,68) { m_R++; _LX = _B; } /* LD LX,B */
+OP(dd,69) { m_R++; _LX = _C; } /* LD LX,C */
+OP(dd,6a) { m_R++; _LX = _D; } /* LD LX,D */
+OP(dd,6b) { m_R++; _LX = _E; } /* LD LX,E */
+OP(dd,6c) { m_R++; _LX = _HX; } /* LD LX,HX */
+OP(dd,6d) { } /* LD LX,LX */
+OP(dd,6e) { m_R++; EAX(); _L = RM(m_ea); } /* LD L,(IX+o) */
+OP(dd,6f) { m_R++; _LX = _A; } /* LD LX,A */
+
+OP(dd,70) { m_R++; EAX(); WM( m_ea, _B ); } /* LD (IX+o),B */
+OP(dd,71) { m_R++; EAX(); WM( m_ea, _C ); } /* LD (IX+o),C */
+OP(dd,72) { m_R++; EAX(); WM( m_ea, _D ); } /* LD (IX+o),D */
+OP(dd,73) { m_R++; EAX(); WM( m_ea, _E ); } /* LD (IX+o),E */
+OP(dd,74) { m_R++; EAX(); WM( m_ea, _H ); } /* LD (IX+o),H */
+OP(dd,75) { m_R++; EAX(); WM( m_ea, _L ); } /* LD (IX+o),L */
+OP(dd,76) { illegal_1(); op_76(); } /* DB DD */
+OP(dd,77) { m_R++; EAX(); WM( m_ea, _A ); } /* LD (IX+o),A */
+
+OP(dd,78) { illegal_1(); op_78(); } /* DB DD */
+OP(dd,79) { illegal_1(); op_79(); } /* DB DD */
+OP(dd,7a) { illegal_1(); op_7a(); } /* DB DD */
+OP(dd,7b) { illegal_1(); op_7b(); } /* DB DD */
+OP(dd,7c) { m_R++; _A = _HX; } /* LD A,HX */
+OP(dd,7d) { m_R++; _A = _LX; } /* LD A,LX */
+OP(dd,7e) { m_R++; EAX(); _A = RM(m_ea); } /* LD A,(IX+o) */
+OP(dd,7f) { illegal_1(); op_7f(); } /* DB DD */
+
+OP(dd,80) { illegal_1(); op_80(); } /* DB DD */
+OP(dd,81) { illegal_1(); op_81(); } /* DB DD */
+OP(dd,82) { illegal_1(); op_82(); } /* DB DD */
+OP(dd,83) { illegal_1(); op_83(); } /* DB DD */
+OP(dd,84) { m_R++; ADD(_HX); } /* ADD A,HX */
+OP(dd,85) { m_R++; ADD(_LX); } /* ADD A,LX */
+OP(dd,86) { m_R++; EAX(); ADD(RM(m_ea)); } /* ADD A,(IX+o) */
+OP(dd,87) { illegal_1(); op_87(); } /* DB DD */
+
+OP(dd,88) { illegal_1(); op_88(); } /* DB DD */
+OP(dd,89) { illegal_1(); op_89(); } /* DB DD */
+OP(dd,8a) { illegal_1(); op_8a(); } /* DB DD */
+OP(dd,8b) { illegal_1(); op_8b(); } /* DB DD */
+OP(dd,8c) { m_R++; ADC(_HX); } /* ADC A,HX */
+OP(dd,8d) { m_R++; ADC(_LX); } /* ADC A,LX */
+OP(dd,8e) { m_R++; EAX(); ADC(RM(m_ea)); } /* ADC A,(IX+o) */
+OP(dd,8f) { illegal_1(); op_8f(); } /* DB DD */
+
+OP(dd,90) { illegal_1(); op_90(); } /* DB DD */
+OP(dd,91) { illegal_1(); op_91(); } /* DB DD */
+OP(dd,92) { illegal_1(); op_92(); } /* DB DD */
+OP(dd,93) { illegal_1(); op_93(); } /* DB DD */
+OP(dd,94) { m_R++; SUB(_HX); } /* SUB HX */
+OP(dd,95) { m_R++; SUB(_LX); } /* SUB LX */
+OP(dd,96) { m_R++; EAX(); SUB(RM(m_ea)); } /* SUB (IX+o) */
+OP(dd,97) { illegal_1(); op_97(); } /* DB DD */
+
+OP(dd,98) { illegal_1(); op_98(); } /* DB DD */
+OP(dd,99) { illegal_1(); op_99(); } /* DB DD */
+OP(dd,9a) { illegal_1(); op_9a(); } /* DB DD */
+OP(dd,9b) { illegal_1(); op_9b(); } /* DB DD */
+OP(dd,9c) { m_R++; SBC(_HX); } /* SBC A,HX */
+OP(dd,9d) { m_R++; SBC(_LX); } /* SBC A,LX */
+OP(dd,9e) { m_R++; EAX(); SBC(RM(m_ea)); } /* SBC A,(IX+o) */
+OP(dd,9f) { illegal_1(); op_9f(); } /* DB DD */
+
+OP(dd,a0) { illegal_1(); op_a0(); } /* DB DD */
+OP(dd,a1) { illegal_1(); op_a1(); } /* DB DD */
+OP(dd,a2) { illegal_1(); op_a2(); } /* DB DD */
+OP(dd,a3) { illegal_1(); op_a3(); } /* DB DD */
+OP(dd,a4) { m_R++; AND(_HX); } /* AND HX */
+OP(dd,a5) { m_R++; AND(_LX); } /* AND LX */
+OP(dd,a6) { m_R++; EAX(); AND(RM(m_ea)); } /* AND (IX+o) */
+OP(dd,a7) { illegal_1(); op_a7(); } /* DB DD */
+
+OP(dd,a8) { illegal_1(); op_a8(); } /* DB DD */
+OP(dd,a9) { illegal_1(); op_a9(); } /* DB DD */
+OP(dd,aa) { illegal_1(); op_aa(); } /* DB DD */
+OP(dd,ab) { illegal_1(); op_ab(); } /* DB DD */
+OP(dd,ac) { m_R++; XOR(_HX); } /* XOR HX */
+OP(dd,ad) { m_R++; XOR(_LX); } /* XOR LX */
+OP(dd,ae) { m_R++; EAX(); XOR(RM(m_ea)); } /* XOR (IX+o) */
+OP(dd,af) { illegal_1(); op_af(); } /* DB DD */
+
+OP(dd,b0) { illegal_1(); op_b0(); } /* DB DD */
+OP(dd,b1) { illegal_1(); op_b1(); } /* DB DD */
+OP(dd,b2) { illegal_1(); op_b2(); } /* DB DD */
+OP(dd,b3) { illegal_1(); op_b3(); } /* DB DD */
+OP(dd,b4) { m_R++; OR(_HX); } /* OR HX */
+OP(dd,b5) { m_R++; OR(_LX); } /* OR LX */
+OP(dd,b6) { m_R++; EAX(); OR(RM(m_ea)); } /* OR (IX+o) */
+OP(dd,b7) { illegal_1(); op_b7(); } /* DB DD */
+
+OP(dd,b8) { illegal_1(); op_b8(); } /* DB DD */
+OP(dd,b9) { illegal_1(); op_b9(); } /* DB DD */
+OP(dd,ba) { illegal_1(); op_ba(); } /* DB DD */
+OP(dd,bb) { illegal_1(); op_bb(); } /* DB DD */
+OP(dd,bc) { m_R++; CP(_HX); } /* CP HX */
+OP(dd,bd) { m_R++; CP(_LX); } /* CP LX */
+OP(dd,be) { m_R++; EAX(); CP(RM(m_ea)); } /* CP (IX+o) */
+OP(dd,bf) { illegal_1(); op_bf(); } /* DB DD */
+
+OP(dd,c0) { illegal_1(); op_c0(); } /* DB DD */
+OP(dd,c1) { illegal_1(); op_c1(); } /* DB DD */
+OP(dd,c2) { illegal_1(); op_c2(); } /* DB DD */
+OP(dd,c3) { illegal_1(); op_c3(); } /* DB DD */
+OP(dd,c4) { illegal_1(); op_c4(); } /* DB DD */
+OP(dd,c5) { illegal_1(); op_c5(); } /* DB DD */
+OP(dd,c6) { illegal_1(); op_c6(); } /* DB DD */
+OP(dd,c7) { illegal_1(); op_c7(); } /* DB DD */
+
+OP(dd,c8) { illegal_1(); op_c8(); } /* DB DD */
+OP(dd,c9) { illegal_1(); op_c9(); } /* DB DD */
+OP(dd,ca) { illegal_1(); op_ca(); } /* DB DD */
+OP(dd,cb) { m_R++; EAX(); m_extra_cycles += exec_xycb(ARG()); } /* ** DD CB xx */
+OP(dd,cc) { illegal_1(); op_cc(); } /* DB DD */
+OP(dd,cd) { illegal_1(); op_cd(); } /* DB DD */
+OP(dd,ce) { illegal_1(); op_ce(); } /* DB DD */
+OP(dd,cf) { illegal_1(); op_cf(); } /* DB DD */
+
+OP(dd,d0) { illegal_1(); op_d0(); } /* DB DD */
+OP(dd,d1) { illegal_1(); op_d1(); } /* DB DD */
+OP(dd,d2) { illegal_1(); op_d2(); } /* DB DD */
+OP(dd,d3) { illegal_1(); op_d3(); } /* DB DD */
+OP(dd,d4) { illegal_1(); op_d4(); } /* DB DD */
+OP(dd,d5) { illegal_1(); op_d5(); } /* DB DD */
+OP(dd,d6) { illegal_1(); op_d6(); } /* DB DD */
+OP(dd,d7) { illegal_1(); op_d7(); } /* DB DD */
+
+OP(dd,d8) { illegal_1(); op_d8(); } /* DB DD */
+OP(dd,d9) { illegal_1(); op_d9(); } /* DB DD */
+OP(dd,da) { illegal_1(); op_da(); } /* DB DD */
+OP(dd,db) { illegal_1(); op_db(); } /* DB DD */
+OP(dd,dc) { illegal_1(); op_dc(); } /* DB DD */
+OP(dd,dd) { illegal_1(); op_dd(); } /* DB DD */
+OP(dd,de) { illegal_1(); op_de(); } /* DB DD */
+OP(dd,df) { illegal_1(); op_df(); } /* DB DD */
+
+OP(dd,e0) { illegal_1(); op_e0(); } /* DB DD */
+OP(dd,e1) { m_R++; POP(IX); } /* POP IX */
+OP(dd,e2) { illegal_1(); op_e2(); } /* DB DD */
+OP(dd,e3) { m_R++; EXSP(IX); } /* EX (SP),IX */
+OP(dd,e4) { illegal_1(); op_e4(); } /* DB DD */
+OP(dd,e5) { m_R++; PUSH( IX ); } /* PUSH IX */
+OP(dd,e6) { illegal_1(); op_e6(); } /* DB DD */
+OP(dd,e7) { illegal_1(); op_e7(); } /* DB DD */
+
+OP(dd,e8) { illegal_1(); op_e8(); } /* DB DD */
+OP(dd,e9) { m_R++; _PC = _IX; } /* JP (IX) */
+OP(dd,ea) { illegal_1(); op_ea(); } /* DB DD */
+OP(dd,eb) { illegal_1(); op_eb(); } /* DB DD */
+OP(dd,ec) { illegal_1(); op_ec(); } /* DB DD */
+OP(dd,ed) { illegal_1(); op_ed(); } /* DB DD */
+OP(dd,ee) { illegal_1(); op_ee(); } /* DB DD */
+OP(dd,ef) { illegal_1(); op_ef(); } /* DB DD */
+
+OP(dd,f0) { illegal_1(); op_f0(); } /* DB DD */
+OP(dd,f1) { illegal_1(); op_f1(); } /* DB DD */
+OP(dd,f2) { illegal_1(); op_f2(); } /* DB DD */
+OP(dd,f3) { illegal_1(); op_f3(); } /* DB DD */
+OP(dd,f4) { illegal_1(); op_f4(); } /* DB DD */
+OP(dd,f5) { illegal_1(); op_f5(); } /* DB DD */
+OP(dd,f6) { illegal_1(); op_f6(); } /* DB DD */
+OP(dd,f7) { illegal_1(); op_f7(); } /* DB DD */
+
+OP(dd,f8) { illegal_1(); op_f8(); } /* DB DD */
+OP(dd,f9) { m_R++; _SP = _IX; } /* LD SP,IX */
+OP(dd,fa) { illegal_1(); op_fa(); } /* DB DD */
+OP(dd,fb) { illegal_1(); op_fb(); } /* DB DD */
+OP(dd,fc) { illegal_1(); op_fc(); } /* DB DD */
+OP(dd,fd) { illegal_1(); op_fd(); } /* DB DD */
+OP(dd,fe) { illegal_1(); op_fe(); } /* DB DD */
+OP(dd,ff) { illegal_1(); op_ff(); } /* DB DD */
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+OP(illegal,2)
+{
+ logerror("Z180 '%s' ill. opcode $ed $%02x\n",
+ tag(), m_ocache_read_byte((_PCD-1)&0xffff));
+}
+
+/**********************************************************
+ * special opcodes (ED prefix)
+ **********************************************************/
+OP(ed,00) { unsigned n = ARG(); _B = IN( n ); } /* IN0 B,(n) */
+OP(ed,01) { unsigned n = ARG(); OUT( n, _B ); } /* OUT0 (n),B */
+OP(ed,02) { illegal_2(); } /* DB ED */
+OP(ed,03) { illegal_2(); } /* DB ED */
+OP(ed,04) { TST( _B ); } /* TST B */
+OP(ed,05) { illegal_2(); } /* DB ED */
+OP(ed,06) { illegal_2(); } /* DB ED */
+OP(ed,07) { illegal_2(); } /* DB ED */
+
+OP(ed,08) { unsigned n = ARG(); _C = IN( n ); } /* IN0 C,(n) */
+OP(ed,09) { unsigned n = ARG(); OUT( n, _C ); } /* OUT0 (n),C */
+OP(ed,0a) { illegal_2(); } /* DB ED */
+OP(ed,0b) { illegal_2(); } /* DB ED */
+OP(ed,0c) { TST( _C ); } /* TST C */
+OP(ed,0d) { illegal_2(); } /* DB ED */
+OP(ed,0e) { illegal_2(); } /* DB ED */
+OP(ed,0f) { illegal_2(); } /* DB ED */
+
+OP(ed,10) { unsigned n = ARG(); _D = IN( n ); } /* IN0 D,(n) */
+OP(ed,11) { unsigned n = ARG(); OUT( n, _D ); } /* OUT0 (n),D */
+OP(ed,12) { illegal_2(); } /* DB ED */
+OP(ed,13) { illegal_2(); } /* DB ED */
+OP(ed,14) { TST( _D ); } /* TST D */
+OP(ed,15) { illegal_2(); } /* DB ED */
+OP(ed,16) { illegal_2(); } /* DB ED */
+OP(ed,17) { illegal_2(); } /* DB ED */
+
+OP(ed,18) { unsigned n = ARG(); _E = IN( n ); } /* IN0 E,(n) */
+OP(ed,19) { unsigned n = ARG(); OUT( n, _E ); } /* OUT0 (n),E */
+OP(ed,1a) { illegal_2(); } /* DB ED */
+OP(ed,1b) { illegal_2(); } /* DB ED */
+OP(ed,1c) { TST( _E ); } /* TST E */
+OP(ed,1d) { illegal_2(); } /* DB ED */
+OP(ed,1e) { illegal_2(); } /* DB ED */
+OP(ed,1f) { illegal_2(); } /* DB ED */
+
+OP(ed,20) { unsigned n = ARG(); _H = IN( n ); } /* IN0 H,(n) */
+OP(ed,21) { unsigned n = ARG(); OUT( n, _H ); } /* OUT0 (n),H */
+OP(ed,22) { illegal_2(); } /* DB ED */
+OP(ed,23) { illegal_2(); } /* DB ED */
+OP(ed,24) { TST( _H ); } /* TST H */
+OP(ed,25) { illegal_2(); } /* DB ED */
+OP(ed,26) { illegal_2(); } /* DB ED */
+OP(ed,27) { illegal_2(); } /* DB ED */
+
+OP(ed,28) { unsigned n = ARG(); _L = IN( n ); } /* IN0 L,(n) */
+OP(ed,29) { unsigned n = ARG(); OUT( n, _L ); } /* OUT0 (n),L */
+OP(ed,2a) { illegal_2(); } /* DB ED */
+OP(ed,2b) { illegal_2(); } /* DB ED */
+OP(ed,2c) { TST( _L ); } /* TST L */
+OP(ed,2d) { illegal_2(); } /* DB ED */
+OP(ed,2e) { illegal_2(); } /* DB ED */
+OP(ed,2f) { illegal_2(); } /* DB ED */
+
+OP(ed,30) { unsigned n = ARG(); IN( n ); } /* IN0 (n) */
+OP(ed,31) { unsigned n = ARG(); OUT( n, 0 ); } /* OUT0 (n) */
+OP(ed,32) { illegal_2(); } /* DB ED */
+OP(ed,33) { illegal_2(); } /* DB ED */
+OP(ed,34) { TST( RM(_HL) ); } /* TST (HL) */
+OP(ed,35) { illegal_2(); } /* DB ED */
+OP(ed,36) { illegal_2(); } /* DB ED */
+OP(ed,37) { illegal_2(); } /* DB ED */
+
+OP(ed,38) { unsigned n = ARG(); _A = IN( n ); } /* IN0 A,(n) */
+OP(ed,39) { unsigned n = ARG(); OUT( n, _A ); } /* OUT0 (n),A */
+OP(ed,3a) { illegal_2(); } /* DB ED */
+OP(ed,3b) { illegal_2(); } /* DB ED */
+OP(ed,3c) { TST( _A ); } /* TST A */
+OP(ed,3d) { illegal_2(); } /* DB ED */
+OP(ed,3e) { illegal_2(); } /* DB ED */
+OP(ed,3f) { illegal_2(); } /* DB ED */
+
+OP(ed,40) { _B = IN(_BC); _F = (_F & CF) | SZP[_B]; } /* IN B,(C) */
+OP(ed,41) { OUT(_BC,_B); } /* OUT (C),B */
+OP(ed,42) { SBC16( BC ); } /* SBC HL,BC */
+OP(ed,43) { m_ea = ARG16(); WM16( m_ea, &m_BC ); } /* LD (w),BC */
+OP(ed,44) { NEG; } /* NEG */
+OP(ed,45) { RETN; } /* RETN; */
+OP(ed,46) { m_IM = 0; } /* IM 0 */
+OP(ed,47) { LD_I_A; } /* LD I,A */
+
+OP(ed,48) { _C = IN(_BC); _F = (_F & CF) | SZP[_C]; } /* IN C,(C) */
+OP(ed,49) { OUT(_BC,_C); } /* OUT (C),C */
+OP(ed,4a) { ADC16( BC ); } /* ADC HL,BC */
+OP(ed,4b) { m_ea = ARG16(); RM16( m_ea, &m_BC ); } /* LD BC,(w) */
+OP(ed,4c) { MLT( BC ); } /* MLT BC */
+OP(ed,4d) { RETI; } /* RETI */
+OP(ed,4e) { m_IM = 0; } /* IM 0 */
+OP(ed,4f) { LD_R_A; } /* LD R,A */
+
+OP(ed,50) { _D = IN(_BC); _F = (_F & CF) | SZP[_D]; } /* IN D,(C) */
+OP(ed,51) { OUT(_BC,_D); } /* OUT (C),D */
+OP(ed,52) { SBC16( DE ); } /* SBC HL,DE */
+OP(ed,53) { m_ea = ARG16(); WM16( m_ea, &m_DE ); } /* LD (w),DE */
+OP(ed,54) { NEG; } /* NEG */
+OP(ed,55) { RETN; } /* RETN; */
+OP(ed,56) { m_IM = 1; } /* IM 1 */
+OP(ed,57) { LD_A_I; } /* LD A,I */
+
+OP(ed,58) { _E = IN(_BC); _F = (_F & CF) | SZP[_E]; } /* IN E,(C) */
+OP(ed,59) { OUT(_BC,_E); } /* OUT (C),E */
+OP(ed,5a) { ADC16( DE ); } /* ADC HL,DE */
+OP(ed,5b) { m_ea = ARG16(); RM16( m_ea, &m_DE ); } /* LD DE,(w) */
+OP(ed,5c) { MLT( DE ); } /* MLT DE */
+OP(ed,5d) { RETI; } /* RETI */
+OP(ed,5e) { m_IM = 2; } /* IM 2 */
+OP(ed,5f) { LD_A_R; } /* LD A,R */
+
+OP(ed,60) { _H = IN(_BC); _F = (_F & CF) | SZP[_H]; } /* IN H,(C) */
+OP(ed,61) { OUT(_BC,_H); } /* OUT (C),H */
+OP(ed,62) { SBC16( HL ); } /* SBC HL,HL */
+OP(ed,63) { m_ea = ARG16(); WM16( m_ea, &m_HL ); } /* LD (w),HL */
+OP(ed,64) { unsigned m = ARG(); TST( m ); } /* TST m */
+OP(ed,65) { RETN; } /* RETN; */
+OP(ed,66) { m_IM = 0; } /* IM 0 */
+OP(ed,67) { RRD; } /* RRD (HL) */
+
+OP(ed,68) { _L = IN(_BC); _F = (_F & CF) | SZP[_L]; } /* IN L,(C) */
+OP(ed,69) { OUT(_BC,_L); } /* OUT (C),L */
+OP(ed,6a) { ADC16( HL ); } /* ADC HL,HL */
+OP(ed,6b) { m_ea = ARG16(); RM16( m_ea, &m_HL ); } /* LD HL,(w) */
+OP(ed,6c) { MLT( HL ); } /* MLT HL */
+OP(ed,6d) { RETI; } /* RETI */
+OP(ed,6e) { m_IM = 0; } /* IM 0 */
+OP(ed,6f) { RLD; } /* RLD (HL) */
+
+OP(ed,70) { uint8_t res = IN(_BC); _F = (_F & CF) | SZP[res]; } /* IN 0,(C) */
+OP(ed,71) { OUT(_BC,0); } /* OUT (C),0 */
+OP(ed,72) { SBC16( SP ); } /* SBC HL,SP */
+OP(ed,73) { m_ea = ARG16(); WM16( m_ea, &m_SP ); } /* LD (w),SP */
+OP(ed,74) { unsigned m = ARG(); _F = (_F & CF) | SZP[IN(_C) & m]; } /* TSTIO m */
+OP(ed,75) { RETN; } /* RETN; */
+OP(ed,76) { SLP; } /* SLP */
+OP(ed,77) { illegal_2(); } /* DB ED,77 */
+
+OP(ed,78) { _A = IN(_BC); _F = (_F & CF) | SZP[_A]; } /* IN E,(C) */
+OP(ed,79) { OUT(_BC,_A); } /* OUT (C),E */
+OP(ed,7a) { ADC16( SP ); } /* ADC HL,SP */
+OP(ed,7b) { m_ea = ARG16(); RM16( m_ea, &m_SP ); } /* LD SP,(w) */
+OP(ed,7c) { MLT( SP ); } /* MLT SP */
+OP(ed,7d) { RETI; } /* RETI */
+OP(ed,7e) { m_IM = 2; } /* IM 2 */
+OP(ed,7f) { illegal_2(); } /* DB ED,7F */
+
+OP(ed,80) { illegal_2(); } /* DB ED */
+OP(ed,81) { illegal_2(); } /* DB ED */
+OP(ed,82) { illegal_2(); } /* DB ED */
+OP(ed,83) { OTIM; } /* OTIM */
+OP(ed,84) { illegal_2(); } /* DB ED */
+OP(ed,85) { illegal_2(); } /* DB ED */
+OP(ed,86) { illegal_2(); } /* DB ED */
+OP(ed,87) { illegal_2(); } /* DB ED */
+
+OP(ed,88) { illegal_2(); } /* DB ED */
+OP(ed,89) { illegal_2(); } /* DB ED */
+OP(ed,8a) { illegal_2(); } /* DB ED */
+OP(ed,8b) { OTDM; } /* OTDM */
+OP(ed,8c) { illegal_2(); } /* DB ED */
+OP(ed,8d) { illegal_2(); } /* DB ED */
+OP(ed,8e) { illegal_2(); } /* DB ED */
+OP(ed,8f) { illegal_2(); } /* DB ED */
+
+OP(ed,90) { illegal_2(); } /* DB ED */
+OP(ed,91) { illegal_2(); } /* DB ED */
+OP(ed,92) { illegal_2(); } /* DB ED */
+OP(ed,93) { OTIMR; } /* OTIMR */
+OP(ed,94) { illegal_2(); } /* DB ED */
+OP(ed,95) { illegal_2(); } /* DB ED */
+OP(ed,96) { illegal_2(); } /* DB ED */
+OP(ed,97) { illegal_2(); } /* DB ED */
+
+OP(ed,98) { illegal_2(); } /* DB ED */
+OP(ed,99) { illegal_2(); } /* DB ED */
+OP(ed,9a) { illegal_2(); } /* DB ED */
+OP(ed,9b) { OTDMR; } /* OTDMR */
+OP(ed,9c) { illegal_2(); } /* DB ED */
+OP(ed,9d) { illegal_2(); } /* DB ED */
+OP(ed,9e) { illegal_2(); } /* DB ED */
+OP(ed,9f) { illegal_2(); } /* DB ED */
+
+OP(ed,a0) { LDI; } /* LDI */
+OP(ed,a1) { CPI; } /* CPI */
+OP(ed,a2) { INI; } /* INI */
+OP(ed,a3) { OUTI; } /* OUTI */
+OP(ed,a4) { illegal_2(); } /* DB ED */
+OP(ed,a5) { illegal_2(); } /* DB ED */
+OP(ed,a6) { illegal_2(); } /* DB ED */
+OP(ed,a7) { illegal_2(); } /* DB ED */
+
+OP(ed,a8) { LDD; } /* LDD */
+OP(ed,a9) { CPD; } /* CPD */
+OP(ed,aa) { IND; } /* IND */
+OP(ed,ab) { OUTD; } /* OUTD */
+OP(ed,ac) { illegal_2(); } /* DB ED */
+OP(ed,ad) { illegal_2(); } /* DB ED */
+OP(ed,ae) { illegal_2(); } /* DB ED */
+OP(ed,af) { illegal_2(); } /* DB ED */
+
+OP(ed,b0) { LDIR; } /* LDIR */
+OP(ed,b1) { CPIR; } /* CPIR */
+OP(ed,b2) { INIR; } /* INIR */
+OP(ed,b3) { OTIR; } /* OTIR */
+OP(ed,b4) { illegal_2(); } /* DB ED */
+OP(ed,b5) { illegal_2(); } /* DB ED */
+OP(ed,b6) { illegal_2(); } /* DB ED */
+OP(ed,b7) { illegal_2(); } /* DB ED */
+
+OP(ed,b8) { LDDR; } /* LDDR */
+OP(ed,b9) { CPDR; } /* CPDR */
+OP(ed,ba) { INDR; } /* INDR */
+OP(ed,bb) { OTDR; } /* OTDR */
+OP(ed,bc) { illegal_2(); } /* DB ED */
+OP(ed,bd) { illegal_2(); } /* DB ED */
+OP(ed,be) { illegal_2(); } /* DB ED */
+OP(ed,bf) { illegal_2(); } /* DB ED */
+
+OP(ed,c0) { illegal_2(); } /* DB ED */
+OP(ed,c1) { illegal_2(); } /* DB ED */
+OP(ed,c2) { illegal_2(); } /* DB ED */
+OP(ed,c3) { illegal_2(); } /* DB ED */
+OP(ed,c4) { illegal_2(); } /* DB ED */
+OP(ed,c5) { illegal_2(); } /* DB ED */
+OP(ed,c6) { illegal_2(); } /* DB ED */
+OP(ed,c7) { illegal_2(); } /* DB ED */
+
+OP(ed,c8) { illegal_2(); } /* DB ED */
+OP(ed,c9) { illegal_2(); } /* DB ED */
+OP(ed,ca) { illegal_2(); } /* DB ED */
+OP(ed,cb) { illegal_2(); } /* DB ED */
+OP(ed,cc) { illegal_2(); } /* DB ED */
+OP(ed,cd) { illegal_2(); } /* DB ED */
+OP(ed,ce) { illegal_2(); } /* DB ED */
+OP(ed,cf) { illegal_2(); } /* DB ED */
+
+OP(ed,d0) { illegal_2(); } /* DB ED */
+OP(ed,d1) { illegal_2(); } /* DB ED */
+OP(ed,d2) { illegal_2(); } /* DB ED */
+OP(ed,d3) { illegal_2(); } /* DB ED */
+OP(ed,d4) { illegal_2(); } /* DB ED */
+OP(ed,d5) { illegal_2(); } /* DB ED */
+OP(ed,d6) { illegal_2(); } /* DB ED */
+OP(ed,d7) { illegal_2(); } /* DB ED */
+
+OP(ed,d8) { illegal_2(); } /* DB ED */
+OP(ed,d9) { illegal_2(); } /* DB ED */
+OP(ed,da) { illegal_2(); } /* DB ED */
+OP(ed,db) { illegal_2(); } /* DB ED */
+OP(ed,dc) { illegal_2(); } /* DB ED */
+OP(ed,dd) { illegal_2(); } /* DB ED */
+OP(ed,de) { illegal_2(); } /* DB ED */
+OP(ed,df) { illegal_2(); } /* DB ED */
+
+OP(ed,e0) { illegal_2(); } /* DB ED */
+OP(ed,e1) { illegal_2(); } /* DB ED */
+OP(ed,e2) { illegal_2(); } /* DB ED */
+OP(ed,e3) { illegal_2(); } /* DB ED */
+OP(ed,e4) { illegal_2(); } /* DB ED */
+OP(ed,e5) { illegal_2(); } /* DB ED */
+OP(ed,e6) { illegal_2(); } /* DB ED */
+OP(ed,e7) { illegal_2(); } /* DB ED */
+
+OP(ed,e8) { illegal_2(); } /* DB ED */
+OP(ed,e9) { illegal_2(); } /* DB ED */
+OP(ed,ea) { illegal_2(); } /* DB ED */
+OP(ed,eb) { illegal_2(); } /* DB ED */
+OP(ed,ec) { illegal_2(); } /* DB ED */
+OP(ed,ed) { illegal_2(); } /* DB ED */
+OP(ed,ee) { illegal_2(); } /* DB ED */
+OP(ed,ef) { illegal_2(); } /* DB ED */
+
+OP(ed,f0) { illegal_2(); } /* DB ED */
+OP(ed,f1) { illegal_2(); } /* DB ED */
+OP(ed,f2) { illegal_2(); } /* DB ED */
+OP(ed,f3) { illegal_2(); } /* DB ED */
+OP(ed,f4) { illegal_2(); } /* DB ED */
+OP(ed,f5) { illegal_2(); } /* DB ED */
+OP(ed,f6) { illegal_2(); } /* DB ED */
+OP(ed,f7) { illegal_2(); } /* DB ED */
+
+OP(ed,f8) { illegal_2(); } /* DB ED */
+OP(ed,f9) { illegal_2(); } /* DB ED */
+OP(ed,fa) { illegal_2(); } /* DB ED */
+OP(ed,fb) { illegal_2(); } /* DB ED */
+OP(ed,fc) { illegal_2(); } /* DB ED */
+OP(ed,fd) { illegal_2(); } /* DB ED */
+OP(ed,fe) { illegal_2(); } /* DB ED */
+OP(ed,ff) { illegal_2(); } /* DB ED */
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+/**********************************************************
+ * IY register related opcodes (FD prefix)
+ **********************************************************/
+OP(fd,00) { illegal_1(); op_00(); } /* DB FD */
+OP(fd,01) { illegal_1(); op_01(); } /* DB FD */
+OP(fd,02) { illegal_1(); op_02(); } /* DB FD */
+OP(fd,03) { illegal_1(); op_03(); } /* DB FD */
+OP(fd,04) { illegal_1(); op_04(); } /* DB FD */
+OP(fd,05) { illegal_1(); op_05(); } /* DB FD */
+OP(fd,06) { illegal_1(); op_06(); } /* DB FD */
+OP(fd,07) { illegal_1(); op_07(); } /* DB FD */
+
+OP(fd,08) { illegal_1(); op_08(); } /* DB FD */
+OP(fd,09) { m_R++; ADD16(IY,BC); } /* ADD IY,BC */
+OP(fd,0a) { illegal_1(); op_0a(); } /* DB FD */
+OP(fd,0b) { illegal_1(); op_0b(); } /* DB FD */
+OP(fd,0c) { illegal_1(); op_0c(); } /* DB FD */
+OP(fd,0d) { illegal_1(); op_0d(); } /* DB FD */
+OP(fd,0e) { illegal_1(); op_0e(); } /* DB FD */
+OP(fd,0f) { illegal_1(); op_0f(); } /* DB FD */
+
+OP(fd,10) { illegal_1(); op_10(); } /* DB FD */
+OP(fd,11) { illegal_1(); op_11(); } /* DB FD */
+OP(fd,12) { illegal_1(); op_12(); } /* DB FD */
+OP(fd,13) { illegal_1(); op_13(); } /* DB FD */
+OP(fd,14) { illegal_1(); op_14(); } /* DB FD */
+OP(fd,15) { illegal_1(); op_15(); } /* DB FD */
+OP(fd,16) { illegal_1(); op_16(); } /* DB FD */
+OP(fd,17) { illegal_1(); op_17(); } /* DB FD */
+
+OP(fd,18) { illegal_1(); op_18(); } /* DB FD */
+OP(fd,19) { m_R++; ADD16(IY,DE); } /* ADD IY,DE */
+OP(fd,1a) { illegal_1(); op_1a(); } /* DB FD */
+OP(fd,1b) { illegal_1(); op_1b(); } /* DB FD */
+OP(fd,1c) { illegal_1(); op_1c(); } /* DB FD */
+OP(fd,1d) { illegal_1(); op_1d(); } /* DB FD */
+OP(fd,1e) { illegal_1(); op_1e(); } /* DB FD */
+OP(fd,1f) { illegal_1(); op_1f(); } /* DB FD */
+
+OP(fd,20) { illegal_1(); op_20(); } /* DB FD */
+OP(fd,21) { m_R++; _IY = ARG16(); } /* LD IY,w */
+OP(fd,22) { m_R++; m_ea = ARG16(); WM16( m_ea, &m_IY ); } /* LD (w),IY */
+OP(fd,23) { m_R++; _IY++; } /* INC IY */
+OP(fd,24) { m_R++; _HY = INC(_HY); } /* INC HY */
+OP(fd,25) { m_R++; _HY = DEC(_HY); } /* DEC HY */
+OP(fd,26) { m_R++; _HY = ARG(); } /* LD HY,n */
+OP(fd,27) { illegal_1(); op_27(); } /* DB FD */
+
+OP(fd,28) { illegal_1(); op_28(); } /* DB FD */
+OP(fd,29) { m_R++; ADD16(IY,IY); } /* ADD IY,IY */
+OP(fd,2a) { m_R++; m_ea = ARG16(); RM16( m_ea, &m_IY ); } /* LD IY,(w) */
+OP(fd,2b) { m_R++; _IY--; } /* DEC IY */
+OP(fd,2c) { m_R++; _LY = INC(_LY); } /* INC LY */
+OP(fd,2d) { m_R++; _LY = DEC(_LY); } /* DEC LY */
+OP(fd,2e) { m_R++; _LY = ARG(); } /* LD LY,n */
+OP(fd,2f) { illegal_1(); op_2f(); } /* DB FD */
+
+OP(fd,30) { illegal_1(); op_30(); } /* DB FD */
+OP(fd,31) { illegal_1(); op_31(); } /* DB FD */
+OP(fd,32) { illegal_1(); op_32(); } /* DB FD */
+OP(fd,33) { illegal_1(); op_33(); } /* DB FD */
+OP(fd,34) { m_R++; EAY(); WM( m_ea, INC(RM(m_ea)) ); } /* INC (IY+o) */
+OP(fd,35) { m_R++; EAY(); WM( m_ea, DEC(RM(m_ea)) ); } /* DEC (IY+o) */
+OP(fd,36) { m_R++; EAY(); WM( m_ea, ARG() ); } /* LD (IY+o),n */
+OP(fd,37) { illegal_1(); op_37(); } /* DB FD */
+
+OP(fd,38) { illegal_1(); op_38(); } /* DB FD */
+OP(fd,39) { m_R++; ADD16(IY,SP); } /* ADD IY,SP */
+OP(fd,3a) { illegal_1(); op_3a(); } /* DB FD */
+OP(fd,3b) { illegal_1(); op_3b(); } /* DB FD */
+OP(fd,3c) { illegal_1(); op_3c(); } /* DB FD */
+OP(fd,3d) { illegal_1(); op_3d(); } /* DB FD */
+OP(fd,3e) { illegal_1(); op_3e(); } /* DB FD */
+OP(fd,3f) { illegal_1(); op_3f(); } /* DB FD */
+
+OP(fd,40) { illegal_1(); op_40(); } /* DB FD */
+OP(fd,41) { illegal_1(); op_41(); } /* DB FD */
+OP(fd,42) { illegal_1(); op_42(); } /* DB FD */
+OP(fd,43) { illegal_1(); op_43(); } /* DB FD */
+OP(fd,44) { m_R++; _B = _HY; } /* LD B,HY */
+OP(fd,45) { m_R++; _B = _LY; } /* LD B,LY */
+OP(fd,46) { m_R++; EAY(); _B = RM(m_ea); } /* LD B,(IY+o) */
+OP(fd,47) { illegal_1(); op_47(); } /* DB FD */
+
+OP(fd,48) { illegal_1(); op_48(); } /* DB FD */
+OP(fd,49) { illegal_1(); op_49(); } /* DB FD */
+OP(fd,4a) { illegal_1(); op_4a(); } /* DB FD */
+OP(fd,4b) { illegal_1(); op_4b(); } /* DB FD */
+OP(fd,4c) { m_R++; _C = _HY; } /* LD C,HY */
+OP(fd,4d) { m_R++; _C = _LY; } /* LD C,LY */
+OP(fd,4e) { m_R++; EAY(); _C = RM(m_ea); } /* LD C,(IY+o) */
+OP(fd,4f) { illegal_1(); op_4f(); } /* DB FD */
+
+OP(fd,50) { illegal_1(); op_50(); } /* DB FD */
+OP(fd,51) { illegal_1(); op_51(); } /* DB FD */
+OP(fd,52) { illegal_1(); op_52(); } /* DB FD */
+OP(fd,53) { illegal_1(); op_53(); } /* DB FD */
+OP(fd,54) { m_R++; _D = _HY; } /* LD D,HY */
+OP(fd,55) { m_R++; _D = _LY; } /* LD D,LY */
+OP(fd,56) { m_R++; EAY(); _D = RM(m_ea); } /* LD D,(IY+o) */
+OP(fd,57) { illegal_1(); op_57(); } /* DB FD */
+
+OP(fd,58) { illegal_1(); op_58(); } /* DB FD */
+OP(fd,59) { illegal_1(); op_59(); } /* DB FD */
+OP(fd,5a) { illegal_1(); op_5a(); } /* DB FD */
+OP(fd,5b) { illegal_1(); op_5b(); } /* DB FD */
+OP(fd,5c) { m_R++; _E = _HY; } /* LD E,HY */
+OP(fd,5d) { m_R++; _E = _LY; } /* LD E,LY */
+OP(fd,5e) { m_R++; EAY(); _E = RM(m_ea); } /* LD E,(IY+o) */
+OP(fd,5f) { illegal_1(); op_5f(); } /* DB FD */
+
+OP(fd,60) { m_R++; _HY = _B; } /* LD HY,B */
+OP(fd,61) { m_R++; _HY = _C; } /* LD HY,C */
+OP(fd,62) { m_R++; _HY = _D; } /* LD HY,D */
+OP(fd,63) { m_R++; _HY = _E; } /* LD HY,E */
+OP(fd,64) { m_R++; } /* LD HY,HY */
+OP(fd,65) { m_R++; _HY = _LY; } /* LD HY,LY */
+OP(fd,66) { m_R++; EAY(); _H = RM(m_ea); } /* LD H,(IY+o) */
+OP(fd,67) { m_R++; _HY = _A; } /* LD HY,A */
+
+OP(fd,68) { m_R++; _LY = _B; } /* LD LY,B */
+OP(fd,69) { m_R++; _LY = _C; } /* LD LY,C */
+OP(fd,6a) { m_R++; _LY = _D; } /* LD LY,D */
+OP(fd,6b) { m_R++; _LY = _E; } /* LD LY,E */
+OP(fd,6c) { m_R++; _LY = _HY; } /* LD LY,HY */
+OP(fd,6d) { m_R++; } /* LD LY,LY */
+OP(fd,6e) { m_R++; EAY(); _L = RM(m_ea); } /* LD L,(IY+o) */
+OP(fd,6f) { m_R++; _LY = _A; } /* LD LY,A */
+
+OP(fd,70) { m_R++; EAY(); WM( m_ea, _B ); } /* LD (IY+o),B */
+OP(fd,71) { m_R++; EAY(); WM( m_ea, _C ); } /* LD (IY+o),C */
+OP(fd,72) { m_R++; EAY(); WM( m_ea, _D ); } /* LD (IY+o),D */
+OP(fd,73) { m_R++; EAY(); WM( m_ea, _E ); } /* LD (IY+o),E */
+OP(fd,74) { m_R++; EAY(); WM( m_ea, _H ); } /* LD (IY+o),H */
+OP(fd,75) { m_R++; EAY(); WM( m_ea, _L ); } /* LD (IY+o),L */
+OP(fd,76) { illegal_1(); op_76(); } /* DB FD */
+OP(fd,77) { m_R++; EAY(); WM( m_ea, _A ); } /* LD (IY+o),A */
+
+OP(fd,78) { illegal_1(); op_78(); } /* DB FD */
+OP(fd,79) { illegal_1(); op_79(); } /* DB FD */
+OP(fd,7a) { illegal_1(); op_7a(); } /* DB FD */
+OP(fd,7b) { illegal_1(); op_7b(); } /* DB FD */
+OP(fd,7c) { m_R++; _A = _HY; } /* LD A,HY */
+OP(fd,7d) { m_R++; _A = _LY; } /* LD A,LY */
+OP(fd,7e) { m_R++; EAY(); _A = RM(m_ea); } /* LD A,(IY+o) */
+OP(fd,7f) { illegal_1(); op_7f(); } /* DB FD */
+
+OP(fd,80) { illegal_1(); op_80(); } /* DB FD */
+OP(fd,81) { illegal_1(); op_81(); } /* DB FD */
+OP(fd,82) { illegal_1(); op_82(); } /* DB FD */
+OP(fd,83) { illegal_1(); op_83(); } /* DB FD */
+OP(fd,84) { m_R++; ADD(_HY); } /* ADD A,HY */
+OP(fd,85) { m_R++; ADD(_LY); } /* ADD A,LY */
+OP(fd,86) { m_R++; EAY(); ADD(RM(m_ea)); } /* ADD A,(IY+o) */
+OP(fd,87) { illegal_1(); op_87(); } /* DB FD */
+
+OP(fd,88) { illegal_1(); op_88(); } /* DB FD */
+OP(fd,89) { illegal_1(); op_89(); } /* DB FD */
+OP(fd,8a) { illegal_1(); op_8a(); } /* DB FD */
+OP(fd,8b) { illegal_1(); op_8b(); } /* DB FD */
+OP(fd,8c) { m_R++; ADC(_HY); } /* ADC A,HY */
+OP(fd,8d) { m_R++; ADC(_LY); } /* ADC A,LY */
+OP(fd,8e) { m_R++; EAY(); ADC(RM(m_ea)); } /* ADC A,(IY+o) */
+OP(fd,8f) { illegal_1(); op_8f(); } /* DB FD */
+
+OP(fd,90) { illegal_1(); op_90(); } /* DB FD */
+OP(fd,91) { illegal_1(); op_91(); } /* DB FD */
+OP(fd,92) { illegal_1(); op_92(); } /* DB FD */
+OP(fd,93) { illegal_1(); op_93(); } /* DB FD */
+OP(fd,94) { m_R++; SUB(_HY); } /* SUB HY */
+OP(fd,95) { m_R++; SUB(_LY); } /* SUB LY */
+OP(fd,96) { m_R++; EAY(); SUB(RM(m_ea)); } /* SUB (IY+o) */
+OP(fd,97) { illegal_1(); op_97(); } /* DB FD */
+
+OP(fd,98) { illegal_1(); op_98(); } /* DB FD */
+OP(fd,99) { illegal_1(); op_99(); } /* DB FD */
+OP(fd,9a) { illegal_1(); op_9a(); } /* DB FD */
+OP(fd,9b) { illegal_1(); op_9b(); } /* DB FD */
+OP(fd,9c) { m_R++; SBC(_HY); } /* SBC A,HY */
+OP(fd,9d) { m_R++; SBC(_LY); } /* SBC A,LY */
+OP(fd,9e) { m_R++; EAY(); SBC(RM(m_ea)); } /* SBC A,(IY+o) */
+OP(fd,9f) { illegal_1(); op_9f(); } /* DB FD */
+
+OP(fd,a0) { illegal_1(); op_a0(); } /* DB FD */
+OP(fd,a1) { illegal_1(); op_a1(); } /* DB FD */
+OP(fd,a2) { illegal_1(); op_a2(); } /* DB FD */
+OP(fd,a3) { illegal_1(); op_a3(); } /* DB FD */
+OP(fd,a4) { m_R++; AND(_HY); } /* AND HY */
+OP(fd,a5) { m_R++; AND(_LY); } /* AND LY */
+OP(fd,a6) { m_R++; EAY(); AND(RM(m_ea)); } /* AND (IY+o) */
+OP(fd,a7) { illegal_1(); op_a7(); } /* DB FD */
+
+OP(fd,a8) { illegal_1(); op_a8(); } /* DB FD */
+OP(fd,a9) { illegal_1(); op_a9(); } /* DB FD */
+OP(fd,aa) { illegal_1(); op_aa(); } /* DB FD */
+OP(fd,ab) { illegal_1(); op_ab(); } /* DB FD */
+OP(fd,ac) { m_R++; XOR(_HY); } /* XOR HY */
+OP(fd,ad) { m_R++; XOR(_LY); } /* XOR LY */
+OP(fd,ae) { m_R++; EAY(); XOR(RM(m_ea)); } /* XOR (IY+o) */
+OP(fd,af) { illegal_1(); op_af(); } /* DB FD */
+
+OP(fd,b0) { illegal_1(); op_b0(); } /* DB FD */
+OP(fd,b1) { illegal_1(); op_b1(); } /* DB FD */
+OP(fd,b2) { illegal_1(); op_b2(); } /* DB FD */
+OP(fd,b3) { illegal_1(); op_b3(); } /* DB FD */
+OP(fd,b4) { m_R++; OR(_HY); } /* OR HY */
+OP(fd,b5) { m_R++; OR(_LY); } /* OR LY */
+OP(fd,b6) { m_R++; EAY(); OR(RM(m_ea)); } /* OR (IY+o) */
+OP(fd,b7) { illegal_1(); op_b7(); } /* DB FD */
+
+OP(fd,b8) { illegal_1(); op_b8(); } /* DB FD */
+OP(fd,b9) { illegal_1(); op_b9(); } /* DB FD */
+OP(fd,ba) { illegal_1(); op_ba(); } /* DB FD */
+OP(fd,bb) { illegal_1(); op_bb(); } /* DB FD */
+OP(fd,bc) { m_R++; CP(_HY); } /* CP HY */
+OP(fd,bd) { m_R++; CP(_LY); } /* CP LY */
+OP(fd,be) { m_R++; EAY(); CP(RM(m_ea)); } /* CP (IY+o) */
+OP(fd,bf) { illegal_1(); op_bf(); } /* DB FD */
+
+OP(fd,c0) { illegal_1(); op_c0(); } /* DB FD */
+OP(fd,c1) { illegal_1(); op_c1(); } /* DB FD */
+OP(fd,c2) { illegal_1(); op_c2(); } /* DB FD */
+OP(fd,c3) { illegal_1(); op_c3(); } /* DB FD */
+OP(fd,c4) { illegal_1(); op_c4(); } /* DB FD */
+OP(fd,c5) { illegal_1(); op_c5(); } /* DB FD */
+OP(fd,c6) { illegal_1(); op_c6(); } /* DB FD */
+OP(fd,c7) { illegal_1(); op_c7(); } /* DB FD */
+
+OP(fd,c8) { illegal_1(); op_c8(); } /* DB FD */
+OP(fd,c9) { illegal_1(); op_c9(); } /* DB FD */
+OP(fd,ca) { illegal_1(); op_ca(); } /* DB FD */
+OP(fd,cb) { m_R++; EAY(); m_extra_cycles += exec_xycb(ARG()); } /* ** FD CB xx */
+OP(fd,cc) { illegal_1(); op_cc(); } /* DB FD */
+OP(fd,cd) { illegal_1(); op_cd(); } /* DB FD */
+OP(fd,ce) { illegal_1(); op_ce(); } /* DB FD */
+OP(fd,cf) { illegal_1(); op_cf(); } /* DB FD */
+
+OP(fd,d0) { illegal_1(); op_d0(); } /* DB FD */
+OP(fd,d1) { illegal_1(); op_d1(); } /* DB FD */
+OP(fd,d2) { illegal_1(); op_d2(); } /* DB FD */
+OP(fd,d3) { illegal_1(); op_d3(); } /* DB FD */
+OP(fd,d4) { illegal_1(); op_d4(); } /* DB FD */
+OP(fd,d5) { illegal_1(); op_d5(); } /* DB FD */
+OP(fd,d6) { illegal_1(); op_d6(); } /* DB FD */
+OP(fd,d7) { illegal_1(); op_d7(); } /* DB FD */
+
+OP(fd,d8) { illegal_1(); op_d8(); } /* DB FD */
+OP(fd,d9) { illegal_1(); op_d9(); } /* DB FD */
+OP(fd,da) { illegal_1(); op_da(); } /* DB FD */
+OP(fd,db) { illegal_1(); op_db(); } /* DB FD */
+OP(fd,dc) { illegal_1(); op_dc(); } /* DB FD */
+OP(fd,dd) { illegal_1(); op_dd(); } /* DB FD */
+OP(fd,de) { illegal_1(); op_de(); } /* DB FD */
+OP(fd,df) { illegal_1(); op_df(); } /* DB FD */
+
+OP(fd,e0) { illegal_1(); op_e0(); } /* DB FD */
+OP(fd,e1) { m_R++; POP(IY); } /* POP IY */
+OP(fd,e2) { illegal_1(); op_e2(); } /* DB FD */
+OP(fd,e3) { m_R++; EXSP(IY); } /* EX (SP),IY */
+OP(fd,e4) { illegal_1(); op_e4(); } /* DB FD */
+OP(fd,e5) { m_R++; PUSH( IY ); } /* PUSH IY */
+OP(fd,e6) { illegal_1(); op_e6(); } /* DB FD */
+OP(fd,e7) { illegal_1(); op_e7(); } /* DB FD */
+
+OP(fd,e8) { illegal_1(); op_e8(); } /* DB FD */
+OP(fd,e9) { m_R++; _PC = _IY; } /* JP (IY) */
+OP(fd,ea) { illegal_1(); op_ea(); } /* DB FD */
+OP(fd,eb) { illegal_1(); op_eb(); } /* DB FD */
+OP(fd,ec) { illegal_1(); op_ec(); } /* DB FD */
+OP(fd,ed) { illegal_1(); op_ed(); } /* DB FD */
+OP(fd,ee) { illegal_1(); op_ee(); } /* DB FD */
+OP(fd,ef) { illegal_1(); op_ef(); } /* DB FD */
+
+OP(fd,f0) { illegal_1(); op_f0(); } /* DB FD */
+OP(fd,f1) { illegal_1(); op_f1(); } /* DB FD */
+OP(fd,f2) { illegal_1(); op_f2(); } /* DB FD */
+OP(fd,f3) { illegal_1(); op_f3(); } /* DB FD */
+OP(fd,f4) { illegal_1(); op_f4(); } /* DB FD */
+OP(fd,f5) { illegal_1(); op_f5(); } /* DB FD */
+OP(fd,f6) { illegal_1(); op_f6(); } /* DB FD */
+OP(fd,f7) { illegal_1(); op_f7(); } /* DB FD */
+
+OP(fd,f8) { illegal_1(); op_f8(); } /* DB FD */
+OP(fd,f9) { m_R++; _SP = _IY; } /* LD SP,IY */
+OP(fd,fa) { illegal_1(); op_fa(); } /* DB FD */
+OP(fd,fb) { illegal_1(); op_fb(); } /* DB FD */
+OP(fd,fc) { illegal_1(); op_fc(); } /* DB FD */
+OP(fd,fd) { illegal_1(); op_fd(); } /* DB FD */
+OP(fd,fe) { illegal_1(); op_fe(); } /* DB FD */
+OP(fd,ff) { illegal_1(); op_ff(); } /* DB FD */
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+/**********************************************************
+ * main opcodes
+ **********************************************************/
+OP(op,00) { } /* NOP */
+OP(op,01) { _BC = ARG16(); } /* LD BC,w */
+OP(op,02) { WM( _BC, _A ); } /* LD (BC),A */
+OP(op,03) { _BC++; } /* INC BC */
+OP(op,04) { _B = INC(_B); } /* INC B */
+OP(op,05) { _B = DEC(_B); } /* DEC B */
+OP(op,06) { _B = ARG(); } /* LD B,n */
+OP(op,07) { RLCA; } /* RLCA */
+
+OP(op,08) { EX_AF; } /* EX AF,AF' */
+OP(op,09) { ADD16(HL,BC); } /* ADD HL,BC */
+OP(op,0a) { _A = RM(_BC); } /* LD A,(BC) */
+OP(op,0b) { _BC--; } /* DEC BC */
+OP(op,0c) { _C = INC(_C); } /* INC C */
+OP(op,0d) { _C = DEC(_C); } /* DEC C */
+OP(op,0e) { _C = ARG(); } /* LD C,n */
+OP(op,0f) { RRCA; } /* RRCA */
+
+OP(op,10) { _B--; JR_COND( _B, 0x10 ); } /* DJNZ o */
+OP(op,11) { _DE = ARG16(); } /* LD DE,w */
+OP(op,12) { WM( _DE, _A ); } /* LD (DE),A */
+OP(op,13) { _DE++; } /* INC DE */
+OP(op,14) { _D = INC(_D); } /* INC D */
+OP(op,15) { _D = DEC(_D); } /* DEC D */
+OP(op,16) { _D = ARG(); } /* LD D,n */
+OP(op,17) { RLA; } /* RLA */
+
+OP(op,18) { JR(); } /* JR o */
+OP(op,19) { ADD16(HL,DE); } /* ADD HL,DE */
+OP(op,1a) { _A = RM(_DE); } /* LD A,(DE) */
+OP(op,1b) { _DE--; ; } /* DEC DE */
+OP(op,1c) { _E = INC(_E); } /* INC E */
+OP(op,1d) { _E = DEC(_E); } /* DEC E */
+OP(op,1e) { _E = ARG(); } /* LD E,n */
+OP(op,1f) { RRA; } /* RRA */
+
+OP(op,20) { JR_COND( !(_F & ZF), 0x20 ); } /* JR NZ,o */
+OP(op,21) { _HL = ARG16(); } /* LD HL,w */
+OP(op,22) { m_ea = ARG16(); WM16(m_ea, &m_HL ); } /* LD (w),HL */
+OP(op,23) { _HL++; } /* INC HL */
+OP(op,24) { _H = INC(_H); } /* INC H */
+OP(op,25) { _H = DEC(_H); } /* DEC H */
+OP(op,26) { _H = ARG(); } /* LD H,n */
+OP(op,27) { DAA; } /* DAA */
+
+OP(op,28) { JR_COND( _F & ZF, 0x28 ); } /* JR Z,o */
+OP(op,29) { ADD16(HL,HL); } /* ADD HL,HL */
+OP(op,2a) { m_ea = ARG16(); RM16(m_ea, &m_HL ); } /* LD HL,(w) */
+OP(op,2b) { _HL--; } /* DEC HL */
+OP(op,2c) { _L = INC(_L); } /* INC L */
+OP(op,2d) { _L = DEC(_L); } /* DEC L */
+OP(op,2e) { _L = ARG(); } /* LD L,n */
+OP(op,2f) { _A ^= 0xff; _F = (_F&(SF|ZF|PF|CF))|HF|NF|(_A&(YF|XF)); } /* CPL */
+
+OP(op,30) { JR_COND( !(_F & CF), 0x30 ); } /* JR NC,o */
+OP(op,31) { _SP = ARG16(); } /* LD SP,w */
+OP(op,32) { m_ea = ARG16(); WM( m_ea, _A ); } /* LD (w),A */
+OP(op,33) { _SP++; } /* INC SP */
+OP(op,34) { WM( _HL, INC(RM(_HL)) ); } /* INC (HL) */
+OP(op,35) { WM( _HL, DEC(RM(_HL)) ); } /* DEC (HL) */
+OP(op,36) { WM( _HL, ARG() ); } /* LD (HL),n */
+OP(op,37) { _F = (_F & (SF|ZF|PF)) | CF | (_A & (YF|XF)); } /* SCF */
+
+OP(op,38) { JR_COND( _F & CF, 0x38 ); } /* JR C,o */
+OP(op,39) { ADD16(HL,SP); } /* ADD HL,SP */
+OP(op,3a) { m_ea = ARG16(); _A = RM( m_ea ); } /* LD A,(w) */
+OP(op,3b) { _SP--; } /* DEC SP */
+OP(op,3c) { _A = INC(_A); } /* INC A */
+OP(op,3d) { _A = DEC(_A); } /* DEC A */
+OP(op,3e) { _A = ARG(); } /* LD A,n */
+OP(op,3f) { _F = ((_F&(SF|ZF|PF|CF))|((_F&CF)<<4)|(_A&(YF|XF)))^CF; } /* CCF */
+//OP(op,3f) { _F = ((_F & ~(HF|NF)) | ((_F & CF)<<4)) ^ CF; } /* CCF */
+
+OP(op,40) { } /* LD B,B */
+OP(op,41) { _B = _C; } /* LD B,C */
+OP(op,42) { _B = _D; } /* LD B,D */
+OP(op,43) { _B = _E; } /* LD B,E */
+OP(op,44) { _B = _H; } /* LD B,H */
+OP(op,45) { _B = _L; } /* LD B,L */
+OP(op,46) { _B = RM(_HL); } /* LD B,(HL) */
+OP(op,47) { _B = _A; } /* LD B,A */
+
+OP(op,48) { _C = _B; } /* LD C,B */
+OP(op,49) { } /* LD C,C */
+OP(op,4a) { _C = _D; } /* LD C,D */
+OP(op,4b) { _C = _E; } /* LD C,E */
+OP(op,4c) { _C = _H; } /* LD C,H */
+OP(op,4d) { _C = _L; } /* LD C,L */
+OP(op,4e) { _C = RM(_HL); } /* LD C,(HL) */
+OP(op,4f) { _C = _A; } /* LD C,A */
+
+OP(op,50) { _D = _B; } /* LD D,B */
+OP(op,51) { _D = _C; } /* LD D,C */
+OP(op,52) { } /* LD D,D */
+OP(op,53) { _D = _E; } /* LD D,E */
+OP(op,54) { _D = _H; } /* LD D,H */
+OP(op,55) { _D = _L; } /* LD D,L */
+OP(op,56) { _D = RM(_HL); } /* LD D,(HL) */
+OP(op,57) { _D = _A; } /* LD D,A */
+
+OP(op,58) { _E = _B; } /* LD E,B */
+OP(op,59) { _E = _C; } /* LD E,C */
+OP(op,5a) { _E = _D; } /* LD E,D */
+OP(op,5b) { } /* LD E,E */
+OP(op,5c) { _E = _H; } /* LD E,H */
+OP(op,5d) { _E = _L; } /* LD E,L */
+OP(op,5e) { _E = RM(_HL); } /* LD E,(HL) */
+OP(op,5f) { _E = _A; } /* LD E,A */
+
+OP(op,60) { _H = _B; } /* LD H,B */
+OP(op,61) { _H = _C; } /* LD H,C */
+OP(op,62) { _H = _D; } /* LD H,D */
+OP(op,63) { _H = _E; } /* LD H,E */
+OP(op,64) { } /* LD H,H */
+OP(op,65) { _H = _L; } /* LD H,L */
+OP(op,66) { _H = RM(_HL); } /* LD H,(HL) */
+OP(op,67) { _H = _A; } /* LD H,A */
+
+OP(op,68) { _L = _B; } /* LD L,B */
+OP(op,69) { _L = _C; } /* LD L,C */
+OP(op,6a) { _L = _D; } /* LD L,D */
+OP(op,6b) { _L = _E; } /* LD L,E */
+OP(op,6c) { _L = _H; } /* LD L,H */
+OP(op,6d) { } /* LD L,L */
+OP(op,6e) { _L = RM(_HL); } /* LD L,(HL) */
+OP(op,6f) { _L = _A; } /* LD L,A */
+
+OP(op,70) { WM( _HL, _B ); } /* LD (HL),B */
+OP(op,71) { WM( _HL, _C ); } /* LD (HL),C */
+OP(op,72) { WM( _HL, _D ); } /* LD (HL),D */
+OP(op,73) { WM( _HL, _E ); } /* LD (HL),E */
+OP(op,74) { WM( _HL, _H ); } /* LD (HL),H */
+OP(op,75) { WM( _HL, _L ); } /* LD (HL),L */
+OP(op,76) { ENTER_HALT(); } /* HALT */
+OP(op,77) { WM( _HL, _A ); } /* LD (HL),A */
+
+OP(op,78) { _A = _B; } /* LD A,B */
+OP(op,79) { _A = _C; } /* LD A,C */
+OP(op,7a) { _A = _D; } /* LD A,D */
+OP(op,7b) { _A = _E; } /* LD A,E */
+OP(op,7c) { _A = _H; } /* LD A,H */
+OP(op,7d) { _A = _L; } /* LD A,L */
+OP(op,7e) { _A = RM(_HL); } /* LD A,(HL) */
+OP(op,7f) { } /* LD A,A */
+
+OP(op,80) { ADD(_B); } /* ADD A,B */
+OP(op,81) { ADD(_C); } /* ADD A,C */
+OP(op,82) { ADD(_D); } /* ADD A,D */
+OP(op,83) { ADD(_E); } /* ADD A,E */
+OP(op,84) { ADD(_H); } /* ADD A,H */
+OP(op,85) { ADD(_L); } /* ADD A,L */
+OP(op,86) { ADD(RM(_HL)); } /* ADD A,(HL) */
+OP(op,87) { ADD(_A); } /* ADD A,A */
+
+OP(op,88) { ADC(_B); } /* ADC A,B */
+OP(op,89) { ADC(_C); } /* ADC A,C */
+OP(op,8a) { ADC(_D); } /* ADC A,D */
+OP(op,8b) { ADC(_E); } /* ADC A,E */
+OP(op,8c) { ADC(_H); } /* ADC A,H */
+OP(op,8d) { ADC(_L); } /* ADC A,L */
+OP(op,8e) { ADC(RM(_HL)); } /* ADC A,(HL) */
+OP(op,8f) { ADC(_A); } /* ADC A,A */
+
+OP(op,90) { SUB(_B); } /* SUB B */
+OP(op,91) { SUB(_C); } /* SUB C */
+OP(op,92) { SUB(_D); } /* SUB D */
+OP(op,93) { SUB(_E); } /* SUB E */
+OP(op,94) { SUB(_H); } /* SUB H */
+OP(op,95) { SUB(_L); } /* SUB L */
+OP(op,96) { SUB(RM(_HL)); } /* SUB (HL) */
+OP(op,97) { SUB(_A); } /* SUB A */
+
+OP(op,98) { SBC(_B); } /* SBC A,B */
+OP(op,99) { SBC(_C); } /* SBC A,C */
+OP(op,9a) { SBC(_D); } /* SBC A,D */
+OP(op,9b) { SBC(_E); } /* SBC A,E */
+OP(op,9c) { SBC(_H); } /* SBC A,H */
+OP(op,9d) { SBC(_L); } /* SBC A,L */
+OP(op,9e) { SBC(RM(_HL)); } /* SBC A,(HL) */
+OP(op,9f) { SBC(_A); } /* SBC A,A */
+
+OP(op,a0) { AND(_B); } /* AND B */
+OP(op,a1) { AND(_C); } /* AND C */
+OP(op,a2) { AND(_D); } /* AND D */
+OP(op,a3) { AND(_E); } /* AND E */
+OP(op,a4) { AND(_H); } /* AND H */
+OP(op,a5) { AND(_L); } /* AND L */
+OP(op,a6) { AND(RM(_HL)); } /* AND (HL) */
+OP(op,a7) { AND(_A); } /* AND A */
+
+OP(op,a8) { XOR(_B); } /* XOR B */
+OP(op,a9) { XOR(_C); } /* XOR C */
+OP(op,aa) { XOR(_D); } /* XOR D */
+OP(op,ab) { XOR(_E); } /* XOR E */
+OP(op,ac) { XOR(_H); } /* XOR H */
+OP(op,ad) { XOR(_L); } /* XOR L */
+OP(op,ae) { XOR(RM(_HL)); } /* XOR (HL) */
+OP(op,af) { XOR(_A); } /* XOR A */
+
+OP(op,b0) { OR(_B); } /* OR B */
+OP(op,b1) { OR(_C); } /* OR C */
+OP(op,b2) { OR(_D); } /* OR D */
+OP(op,b3) { OR(_E); } /* OR E */
+OP(op,b4) { OR(_H); } /* OR H */
+OP(op,b5) { OR(_L); } /* OR L */
+OP(op,b6) { OR(RM(_HL)); } /* OR (HL) */
+OP(op,b7) { OR(_A); } /* OR A */
+
+OP(op,b8) { CP(_B); } /* CP B */
+OP(op,b9) { CP(_C); } /* CP C */
+OP(op,ba) { CP(_D); } /* CP D */
+OP(op,bb) { CP(_E); } /* CP E */
+OP(op,bc) { CP(_H); } /* CP H */
+OP(op,bd) { CP(_L); } /* CP L */
+OP(op,be) { CP(RM(_HL)); } /* CP (HL) */
+OP(op,bf) { CP(_A); } /* CP A */
+
+OP(op,c0) { RET_COND( !(_F & ZF), 0xc0 ); } /* RET NZ */
+OP(op,c1) { POP(BC); } /* POP BC */
+OP(op,c2) { JP_COND( !(_F & ZF) ); } /* JP NZ,a */
+OP(op,c3) { JP; } /* JP a */
+OP(op,c4) { CALL_COND( !(_F & ZF), 0xc4 ); } /* CALL NZ,a */
+OP(op,c5) { PUSH( BC ); } /* PUSH BC */
+OP(op,c6) { ADD(ARG()); } /* ADD A,n */
+OP(op,c7) { RST(0x00); } /* RST 0 */
+
+OP(op,c8) { RET_COND( _F & ZF, 0xc8 ); } /* RET Z */
+OP(op,c9) { POP(PC); } /* RET */
+OP(op,ca) { JP_COND( _F & ZF ); } /* JP Z,a */
+OP(op,cb) { m_R++; m_extra_cycles += exec_cb(ROP()); } /* **** CB xx */
+OP(op,cc) { CALL_COND( _F & ZF, 0xcc ); } /* CALL Z,a */
+OP(op,cd) { CALL(); } /* CALL a */
+OP(op,ce) { ADC(ARG()); } /* ADC A,n */
+OP(op,cf) { RST(0x08); } /* RST 1 */
+
+OP(op,d0) { RET_COND( !(_F & CF), 0xd0 ); } /* RET NC */
+OP(op,d1) { POP(DE); } /* POP DE */
+OP(op,d2) { JP_COND( !(_F & CF) ); } /* JP NC,a */
+OP(op,d3) { unsigned n = ARG() | (_A << 8); OUT(n, _A ); } /* OUT (n),A */
+OP(op,d4) { CALL_COND( !(_F & CF), 0xd4 ); } /* CALL NC,a */
+OP(op,d5) { PUSH( DE ); } /* PUSH DE */
+OP(op,d6) { SUB(ARG()); } /* SUB n */
+OP(op,d7) { RST(0x10); } /* RST 2 */
+
+OP(op,d8) { RET_COND( _F & CF, 0xd8 ); } /* RET C */
+OP(op,d9) { EXX; } /* EXX */
+OP(op,da) { JP_COND( _F & CF ); } /* JP C,a */
+OP(op,db) { unsigned n = ARG() | (_A << 8); _A = IN(n ); } /* IN A,(n) */
+OP(op,dc) { CALL_COND( _F & CF, 0xdc ); } /* CALL C,a */
+OP(op,dd) { m_R++; m_extra_cycles += exec_dd(ROP()); } /* **** DD xx */
+OP(op,de) { SBC(ARG()); } /* SBC A,n */
+OP(op,df) { RST(0x18); } /* RST 3 */
+
+OP(op,e0) { RET_COND( !(_F & PF), 0xe0 ); } /* RET PO */
+OP(op,e1) { POP(HL); } /* POP HL */
+OP(op,e2) { JP_COND( !(_F & PF) ); } /* JP PO,a */
+OP(op,e3) { EXSP(HL); } /* EX HL,(SP) */
+OP(op,e4) { CALL_COND( !(_F & PF), 0xe4 ); } /* CALL PO,a */
+OP(op,e5) { PUSH( HL ); } /* PUSH HL */
+OP(op,e6) { AND(ARG()); } /* AND n */
+OP(op,e7) { RST(0x20); } /* RST 4 */
+
+OP(op,e8) { RET_COND( _F & PF, 0xe8 ); } /* RET PE */
+OP(op,e9) { _PC = _HL; } /* JP (HL) */
+OP(op,ea) { JP_COND( _F & PF ); } /* JP PE,a */
+OP(op,eb) { EX_DE_HL; } /* EX DE,HL */
+OP(op,ec) { CALL_COND( _F & PF, 0xec ); } /* CALL PE,a */
+OP(op,ed) { m_R++; m_extra_cycles += exec_ed(ROP()); } /* **** ED xx */
+OP(op,ee) { XOR(ARG()); } /* XOR n */
+OP(op,ef) { RST(0x28); } /* RST 5 */
+
+OP(op,f0) { RET_COND( !(_F & SF), 0xf0 ); } /* RET P */
+OP(op,f1) { POP(AF); } /* POP AF */
+OP(op,f2) { JP_COND( !(_F & SF) ); } /* JP P,a */
+OP(op,f3) { m_IFF1 = m_IFF2 = 0; } /* DI */
+OP(op,f4) { CALL_COND( !(_F & SF), 0xf4 ); } /* CALL P,a */
+OP(op,f5) { PUSH( AF ); } /* PUSH AF */
+OP(op,f6) { OR(ARG()); } /* OR n */
+OP(op,f7) { RST(0x30); } /* RST 6 */
+
+OP(op,f8) { RET_COND( _F & SF, 0xf8 ); } /* RET M */
+OP(op,f9) { _SP = _HL; } /* LD SP,HL */
+OP(op,fa) { JP_COND(_F & SF); } /* JP M,a */
+OP(op,fb) { EI; } /* EI */
+OP(op,fc) { CALL_COND( _F & SF, 0xfc ); } /* CALL M,a */
+OP(op,fd) { m_R++; m_extra_cycles += exec_fd(ROP()); } /* **** FD xx */
+OP(op,fe) { CP(ARG()); } /* CP n */
+OP(op,ff) { RST(0x38); } /* RST 7 */
+
+
+int /*z180_device::*/take_interrupt(int irq)
+{
+ int irq_vector;
+ int cycles = 0;
+
+ /* Check if processor was halted */
+ LEAVE_HALT();
+
+ /* Clear both interrupt flip flops */
+ m_IFF1 = m_IFF2 = 0;
+
+ if( irq == Z180_INT_IRQ0 )
+ {
+ // retrieve the IRQ vector from the daisy chain or CPU interface
+ device_z80daisy_interface *intf = daisy_get_irq_device();
+ irq_vector = (intf != /*nullptr*/NULL) ? intf_z80daisy_irq_ack() : standard_irq_callback_member(/**this,*/ 0);
+
+ LOG("Z180 single int. irq_vector $%02x\n", irq_vector);
+
+ /* Interrupt mode 2. Call [m_I:databyte] */
+ if( m_IM == 2 )
+ {
+ irq_vector = (irq_vector & 0xff) + (m_I << 8);
+ PUSH( PC );
+ RM16(irq_vector, &m_PC );
+ LOG("Z180 IM2 [$%04x] = $%04x\n", irq_vector, _PCD);
+ /* CALL opcode timing */
+ cycles += m_cc[Z180_TABLE_op][0xcd];
+ }
+ else
+ /* Interrupt mode 1. RST 38h */
+ if( m_IM == 1 )
+ {
+ LOG("Z180 IM1 $0038\n");
+ PUSH( PC );
+ _PCD = 0x0038;
+ /* RST $38 + 'interrupt latency' cycles */
+ cycles += m_cc[Z180_TABLE_op][0xff] - m_cc[Z180_TABLE_ex][0xff];
+ }
+ else
+ {
+ /* Interrupt mode 0. We check for CALL and JP instructions, */
+ /* if neither of these were found we assume a 1 byte opcode */
+ /* was placed on the databus */
+ LOG("Z180 IM0 $%04x\n", irq_vector);
+ switch (irq_vector & 0xff0000)
+ {
+ case 0xcd0000: /* call */
+ PUSH( PC );
+ _PCD = irq_vector & 0xffff;
+ /* CALL $xxxx + 'interrupt latency' cycles */
+ cycles += m_cc[Z180_TABLE_op][0xcd] - m_cc[Z180_TABLE_ex][0xff];
+ break;
+ case 0xc30000: /* jump */
+ _PCD = irq_vector & 0xffff;
+ /* JP $xxxx + 2 cycles */
+ cycles += m_cc[Z180_TABLE_op][0xc3] - m_cc[Z180_TABLE_ex][0xff];
+ break;
+ default: /* rst (or other opcodes?) */
+ PUSH( PC );
+ _PCD = irq_vector & 0x0038;
+ /* RST $xx + 2 cycles */
+ cycles += m_cc[Z180_TABLE_op][_PCD] - m_cc[Z180_TABLE_ex][_PCD];
+ break;
+ }
+ }
+ }
+ else
+ {
+ irq_vector = (IO(Z180_IL) & Z180_IL_IL) + (irq - Z180_INT_IRQ1) * 2;
+ irq_vector = (m_I << 8) + (irq_vector & 0xff);
+ PUSH( PC );
+ RM16(irq_vector, &m_PC );
+ LOG("Z180 INT%d [$%04x] = $%04x\n", irq, irq_vector, _PCD);
+ /* CALL opcode timing */
+ cycles += m_cc[Z180_TABLE_op][0xcd];
+ }
+
+ return cycles;
+}
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+/***************************************************************
+ * Enter HALT state; write 1 to fake port on first execution
+ ***************************************************************/
+#define ENTER_HALT() { \
+ _PC--; \
+ m_HALT = 1; \
+}
+
+/***************************************************************
+ * Leave HALT state; write 0 to fake port
+ ***************************************************************/
+#define LEAVE_HALT() { \
+ if( m_HALT ) \
+ { \
+ m_HALT = 0; \
+ _PC++; \
+ } \
+}
+
+/***************************************************************
+ * Input a byte from given I/O port
+ ***************************************************************/
+/*inline*/ u8 /*z180_device::*/IN(u16 port)
+{
+ if(((port ^ IO_IOCR) & 0xffc0) == 0)
+ return z180_readcontrol(port);
+ m_extra_cycles += ((IO_DCNTL & (Z180_DCNTL_IWI1 | Z180_DCNTL_IWI0)) >> 4) + 1; // external I/O wait states
+ return m_iospace_read_byte(port);
+}
+
+/***************************************************************
+ * Output a byte to given I/O port
+ ***************************************************************/
+/*inline*/ void /*z180_device::*/OUT(u16 port, u8 value)
+{
+ if (((port ^ IO_IOCR) & 0xffc0) == 0) {
+ z180_writecontrol(port,value);
+ } else
+ {
+ m_extra_cycles += ((IO_DCNTL & (Z180_DCNTL_IWI1 | Z180_DCNTL_IWI0)) >> 4) + 1; // external I/O wait states
+ m_iospace_write_byte(port, value);
+ }
+}
+
+/***************************************************************
+ * MMU calculate the memory management lookup table
+ * bb and cb specify a 4K page
+ * If the 4 most significant bits of an 16 bit address are
+ * greater or equal to the bank base, the bank base register
+ * specifies the 4K offset into the 20 bit address space.
+ * If the 4 bits are also greater or equal to the common base,
+ * the common base register is used to specify the offset.
+ ***************************************************************/
+void /*z180_device::*/z180_mmu()
+{
+ offs_t addr, page, bb, cb;
+ bb = IO_CBAR & 15;
+ cb = IO_CBAR >> 4;
+ for( page = 0; page < 16; page++ )
+ {
+ addr = page << 12;
+ if (page >= bb)
+ {
+ if (page >= cb)
+ addr += (IO_CBR << 12);
+ else
+ addr += (IO_BBR << 12);
+ }
+ m_mmu[page] = (addr & 0xfffff);
+ }
+}
+
+
+#define MMU_REMAP_ADDR(addr) (m_mmu[((addr)>>12)&15]|((addr)&4095))
+
+/***************************************************************
+ * Read a byte from given memory location
+ ***************************************************************/
+/*inline*/ u8 /*z180_device::*/RM(offs_t addr)
+{
+ m_extra_cycles += IO_DCNTL >> 6; // memory wait states
+ return m_program_read_byte(MMU_REMAP_ADDR(addr));
+}
+
+/***************************************************************
+ * Write a byte to given memory location
+ ***************************************************************/
+#define WM(addr,value) m_extra_cycles += IO_DCNTL >> 6; /* memory wait states */ m_program_write_byte(MMU_REMAP_ADDR(addr),value)
+
+/***************************************************************
+ * Read a word from given memory location
+ ***************************************************************/
+void /*z180_device::*/RM16( offs_t addr, PAIR *r )
+{
+ r->b.l = RM(addr);
+ r->b.h = RM(addr+1);
+}
+
+/***************************************************************
+ * Write a word to given memory location
+ ***************************************************************/
+void /*z180_device::*/WM16( offs_t addr, PAIR *r )
+{
+ WM(addr, r->b.l);
+ WM(addr+1, r->b.h);
+}
+
+/***************************************************************
+ * ROP() is identical to RM() except it is used for
+ * reading opcodes_ In case of system with memory mapped I/O,
+ * this function can be used to greatly speed up emulation
+ ***************************************************************/
+uint8_t /*z180_device::*/ROP()
+{
+ offs_t addr = _PCD;
+ _PC++;
+ m_extra_cycles += IO_DCNTL >> 6; // memory wait states
+ return m_ocache_read_byte(MMU_REMAP_ADDR(addr));
+}
+
+/****************************************************************
+ * ARG() is identical to ROP() except it is used
+ * for reading opcode arguments. This difference can be used to
+ * support systems that use different encoding mechanisms for
+ * opcodes and opcode arguments
+ ***************************************************************/
+uint8_t /*z180_device::*/ARG()
+{
+ offs_t addr = _PCD;
+ _PC++;
+ m_extra_cycles += IO_DCNTL >> 6; // memory wait states
+ return m_cache_read_byte(MMU_REMAP_ADDR(addr));
+}
+
+uint32_t /*z180_device::*/ARG16()
+{
+ offs_t addr = _PCD;
+ _PC += 2;
+ m_extra_cycles += (IO_DCNTL >> 6) * 2; // memory wait states
+ return m_cache_read_byte(MMU_REMAP_ADDR(addr)) | (m_cache_read_byte(MMU_REMAP_ADDR(addr+1)) << 8);
+}
+
+/***************************************************************
+ * Calculate the effective address m_ea of an opcode using
+ * IX+offset resp. IY+offset addressing.
+ ***************************************************************/
+#define EAX() m_ea = (uint32_t)(uint16_t)(_IX + (int8_t)ARG())
+#define EAY() m_ea = (uint32_t)(uint16_t)(_IY + (int8_t)ARG())
+
+/***************************************************************
+ * POP
+ ***************************************************************/
+#define POP(DR) { RM16(_SPD, &m_##DR ); _SP += 2; }
+
+/***************************************************************
+ * PUSH
+ ***************************************************************/
+#define PUSH(SR) { _SP -= 2; WM16(_SPD, &m_##SR); }
+
+/***************************************************************
+ * JP
+ ***************************************************************/
+#define JP { \
+ _PCD = ARG16(); \
+}
+
+/***************************************************************
+ * JP_COND
+ ***************************************************************/
+
+#define JP_COND(cond) \
+ if( cond ) \
+ { \
+ _PCD = ARG16(); \
+ } \
+ else \
+ { \
+ _PC += 2; \
+ }
+
+/***************************************************************
+ * JR
+ ***************************************************************/
+#define JR() \
+{ \
+ int8_t arg = (int8_t)ARG(); /* ARG() also increments _PC */ \
+ _PC += arg; /* so don't do _PC += ARG() */ \
+}
+
+/***************************************************************
+ * JR_COND
+ ***************************************************************/
+#define JR_COND(cond,opcode) \
+ if( cond ) \
+ { \
+ int8_t arg = (int8_t)ARG(); /* ARG() also increments _PC */ \
+ _PC += arg; /* so don't do _PC += ARG() */ \
+ CC(ex,opcode); \
+ } \
+ else _PC++;
+/***************************************************************
+ * CALL
+ ***************************************************************/
+#define CALL() \
+ m_ea = ARG16(); \
+ PUSH( PC ); \
+ _PCD = m_ea;
+
+/***************************************************************
+ * CALL_COND
+ ***************************************************************/
+#define CALL_COND(cond,opcode) \
+ if( cond ) \
+ { \
+ m_ea = ARG16(); \
+ PUSH( PC ); \
+ _PCD = m_ea; \
+ CC(ex,opcode); \
+ } \
+ else \
+ { \
+ _PC+=2; \
+ }
+
+/***************************************************************
+ * RET_COND
+ ***************************************************************/
+#define RET_COND(cond,opcode) \
+ if( cond ) \
+ { \
+ POP(PC); \
+ CC(ex,opcode); \
+ }
+
+/***************************************************************
+ * RETN
+ ***************************************************************/
+#define RETN { \
+ LOG("Z180 RETN IFF1:%d IFF2:%d\n", m_IFF1, m_IFF2); \
+ POP(PC); \
+ m_IFF1 = m_IFF2; \
+}
+
+/***************************************************************
+ * RETI
+ ***************************************************************/
+#define RETI { \
+ POP(PC); \
+/* according to http://www.msxnet.org/tech/Z80/z80undoc.txt */ \
+/* m_IFF1 = m_IFF2; */ \
+ daisy_call_reti_device(); \
+}
+
+/***************************************************************
+ * LD R,A
+ ***************************************************************/
+#define LD_R_A { \
+ m_R = _A; \
+ m_R2 = _A & 0x80; /* keep bit 7 of R */ \
+}
+
+/***************************************************************
+ * LD A,R
+ ***************************************************************/
+#define LD_A_R { \
+ _A = (m_R & 0x7f) | m_R2; \
+ _F = (_F & CF) | SZ[_A] | ( m_IFF2 << 2 ); \
+}
+
+/***************************************************************
+ * LD I,A
+ ***************************************************************/
+#define LD_I_A { \
+ m_I = _A; \
+}
+
+/***************************************************************
+ * LD A,I
+ ***************************************************************/
+#define LD_A_I { \
+ _A = m_I; \
+ _F = (_F & CF) | SZ[_A] | ( m_IFF2 << 2 ); \
+}
+
+/***************************************************************
+ * RST
+ ***************************************************************/
+#define RST(addr) \
+ PUSH( PC ); \
+ _PCD = addr;
+
+/***************************************************************
+ * INC r8
+ ***************************************************************/
+uint8_t /*z180_device::*/INC(uint8_t value)
+{
+ uint8_t res = value + 1;
+ _F = (_F & CF) | SZHV_inc[res];
+ return (uint8_t)res;
+}
+
+/***************************************************************
+ * DEC r8
+ ***************************************************************/
+uint8_t /*z180_device::*/DEC(uint8_t value)
+{
+ uint8_t res = value - 1;
+ _F = (_F & CF) | SZHV_dec[res];
+ return res;
+}
+
+/***************************************************************
+ * RLCA
+ ***************************************************************/
+#define RLCA \
+ _A = (_A << 1) | (_A >> 7); \
+ _F = (_F & (SF | ZF | PF)) | (_A & (YF | XF | CF))
+
+/***************************************************************
+ * RRCA
+ ***************************************************************/
+#define RRCA \
+ _F = (_F & (SF | ZF | PF)) | (_A & (YF | XF | CF)); \
+ _A = (_A >> 1) | (_A << 7)
+
+/***************************************************************
+ * RLA
+ ***************************************************************/
+#define RLA { \
+ uint8_t res = (_A << 1) | (_F & CF); \
+ uint8_t c = (_A & 0x80) ? CF : 0; \
+ _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \
+ _A = res; \
+}
+
+/***************************************************************
+ * RRA
+ ***************************************************************/
+#define RRA { \
+ uint8_t res = (_A >> 1) | (_F << 7); \
+ uint8_t c = (_A & 0x01) ? CF : 0; \
+ _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \
+ _A = res; \
+}
+
+/***************************************************************
+ * RRD
+ ***************************************************************/
+#define RRD { \
+ uint8_t n = RM(_HL); \
+ WM( _HL, (n >> 4) | (_A << 4) ); \
+ _A = (_A & 0xf0) | (n & 0x0f); \
+ _F = (_F & CF) | SZP[_A]; \
+}
+
+/***************************************************************
+ * RLD
+ ***************************************************************/
+#define RLD { \
+ uint8_t n = RM(_HL); \
+ WM( _HL, (n << 4) | (_A & 0x0f) ); \
+ _A = (_A & 0xf0) | (n >> 4); \
+ _F = (_F & CF) | SZP[_A]; \
+}
+
+/***************************************************************
+ * ADD A,n
+ ***************************************************************/
+#define ADD(value) \
+{ \
+ uint32_t ah = _AFD & 0xff00; \
+ uint32_t res = (uint8_t)((ah >> 8) + value); \
+ _F = SZHVC_add[ah | res]; \
+ _A = res; \
+}
+
+/***************************************************************
+ * ADC A,n
+ ***************************************************************/
+#define ADC(value) \
+{ \
+ uint32_t ah = _AFD & 0xff00, c = _AFD & 1; \
+ uint32_t res = (uint8_t)((ah >> 8) + value + c); \
+ _F = SZHVC_add[(c << 16) | ah | res]; \
+ _A = res; \
+}
+
+/***************************************************************
+ * SUB n
+ ***************************************************************/
+#define SUB(value) \
+{ \
+ uint32_t ah = _AFD & 0xff00; \
+ uint32_t res = (uint8_t)((ah >> 8) - value); \
+ _F = SZHVC_sub[ah | res]; \
+ _A = res; \
+}
+
+/***************************************************************
+ * SBC A,n
+ ***************************************************************/
+#define SBC(value) \
+{ \
+ uint32_t ah = _AFD & 0xff00, c = _AFD & 1; \
+ uint32_t res = (uint8_t)((ah >> 8) - value - c); \
+ _F = SZHVC_sub[(c<<16) | ah | res]; \
+ _A = res; \
+}
+
+/***************************************************************
+ * NEG
+ ***************************************************************/
+#define NEG { \
+ uint8_t value = _A; \
+ _A = 0; \
+ SUB(value); \
+}
+
+/***************************************************************
+ * DAA
+ ***************************************************************/
+#define DAA { \
+ uint8_t r = _A; \
+ if (_F&NF) { \
+ if ((_F&HF)|((_A&0xf)>9)) r-=6; \
+ if ((_F&CF)|(_A>0x99)) r-=0x60; \
+ } \
+ else { \
+ if ((_F&HF)|((_A&0xf)>9)) r+=6; \
+ if ((_F&CF)|(_A>0x99)) r+=0x60; \
+ } \
+ _F=(_F&3)|(_A>0x99)|((_A^r)&HF)|SZP[r]; \
+ _A=r; \
+}
+
+/***************************************************************
+ * AND n
+ ***************************************************************/
+#define AND(value) \
+ _A &= value; \
+ _F = SZP[_A] | HF
+
+/***************************************************************
+ * OR n
+ ***************************************************************/
+#define OR(value) \
+ _A |= value; \
+ _F = SZP[_A]
+
+/***************************************************************
+ * XOR n
+ ***************************************************************/
+#define XOR(value) \
+ _A ^= value; \
+ _F = SZP[_A]
+
+/***************************************************************
+ * CP n
+ ***************************************************************/
+#define CP(value) \
+{ \
+ uint32_t ah = _AFD & 0xff00; \
+ uint32_t res = (uint8_t)((ah >> 8) - value); \
+ _F = SZHVC_sub[ah | res]; \
+}
+
+/***************************************************************
+ * EX AF,AF'
+ ***************************************************************/
+#define EX_AF { \
+ PAIR tmp; \
+ tmp = m_AF; m_AF = m_AF2; m_AF2 = tmp; \
+}
+
+/***************************************************************
+ * EX DE,HL
+ ***************************************************************/
+#define EX_DE_HL { \
+ PAIR tmp; \
+ tmp = m_DE; m_DE = m_HL; m_HL = tmp; \
+}
+
+/***************************************************************
+ * EXX
+ ***************************************************************/
+#define EXX { \
+ PAIR tmp; \
+ tmp = m_BC; m_BC = m_BC2; m_BC2 = tmp; \
+ tmp = m_DE; m_DE = m_DE2; m_DE2 = tmp; \
+ tmp = m_HL; m_HL = m_HL2; m_HL2 = tmp; \
+}
+
+/***************************************************************
+ * EX (SP),r16
+ ***************************************************************/
+#define EXSP(DR) \
+{ \
+ PAIR tmp = { { 0, 0, 0, 0 } }; \
+ RM16( _SPD, &tmp ); \
+ WM16( _SPD, &m_##DR ); \
+ m_##DR = tmp; \
+}
+
+
+/***************************************************************
+ * ADD16
+ ***************************************************************/
+#define ADD16(DR,SR) \
+{ \
+ uint32_t res = m_##DR.d + m_##SR.d; \
+ _F = (_F & (SF | ZF | VF)) | \
+ (((m_##DR.d ^ res ^ m_##SR.d) >> 8) & HF) | \
+ ((res >> 16) & CF); \
+ m_##DR.w.l = (uint16_t)res; \
+}
+
+/***************************************************************
+ * ADC r16,r16
+ ***************************************************************/
+#define ADC16(DR) \
+{ \
+ uint32_t res = _HLD + m_##DR.d + (_F & CF); \
+ _F = (((_HLD ^ res ^ m_##DR.d) >> 8) & HF) | \
+ ((res >> 16) & CF) | \
+ ((res >> 8) & SF) | \
+ ((res & 0xffff) ? 0 : ZF) | \
+ (((m_##DR.d ^ _HLD ^ 0x8000) & (m_##DR.d ^ res) & 0x8000) >> 13); \
+ _HL = (uint16_t)res; \
+}
+
+/***************************************************************
+ * SBC r16,r16
+ ***************************************************************/
+#define SBC16(DR) \
+{ \
+ uint32_t res = _HLD - m_##DR.d - (_F & CF); \
+ _F = (((_HLD ^ res ^ m_##DR.d) >> 8) & HF) | NF | \
+ ((res >> 16) & CF) | \
+ ((res >> 8) & SF) | \
+ ((res & 0xffff) ? 0 : ZF) | \
+ (((m_##DR.d ^ _HLD) & (_HLD ^ res) &0x8000) >> 13); \
+ _HL = (uint16_t)res; \
+}
+
+/***************************************************************
+ * RLC r8
+ ***************************************************************/
+uint8_t /*z180_device::*/RLC(uint8_t value)
+{
+ unsigned res = value;
+ unsigned c = (res & 0x80) ? CF : 0;
+ res = ((res << 1) | (res >> 7)) & 0xff;
+ _F = SZP[res] | c;
+ return res;
+}
+
+/***************************************************************
+ * RRC r8
+ ***************************************************************/
+uint8_t /*z180_device::*/RRC(uint8_t value)
+{
+ unsigned res = value;
+ unsigned c = (res & 0x01) ? CF : 0;
+ res = ((res >> 1) | (res << 7)) & 0xff;
+ _F = SZP[res] | c;
+ return res;
+}
+
+/***************************************************************
+ * RL r8
+ ***************************************************************/
+uint8_t /*z180_device::*/RL(uint8_t value)
+{
+ unsigned res = value;
+ unsigned c = (res & 0x80) ? CF : 0;
+ res = ((res << 1) | (_F & CF)) & 0xff;
+ _F = SZP[res] | c;
+ return res;
+}
+
+/***************************************************************
+ * RR r8
+ ***************************************************************/
+uint8_t /*z180_device::*/RR(uint8_t value)
+{
+ unsigned res = value;
+ unsigned c = (res & 0x01) ? CF : 0;
+ res = ((res >> 1) | (_F << 7)) & 0xff;
+ _F = SZP[res] | c;
+ return res;
+}
+
+/***************************************************************
+ * SLA r8
+ ***************************************************************/
+uint8_t /*z180_device::*/SLA(uint8_t value)
+{
+ unsigned res = value;
+ unsigned c = (res & 0x80) ? CF : 0;
+ res = (res << 1) & 0xff;
+ _F = SZP[res] | c;
+ return res;
+}
+
+/***************************************************************
+ * SRA r8
+ ***************************************************************/
+uint8_t /*z180_device::*/SRA(uint8_t value)
+{
+ unsigned res = value;
+ unsigned c = (res & 0x01) ? CF : 0;
+ res = ((res >> 1) | (res & 0x80)) & 0xff;
+ _F = SZP[res] | c;
+ return res;
+}
+
+/***************************************************************
+ * SLL r8
+ ***************************************************************/
+uint8_t /*z180_device::*/SLL(uint8_t value)
+{
+ unsigned res = value;
+ unsigned c = (res & 0x80) ? CF : 0;
+ res = ((res << 1) | 0x01) & 0xff;
+ _F = SZP[res] | c;
+ return res;
+}
+
+/***************************************************************
+ * SRL r8
+ ***************************************************************/
+uint8_t /*z180_device::*/SRL(uint8_t value)
+{
+ unsigned res = value;
+ unsigned c = (res & 0x01) ? CF : 0;
+ res = (res >> 1) & 0xff;
+ _F = SZP[res] | c;
+ return res;
+}
+
+/***************************************************************
+ * BIT bit,r8
+ ***************************************************************/
+#undef BIT
+#define BIT(bit,reg) \
+ _F = (_F & CF) | HF | SZ_BIT[reg & (1<<bit)]
+
+/***************************************************************
+ * BIT bit,(IX/Y+o)
+ ***************************************************************/
+#define BIT_XY(bit,reg) \
+ _F = (_F & CF) | HF | (SZ_BIT[reg & (1<<bit)] & ~(YF|XF)) | ((m_ea>>8) & (YF|XF))
+
+/***************************************************************
+ * RES bit,r8
+ ***************************************************************/
+uint8_t /*z180_device::*/RES(uint8_t bit, uint8_t value)
+{
+ return value & ~(1<<bit);
+}
+
+/***************************************************************
+ * SET bit,r8
+ ***************************************************************/
+uint8_t /*z180_device::*/SET(uint8_t bit, uint8_t value)
+{
+ return value | (1<<bit);
+}
+
+/***************************************************************
+ * LDI
+ ***************************************************************/
+#define LDI { \
+ uint8_t io = RM(_HL); \
+ WM( _DE, io ); \
+ _F &= SF | ZF | CF; \
+ if( (_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \
+ if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \
+ _HL++; _DE++; _BC--; \
+ if( _BC ) _F |= VF; \
+}
+
+/***************************************************************
+ * CPI
+ ***************************************************************/
+#define CPI { \
+ uint8_t val = RM(_HL); \
+ uint8_t res = _A - val; \
+ _HL++; _BC--; \
+ _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF; \
+ if( _F & HF ) res -= 1; \
+ if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \
+ if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \
+ if( _BC ) _F |= VF; \
+}
+
+/***************************************************************
+ * INI
+ ***************************************************************/
+#define INI { \
+ uint8_t io = IN(_BC); \
+ _B--; \
+ WM( _HL, io ); \
+ _HL++; \
+ _F = SZ[_B]; \
+ if( io & SF ) _F |= NF; \
+ if( (_C + io + 1) & 0x100 ) _F |= HF | CF; \
+ if( (irep_tmp1[_C & 3][io & 3] ^ \
+ breg_tmp2[_B] ^ \
+ (_C >> 2) ^ \
+ (io >> 2)) & 1 ) \
+ _F |= PF; \
+}
+
+/***************************************************************
+ * OUTI
+ ***************************************************************/
+#define OUTI { \
+ uint8_t io = RM(_HL); \
+ _B--; \
+ OUT( _BC, io ); \
+ _HL++; \
+ _F = SZ[_B]; \
+ if( io & SF ) _F |= NF; \
+ if( (_C + io + 1) & 0x100 ) _F |= HF | CF; \
+ if( (irep_tmp1[_C & 3][io & 3] ^ \
+ breg_tmp2[_B] ^ \
+ (_C >> 2) ^ \
+ (io >> 2)) & 1 ) \
+ _F |= PF; \
+}
+
+/***************************************************************
+ * LDD
+ ***************************************************************/
+#define LDD { \
+ uint8_t io = RM(_HL); \
+ WM( _DE, io ); \
+ _F &= SF | ZF | CF; \
+ if( (_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \
+ if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \
+ _HL--; _DE--; _BC--; \
+ if( _BC ) _F |= VF; \
+}
+
+/***************************************************************
+ * CPD
+ ***************************************************************/
+#define CPD { \
+ uint8_t val = RM(_HL); \
+ uint8_t res = _A - val; \
+ _HL--; _BC--; \
+ _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF; \
+ if( _F & HF ) res -= 1; \
+ if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \
+ if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \
+ if( _BC ) _F |= VF; \
+}
+
+/***************************************************************
+ * IND
+ ***************************************************************/
+#define IND { \
+ uint8_t io = IN(_BC); \
+ _B--; \
+ WM( _HL, io ); \
+ _HL--; \
+ _F = SZ[_B]; \
+ if( io & SF ) _F |= NF; \
+ if( (_C + io - 1) & 0x100 ) _F |= HF | CF; \
+ if( (drep_tmp1[_C & 3][io & 3] ^ \
+ breg_tmp2[_B] ^ \
+ (_C >> 2) ^ \
+ (io >> 2)) & 1 ) \
+ _F |= PF; \
+}
+
+/***************************************************************
+ * OUTD
+ ***************************************************************/
+#define OUTD { \
+ uint8_t io = RM(_HL); \
+ _B--; \
+ OUT( _BC, io ); \
+ _HL--; \
+ _F = SZ[_B]; \
+ if( io & SF ) _F |= NF; \
+ if( (_C + io - 1) & 0x100 ) _F |= HF | CF; \
+ if( (drep_tmp1[_C & 3][io & 3] ^ \
+ breg_tmp2[_B] ^ \
+ (_C >> 2) ^ \
+ (io >> 2)) & 1 ) \
+ _F |= PF; \
+}
+
+/***************************************************************
+ * LDIR
+ ***************************************************************/
+#define LDIR \
+ LDI; \
+ if( _BC ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xb0); \
+ }
+
+/***************************************************************
+ * CPIR
+ ***************************************************************/
+#define CPIR \
+ CPI; \
+ if( _BC && !(_F & ZF) ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xb1); \
+ }
+
+/***************************************************************
+ * INIR
+ ***************************************************************/
+#define INIR \
+ INI; \
+ if( _B ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xb2); \
+ }
+
+/***************************************************************
+ * OTIR
+ ***************************************************************/
+#define OTIR \
+ OUTI; \
+ if( _B ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xb3); \
+ }
+
+/***************************************************************
+ * LDDR
+ ***************************************************************/
+#define LDDR \
+ LDD; \
+ if( _BC ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xb8); \
+ }
+
+/***************************************************************
+ * CPDR
+ ***************************************************************/
+#define CPDR \
+ CPD; \
+ if( _BC && !(_F & ZF) ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xb9); \
+ }
+
+/***************************************************************
+ * INDR
+ ***************************************************************/
+#define INDR \
+ IND; \
+ if( _B ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xba); \
+ }
+
+/***************************************************************
+ * OTDR
+ ***************************************************************/
+#define OTDR \
+ OUTD; \
+ if( _B ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xbb); \
+ }
+
+/***************************************************************
+ * EI
+ ***************************************************************/
+#define EI { \
+ m_IFF1 = m_IFF2 = 1; \
+ m_after_EI = 1; \
+}
+
+/***************************************************************
+ * TST n
+ ***************************************************************/
+#define TST(value) \
+ _F = SZP[_A & value] | HF
+
+/***************************************************************
+ * MLT rr
+ ***************************************************************/
+#define MLT(DR) { \
+ m_##DR.w.l = m_##DR.b.l * m_##DR.b.h; \
+}
+
+/***************************************************************
+ * OTIM
+ ***************************************************************/
+#define OTIM { \
+ _B--; \
+ OUT( _C, RM(_HL) ); \
+ _HL++; \
+ _C++; \
+ _F = (_B) ? NF : NF | ZF; \
+}
+
+/***************************************************************
+ * OTDM
+ ***************************************************************/
+#define OTDM { \
+ _B--; \
+ OUT( _C, RM(_HL) ); \
+ _HL--; \
+ _C--; \
+ _F = (_B) ? NF : NF | ZF; \
+}
+
+/***************************************************************
+ * OTIMR
+ ***************************************************************/
+#define OTIMR \
+ OTIM; \
+ if( _B ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xb3); \
+ }
+
+/***************************************************************
+ * OTDMR
+ ***************************************************************/
+#define OTDMR \
+ OTDM; \
+ if( _B ) \
+ { \
+ _PC -= 2; \
+ CC(ex,0xb3); \
+ }
+
+/***************************************************************
+ * OTDMR
+ ***************************************************************/
+#define SLP { \
+ m_icount = 0; \
+ m_HALT = 2; \
+}
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+/* tmp1 value for ini/inir/outi/otir for [C.1-0][io.1-0] */
+static const uint8_t irep_tmp1[4][4] = {
+ {0,0,1,0},{0,1,0,1},{1,0,1,1},{0,1,1,0}
+};
+
+/* tmp1 value for ind/indr/outd/otdr for [C.1-0][io.1-0] */
+static const uint8_t drep_tmp1[4][4] = {
+ {0,1,0,0},{1,0,0,1},{0,0,1,0},{0,1,0,1}
+};
+
+/* tmp2 value for all in/out repeated opcodes for B.7-0 */
+static const uint8_t breg_tmp2[256] = {
+ 0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+ 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+ 1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+ 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+ 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+ 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+ 0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+ 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+ 1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+ 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+ 0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+ 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+ 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+ 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+ 1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+ 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1
+};
+
+static const uint8_t cc_op[0x100] = {
+/*-0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -a -b -c -d -e -f */
+ 3, 9, 7, 4, 4, 4, 6, 3, 4, 7, 6, 4, 4, 4, 6, 3,
+ 7, 9, 7, 4, 4, 4, 6, 3, 8, 7, 6, 4, 4, 4, 6, 3,
+ 6, 9,16, 4, 4, 4, 6, 4, 6, 7,15, 4, 4, 4, 6, 3,
+ 6, 9,13, 4,10,10, 9, 3, 6, 7,12, 4, 4, 4, 6, 3,
+ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
+ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
+ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
+ 7, 7, 7, 7, 7, 7, 3, 7, 4, 4, 4, 4, 4, 4, 6, 4,
+ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
+ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
+ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
+ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
+ 5, 9, 6, 9, 6,11, 6,11, 5, 9, 6, 0, 6,16, 6,11,
+ 5, 9, 6,10, 6,11, 6,11, 5, 3, 6, 9, 6, 0, 6,11,
+ 5, 9, 6,16, 6,11, 6,11, 5, 3, 6, 3, 6, 0, 6,11,
+ 5, 9, 6, 3, 6,11, 6,11, 5, 4, 6, 3, 6, 0, 6,11
+};
+
+static const uint8_t cc_cb[0x100] = {
+/*-0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -a -b -c -d -e -f */
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 6, 6, 6, 6, 6, 6, 9, 6, 6, 6, 6, 6, 6, 6, 9, 6,
+ 6, 6, 6, 6, 6, 6, 9, 6, 6, 6, 6, 6, 6, 6, 9, 6,
+ 6, 6, 6, 6, 6, 6, 9, 6, 6, 6, 6, 6, 6, 6, 9, 6,
+ 6, 6, 6, 6, 6, 6, 9, 6, 6, 6, 6, 6, 6, 6, 9, 6,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
+ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7
+};
+
+static const uint8_t cc_ed[0x100] = {
+/*-0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -a -b -c -d -e -f */
+ 12,13, 6, 6, 9, 6, 6, 6,12,13, 6, 6, 9, 6, 6, 6,
+ 12,13, 6, 6, 9, 6, 6, 6,12,13, 6, 6, 9, 6, 6, 6,
+ 12,13, 6, 6, 9, 6, 6, 6,12,13, 6, 6,10, 6, 6, 6,
+ 12,13, 6, 6, 9, 6, 6, 6,12,13, 6, 6, 9, 6, 6, 6,
+ 9,10,10,19, 6,12, 6, 6, 9,10,10,18,17,12, 6, 6,
+ 9,10,10,19, 6,12, 6, 6, 9,10,10,18,17,12, 6, 6,
+ 9,10,10,19, 6,12, 6,16, 9,10,10,18,17,12, 6,16,
+ 9,10,10,19,12,12, 8, 6, 9,10,10,18,17,12, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 12,12,12,12, 6, 6, 6, 6,12,12,12,12, 6, 6, 6, 6,
+ 12,12,12,12, 6, 6, 6, 6,12,12,12,12, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6
+};
+
+static const uint8_t cc_xy[0x100] = {
+/*-0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -a -b -c -d -e -f */
+ 4, 4, 4, 4, 4, 4, 4, 4, 4,10, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4,10, 4, 4, 4, 4, 4, 4,
+ 4,12,19, 7, 9, 9,15, 4, 4,10,18, 7, 9, 9, 9, 4,
+ 4, 4, 4, 4,18,18,15, 4, 4,10, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 9, 9,14, 4, 4, 4, 4, 4, 9, 9,14, 4,
+ 4, 4, 4, 4, 9, 9,14, 4, 4, 4, 4, 4, 9, 9,14, 4,
+ 9, 9, 9, 9, 9, 9,14, 9, 9, 9, 9, 9, 9, 9,14, 9,
+ 15,15,15,15,15,15, 4,15, 4, 4, 4, 4, 9, 9,14, 4,
+ 4, 4, 4, 4, 9, 9,14, 4, 4, 4, 4, 4, 9, 9,14, 4,
+ 4, 4, 4, 4, 9, 9,14, 4, 4, 4, 4, 4, 9, 9,14, 4,
+ 4, 4, 4, 4, 9, 9,14, 4, 4, 4, 4, 4, 9, 9,14, 4,
+ 4, 4, 4, 4, 9, 9,14, 4, 4, 4, 4, 4, 9, 9,14, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4,12, 4,19, 4,14, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4
+};
+
+static const uint8_t cc_xycb[0x100] = {
+/*-0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -a -b -c -d -e -f */
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
+ 15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
+ 15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
+ 15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,
+ 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19
+};
+
+/* extra cycles if jr/jp/call taken and 'interrupt latency' on rst 0-7 */
+static const uint8_t cc_ex[0x100] = {
+/*-0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -a -b -c -d -e -f */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* DJNZ */
+ 2, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, /* JR NZ/JR Z */
+ 2, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, /* JR NC/JR C */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 4, 4, 4, 4, 0, 0, 0, 0, 4, 4, 4, 4, 0, 0, 0, 0, /* LDIR/CPIR/INIR/OTIR LDDR/CPDR/INDR/OTDR */
+ 5, 0, 3, 0,10, 0, 0, 2, 5, 0, 3, 0,10, 0, 0, 2,
+ 5, 0, 3, 0,10, 0, 0, 2, 5, 0, 3, 0,10, 0, 0, 2,
+ 5, 0, 3, 0,10, 0, 0, 2, 5, 0, 3, 0,10, 0, 0, 2,
+ 5, 0, 3, 0,10, 0, 0, 2, 5, 0, 3, 0,10, 0, 0, 2
+};
+
+static const uint8_t *const cc_default[6] = { cc_op, cc_cb, cc_ed, cc_xy, cc_xycb, cc_ex };
+
+#define Z180_TABLE_dd Z180_TABLE_xy
+#define Z180_TABLE_fd Z180_TABLE_xy
+
+
+#define TABLE(prefix) {\
+ &/*z180_device::*/prefix##_00,&/*z180_device::*/prefix##_01,&/*z180_device::*/prefix##_02,&/*z180_device::*/prefix##_03,&/*z180_device::*/prefix##_04,&/*z180_device::*/prefix##_05,&/*z180_device::*/prefix##_06,&/*z180_device::*/prefix##_07, \
+ &/*z180_device::*/prefix##_08,&/*z180_device::*/prefix##_09,&/*z180_device::*/prefix##_0a,&/*z180_device::*/prefix##_0b,&/*z180_device::*/prefix##_0c,&/*z180_device::*/prefix##_0d,&/*z180_device::*/prefix##_0e,&/*z180_device::*/prefix##_0f, \
+ &/*z180_device::*/prefix##_10,&/*z180_device::*/prefix##_11,&/*z180_device::*/prefix##_12,&/*z180_device::*/prefix##_13,&/*z180_device::*/prefix##_14,&/*z180_device::*/prefix##_15,&/*z180_device::*/prefix##_16,&/*z180_device::*/prefix##_17, \
+ &/*z180_device::*/prefix##_18,&/*z180_device::*/prefix##_19,&/*z180_device::*/prefix##_1a,&/*z180_device::*/prefix##_1b,&/*z180_device::*/prefix##_1c,&/*z180_device::*/prefix##_1d,&/*z180_device::*/prefix##_1e,&/*z180_device::*/prefix##_1f, \
+ &/*z180_device::*/prefix##_20,&/*z180_device::*/prefix##_21,&/*z180_device::*/prefix##_22,&/*z180_device::*/prefix##_23,&/*z180_device::*/prefix##_24,&/*z180_device::*/prefix##_25,&/*z180_device::*/prefix##_26,&/*z180_device::*/prefix##_27, \
+ &/*z180_device::*/prefix##_28,&/*z180_device::*/prefix##_29,&/*z180_device::*/prefix##_2a,&/*z180_device::*/prefix##_2b,&/*z180_device::*/prefix##_2c,&/*z180_device::*/prefix##_2d,&/*z180_device::*/prefix##_2e,&/*z180_device::*/prefix##_2f, \
+ &/*z180_device::*/prefix##_30,&/*z180_device::*/prefix##_31,&/*z180_device::*/prefix##_32,&/*z180_device::*/prefix##_33,&/*z180_device::*/prefix##_34,&/*z180_device::*/prefix##_35,&/*z180_device::*/prefix##_36,&/*z180_device::*/prefix##_37, \
+ &/*z180_device::*/prefix##_38,&/*z180_device::*/prefix##_39,&/*z180_device::*/prefix##_3a,&/*z180_device::*/prefix##_3b,&/*z180_device::*/prefix##_3c,&/*z180_device::*/prefix##_3d,&/*z180_device::*/prefix##_3e,&/*z180_device::*/prefix##_3f, \
+ &/*z180_device::*/prefix##_40,&/*z180_device::*/prefix##_41,&/*z180_device::*/prefix##_42,&/*z180_device::*/prefix##_43,&/*z180_device::*/prefix##_44,&/*z180_device::*/prefix##_45,&/*z180_device::*/prefix##_46,&/*z180_device::*/prefix##_47, \
+ &/*z180_device::*/prefix##_48,&/*z180_device::*/prefix##_49,&/*z180_device::*/prefix##_4a,&/*z180_device::*/prefix##_4b,&/*z180_device::*/prefix##_4c,&/*z180_device::*/prefix##_4d,&/*z180_device::*/prefix##_4e,&/*z180_device::*/prefix##_4f, \
+ &/*z180_device::*/prefix##_50,&/*z180_device::*/prefix##_51,&/*z180_device::*/prefix##_52,&/*z180_device::*/prefix##_53,&/*z180_device::*/prefix##_54,&/*z180_device::*/prefix##_55,&/*z180_device::*/prefix##_56,&/*z180_device::*/prefix##_57, \
+ &/*z180_device::*/prefix##_58,&/*z180_device::*/prefix##_59,&/*z180_device::*/prefix##_5a,&/*z180_device::*/prefix##_5b,&/*z180_device::*/prefix##_5c,&/*z180_device::*/prefix##_5d,&/*z180_device::*/prefix##_5e,&/*z180_device::*/prefix##_5f, \
+ &/*z180_device::*/prefix##_60,&/*z180_device::*/prefix##_61,&/*z180_device::*/prefix##_62,&/*z180_device::*/prefix##_63,&/*z180_device::*/prefix##_64,&/*z180_device::*/prefix##_65,&/*z180_device::*/prefix##_66,&/*z180_device::*/prefix##_67, \
+ &/*z180_device::*/prefix##_68,&/*z180_device::*/prefix##_69,&/*z180_device::*/prefix##_6a,&/*z180_device::*/prefix##_6b,&/*z180_device::*/prefix##_6c,&/*z180_device::*/prefix##_6d,&/*z180_device::*/prefix##_6e,&/*z180_device::*/prefix##_6f, \
+ &/*z180_device::*/prefix##_70,&/*z180_device::*/prefix##_71,&/*z180_device::*/prefix##_72,&/*z180_device::*/prefix##_73,&/*z180_device::*/prefix##_74,&/*z180_device::*/prefix##_75,&/*z180_device::*/prefix##_76,&/*z180_device::*/prefix##_77, \
+ &/*z180_device::*/prefix##_78,&/*z180_device::*/prefix##_79,&/*z180_device::*/prefix##_7a,&/*z180_device::*/prefix##_7b,&/*z180_device::*/prefix##_7c,&/*z180_device::*/prefix##_7d,&/*z180_device::*/prefix##_7e,&/*z180_device::*/prefix##_7f, \
+ &/*z180_device::*/prefix##_80,&/*z180_device::*/prefix##_81,&/*z180_device::*/prefix##_82,&/*z180_device::*/prefix##_83,&/*z180_device::*/prefix##_84,&/*z180_device::*/prefix##_85,&/*z180_device::*/prefix##_86,&/*z180_device::*/prefix##_87, \
+ &/*z180_device::*/prefix##_88,&/*z180_device::*/prefix##_89,&/*z180_device::*/prefix##_8a,&/*z180_device::*/prefix##_8b,&/*z180_device::*/prefix##_8c,&/*z180_device::*/prefix##_8d,&/*z180_device::*/prefix##_8e,&/*z180_device::*/prefix##_8f, \
+ &/*z180_device::*/prefix##_90,&/*z180_device::*/prefix##_91,&/*z180_device::*/prefix##_92,&/*z180_device::*/prefix##_93,&/*z180_device::*/prefix##_94,&/*z180_device::*/prefix##_95,&/*z180_device::*/prefix##_96,&/*z180_device::*/prefix##_97, \
+ &/*z180_device::*/prefix##_98,&/*z180_device::*/prefix##_99,&/*z180_device::*/prefix##_9a,&/*z180_device::*/prefix##_9b,&/*z180_device::*/prefix##_9c,&/*z180_device::*/prefix##_9d,&/*z180_device::*/prefix##_9e,&/*z180_device::*/prefix##_9f, \
+ &/*z180_device::*/prefix##_a0,&/*z180_device::*/prefix##_a1,&/*z180_device::*/prefix##_a2,&/*z180_device::*/prefix##_a3,&/*z180_device::*/prefix##_a4,&/*z180_device::*/prefix##_a5,&/*z180_device::*/prefix##_a6,&/*z180_device::*/prefix##_a7, \
+ &/*z180_device::*/prefix##_a8,&/*z180_device::*/prefix##_a9,&/*z180_device::*/prefix##_aa,&/*z180_device::*/prefix##_ab,&/*z180_device::*/prefix##_ac,&/*z180_device::*/prefix##_ad,&/*z180_device::*/prefix##_ae,&/*z180_device::*/prefix##_af, \
+ &/*z180_device::*/prefix##_b0,&/*z180_device::*/prefix##_b1,&/*z180_device::*/prefix##_b2,&/*z180_device::*/prefix##_b3,&/*z180_device::*/prefix##_b4,&/*z180_device::*/prefix##_b5,&/*z180_device::*/prefix##_b6,&/*z180_device::*/prefix##_b7, \
+ &/*z180_device::*/prefix##_b8,&/*z180_device::*/prefix##_b9,&/*z180_device::*/prefix##_ba,&/*z180_device::*/prefix##_bb,&/*z180_device::*/prefix##_bc,&/*z180_device::*/prefix##_bd,&/*z180_device::*/prefix##_be,&/*z180_device::*/prefix##_bf, \
+ &/*z180_device::*/prefix##_c0,&/*z180_device::*/prefix##_c1,&/*z180_device::*/prefix##_c2,&/*z180_device::*/prefix##_c3,&/*z180_device::*/prefix##_c4,&/*z180_device::*/prefix##_c5,&/*z180_device::*/prefix##_c6,&/*z180_device::*/prefix##_c7, \
+ &/*z180_device::*/prefix##_c8,&/*z180_device::*/prefix##_c9,&/*z180_device::*/prefix##_ca,&/*z180_device::*/prefix##_cb,&/*z180_device::*/prefix##_cc,&/*z180_device::*/prefix##_cd,&/*z180_device::*/prefix##_ce,&/*z180_device::*/prefix##_cf, \
+ &/*z180_device::*/prefix##_d0,&/*z180_device::*/prefix##_d1,&/*z180_device::*/prefix##_d2,&/*z180_device::*/prefix##_d3,&/*z180_device::*/prefix##_d4,&/*z180_device::*/prefix##_d5,&/*z180_device::*/prefix##_d6,&/*z180_device::*/prefix##_d7, \
+ &/*z180_device::*/prefix##_d8,&/*z180_device::*/prefix##_d9,&/*z180_device::*/prefix##_da,&/*z180_device::*/prefix##_db,&/*z180_device::*/prefix##_dc,&/*z180_device::*/prefix##_dd,&/*z180_device::*/prefix##_de,&/*z180_device::*/prefix##_df, \
+ &/*z180_device::*/prefix##_e0,&/*z180_device::*/prefix##_e1,&/*z180_device::*/prefix##_e2,&/*z180_device::*/prefix##_e3,&/*z180_device::*/prefix##_e4,&/*z180_device::*/prefix##_e5,&/*z180_device::*/prefix##_e6,&/*z180_device::*/prefix##_e7, \
+ &/*z180_device::*/prefix##_e8,&/*z180_device::*/prefix##_e9,&/*z180_device::*/prefix##_ea,&/*z180_device::*/prefix##_eb,&/*z180_device::*/prefix##_ec,&/*z180_device::*/prefix##_ed,&/*z180_device::*/prefix##_ee,&/*z180_device::*/prefix##_ef, \
+ &/*z180_device::*/prefix##_f0,&/*z180_device::*/prefix##_f1,&/*z180_device::*/prefix##_f2,&/*z180_device::*/prefix##_f3,&/*z180_device::*/prefix##_f4,&/*z180_device::*/prefix##_f5,&/*z180_device::*/prefix##_f6,&/*z180_device::*/prefix##_f7, \
+ &/*z180_device::*/prefix##_f8,&/*z180_device::*/prefix##_f9,&/*z180_device::*/prefix##_fa,&/*z180_device::*/prefix##_fb,&/*z180_device::*/prefix##_fc,&/*z180_device::*/prefix##_fd,&/*z180_device::*/prefix##_fe,&/*z180_device::*/prefix##_ff \
+}
+
+
+const /*z180_device::*/opcode_func /*z180_device::*/s_z180ops[Z180_PREFIX_COUNT][0x100] =
+{
+ TABLE(op),
+ TABLE(cb),
+ TABLE(dd),
+ TABLE(ed),
+ TABLE(fd),
+ TABLE(xycb)
+};
+
+/***************************************************************
+ * define an opcode function
+ ***************************************************************/
+#define OP(prefix,opcode) void /*z180_device::*/prefix##_##opcode()
+
+/***************************************************************
+ * adjust cycle count by n T-states
+ ***************************************************************/
+#define CC(prefix,opcode) m_extra_cycles += m_cc[Z180_TABLE_##prefix][opcode]
+
+/***************************************************************
+ * execute an opcode
+ ***************************************************************/
+
+#define EXEC_PROTOTYPE(prefix) \
+int /*z180_device::*/exec##_##prefix(const uint8_t opcode) \
+{ \
+ (/*this->*/*s_z180ops[Z180_PREFIX_##prefix][opcode])(); \
+ return m_cc[Z180_TABLE_##prefix][opcode]; \
+}
+
+EXEC_PROTOTYPE(op)
+EXEC_PROTOTYPE(cb)
+EXEC_PROTOTYPE(dd)
+EXEC_PROTOTYPE(ed)
+EXEC_PROTOTYPE(fd)
+EXEC_PROTOTYPE(xycb)
--- /dev/null
+// license:BSD-3-Clause
+// copyright-holders:Juergen Buchmueller
+/**********************************************************
+* opcodes with DD/FD CB prefix
+* rotate, shift and bit operations with (IX+o)
+**********************************************************/
+OP(xycb,00) { _B = RLC(RM(m_ea) ); WM( m_ea,_B ); } /* RLC B=(XY+o) */
+OP(xycb,01) { _C = RLC(RM(m_ea) ); WM( m_ea,_C ); } /* RLC C=(XY+o) */
+OP(xycb,02) { _D = RLC(RM(m_ea) ); WM( m_ea,_D ); } /* RLC D=(XY+o) */
+OP(xycb,03) { _E = RLC(RM(m_ea) ); WM( m_ea,_E ); } /* RLC E=(XY+o) */
+OP(xycb,04) { _H = RLC(RM(m_ea) ); WM( m_ea,_H ); } /* RLC H=(XY+o) */
+OP(xycb,05) { _L = RLC(RM(m_ea) ); WM( m_ea,_L ); } /* RLC L=(XY+o) */
+OP(xycb,06) { WM( m_ea, RLC(RM(m_ea) ) ); } /* RLC (XY+o) */
+OP(xycb,07) { _A = RLC(RM(m_ea) ); WM( m_ea,_A ); } /* RLC A=(XY+o) */
+
+OP(xycb,08) { _B = RRC(RM(m_ea) ); WM( m_ea,_B ); } /* RRC B=(XY+o) */
+OP(xycb,09) { _C = RRC(RM(m_ea) ); WM( m_ea,_C ); } /* RRC C=(XY+o) */
+OP(xycb,0a) { _D = RRC(RM(m_ea) ); WM( m_ea,_D ); } /* RRC D=(XY+o) */
+OP(xycb,0b) { _E = RRC(RM(m_ea) ); WM( m_ea,_E ); } /* RRC E=(XY+o) */
+OP(xycb,0c) { _H = RRC(RM(m_ea) ); WM( m_ea,_H ); } /* RRC H=(XY+o) */
+OP(xycb,0d) { _L = RRC(RM(m_ea) ); WM( m_ea,_L ); } /* RRC L=(XY+o) */
+OP(xycb,0e) { WM( m_ea,RRC(RM(m_ea) ) ); } /* RRC (XY+o) */
+OP(xycb,0f) { _A = RRC(RM(m_ea) ); WM( m_ea,_A ); } /* RRC A=(XY+o) */
+
+OP(xycb,10) { _B = RL(RM(m_ea) ); WM( m_ea,_B ); } /* RL B=(XY+o) */
+OP(xycb,11) { _C = RL(RM(m_ea) ); WM( m_ea,_C ); } /* RL C=(XY+o) */
+OP(xycb,12) { _D = RL(RM(m_ea) ); WM( m_ea,_D ); } /* RL D=(XY+o) */
+OP(xycb,13) { _E = RL(RM(m_ea) ); WM( m_ea,_E ); } /* RL E=(XY+o) */
+OP(xycb,14) { _H = RL(RM(m_ea) ); WM( m_ea,_H ); } /* RL H=(XY+o) */
+OP(xycb,15) { _L = RL(RM(m_ea) ); WM( m_ea,_L ); } /* RL L=(XY+o) */
+OP(xycb,16) { WM( m_ea,RL(RM(m_ea) ) ); } /* RL (XY+o) */
+OP(xycb,17) { _A = RL(RM(m_ea) ); WM( m_ea,_A ); } /* RL A=(XY+o) */
+
+OP(xycb,18) { _B = RR(RM(m_ea) ); WM( m_ea,_B ); } /* RR B=(XY+o) */
+OP(xycb,19) { _C = RR(RM(m_ea) ); WM( m_ea,_C ); } /* RR C=(XY+o) */
+OP(xycb,1a) { _D = RR(RM(m_ea) ); WM( m_ea,_D ); } /* RR D=(XY+o) */
+OP(xycb,1b) { _E = RR(RM(m_ea) ); WM( m_ea,_E ); } /* RR E=(XY+o) */
+OP(xycb,1c) { _H = RR(RM(m_ea) ); WM( m_ea,_H ); } /* RR H=(XY+o) */
+OP(xycb,1d) { _L = RR(RM(m_ea) ); WM( m_ea,_L ); } /* RR L=(XY+o) */
+OP(xycb,1e) { WM( m_ea,RR(RM(m_ea) ) ); } /* RR (XY+o) */
+OP(xycb,1f) { _A = RR(RM(m_ea) ); WM( m_ea,_A ); } /* RR A=(XY+o) */
+
+OP(xycb,20) { _B = SLA(RM(m_ea) ); WM( m_ea,_B ); } /* SLA B=(XY+o) */
+OP(xycb,21) { _C = SLA(RM(m_ea) ); WM( m_ea,_C ); } /* SLA C=(XY+o) */
+OP(xycb,22) { _D = SLA(RM(m_ea) ); WM( m_ea,_D ); } /* SLA D=(XY+o) */
+OP(xycb,23) { _E = SLA(RM(m_ea) ); WM( m_ea,_E ); } /* SLA E=(XY+o) */
+OP(xycb,24) { _H = SLA(RM(m_ea) ); WM( m_ea,_H ); } /* SLA H=(XY+o) */
+OP(xycb,25) { _L = SLA(RM(m_ea) ); WM( m_ea,_L ); } /* SLA L=(XY+o) */
+OP(xycb,26) { WM( m_ea,SLA(RM(m_ea) ) ); } /* SLA (XY+o) */
+OP(xycb,27) { _A = SLA(RM(m_ea) ); WM( m_ea,_A ); } /* SLA A=(XY+o) */
+
+OP(xycb,28) { _B = SRA(RM(m_ea) ); WM( m_ea,_B ); } /* SRA B=(XY+o) */
+OP(xycb,29) { _C = SRA(RM(m_ea) ); WM( m_ea,_C ); } /* SRA C=(XY+o) */
+OP(xycb,2a) { _D = SRA(RM(m_ea) ); WM( m_ea,_D ); } /* SRA D=(XY+o) */
+OP(xycb,2b) { _E = SRA(RM(m_ea) ); WM( m_ea,_E ); } /* SRA E=(XY+o) */
+OP(xycb,2c) { _H = SRA(RM(m_ea) ); WM( m_ea,_H ); } /* SRA H=(XY+o) */
+OP(xycb,2d) { _L = SRA(RM(m_ea) ); WM( m_ea,_L ); } /* SRA L=(XY+o) */
+OP(xycb,2e) { WM( m_ea,SRA(RM(m_ea) ) ); } /* SRA (XY+o) */
+OP(xycb,2f) { _A = SRA(RM(m_ea) ); WM( m_ea,_A ); } /* SRA A=(XY+o) */
+
+OP(xycb,30) { _B = SLL(RM(m_ea) ); WM( m_ea,_B ); } /* SLL B=(XY+o) */
+OP(xycb,31) { _C = SLL(RM(m_ea) ); WM( m_ea,_C ); } /* SLL C=(XY+o) */
+OP(xycb,32) { _D = SLL(RM(m_ea) ); WM( m_ea,_D ); } /* SLL D=(XY+o) */
+OP(xycb,33) { _E = SLL(RM(m_ea) ); WM( m_ea,_E ); } /* SLL E=(XY+o) */
+OP(xycb,34) { _H = SLL(RM(m_ea) ); WM( m_ea,_H ); } /* SLL H=(XY+o) */
+OP(xycb,35) { _L = SLL(RM(m_ea) ); WM( m_ea,_L ); } /* SLL L=(XY+o) */
+OP(xycb,36) { WM( m_ea,SLL(RM(m_ea) ) ); } /* SLL (XY+o) */
+OP(xycb,37) { _A = SLL(RM(m_ea) ); WM( m_ea,_A ); } /* SLL A=(XY+o) */
+
+OP(xycb,38) { _B = SRL(RM(m_ea) ); WM( m_ea,_B ); } /* SRL B=(XY+o) */
+OP(xycb,39) { _C = SRL(RM(m_ea) ); WM( m_ea,_C ); } /* SRL C=(XY+o) */
+OP(xycb,3a) { _D = SRL(RM(m_ea) ); WM( m_ea,_D ); } /* SRL D=(XY+o) */
+OP(xycb,3b) { _E = SRL(RM(m_ea) ); WM( m_ea,_E ); } /* SRL E=(XY+o) */
+OP(xycb,3c) { _H = SRL(RM(m_ea) ); WM( m_ea,_H ); } /* SRL H=(XY+o) */
+OP(xycb,3d) { _L = SRL(RM(m_ea) ); WM( m_ea,_L ); } /* SRL L=(XY+o) */
+OP(xycb,3e) { WM( m_ea,SRL(RM(m_ea) ) ); } /* SRL (XY+o) */
+OP(xycb,3f) { _A = SRL(RM(m_ea) ); WM( m_ea,_A ); } /* SRL A=(XY+o) */
+
+OP(xycb,40) { xycb_46(); } /* BIT 0,B=(XY+o) */
+OP(xycb,41) { xycb_46(); } /* BIT 0,C=(XY+o) */
+OP(xycb,42) { xycb_46(); } /* BIT 0,D=(XY+o) */
+OP(xycb,43) { xycb_46(); } /* BIT 0,E=(XY+o) */
+OP(xycb,44) { xycb_46(); } /* BIT 0,H=(XY+o) */
+OP(xycb,45) { xycb_46(); } /* BIT 0,L=(XY+o) */
+OP(xycb,46) { BIT_XY(0,RM(m_ea)); } /* BIT 0,(XY+o) */
+OP(xycb,47) { xycb_46(); } /* BIT 0,A=(XY+o) */
+
+OP(xycb,48) { xycb_4e(); } /* BIT 1,B=(XY+o) */
+OP(xycb,49) { xycb_4e(); } /* BIT 1,C=(XY+o) */
+OP(xycb,4a) { xycb_4e(); } /* BIT 1,D=(XY+o) */
+OP(xycb,4b) { xycb_4e(); } /* BIT 1,E=(XY+o) */
+OP(xycb,4c) { xycb_4e(); } /* BIT 1,H=(XY+o) */
+OP(xycb,4d) { xycb_4e(); } /* BIT 1,L=(XY+o) */
+OP(xycb,4e) { BIT_XY(1,RM(m_ea)); } /* BIT 1,(XY+o) */
+OP(xycb,4f) { xycb_4e(); } /* BIT 1,A=(XY+o) */
+
+OP(xycb,50) { xycb_56(); } /* BIT 2,B=(XY+o) */
+OP(xycb,51) { xycb_56(); } /* BIT 2,C=(XY+o) */
+OP(xycb,52) { xycb_56(); } /* BIT 2,D=(XY+o) */
+OP(xycb,53) { xycb_56(); } /* BIT 2,E=(XY+o) */
+OP(xycb,54) { xycb_56(); } /* BIT 2,H=(XY+o) */
+OP(xycb,55) { xycb_56(); } /* BIT 2,L=(XY+o) */
+OP(xycb,56) { BIT_XY(2,RM(m_ea)); } /* BIT 2,(XY+o) */
+OP(xycb,57) { xycb_56(); } /* BIT 2,A=(XY+o) */
+
+OP(xycb,58) { xycb_5e(); } /* BIT 3,B=(XY+o) */
+OP(xycb,59) { xycb_5e(); } /* BIT 3,C=(XY+o) */
+OP(xycb,5a) { xycb_5e(); } /* BIT 3,D=(XY+o) */
+OP(xycb,5b) { xycb_5e(); } /* BIT 3,E=(XY+o) */
+OP(xycb,5c) { xycb_5e(); } /* BIT 3,H=(XY+o) */
+OP(xycb,5d) { xycb_5e(); } /* BIT 3,L=(XY+o) */
+OP(xycb,5e) { BIT_XY(3,RM(m_ea)); } /* BIT 3,(XY+o) */
+OP(xycb,5f) { xycb_5e(); } /* BIT 3,A=(XY+o) */
+
+OP(xycb,60) { xycb_66(); } /* BIT 4,B=(XY+o) */
+OP(xycb,61) { xycb_66(); } /* BIT 4,C=(XY+o) */
+OP(xycb,62) { xycb_66(); } /* BIT 4,D=(XY+o) */
+OP(xycb,63) { xycb_66(); } /* BIT 4,E=(XY+o) */
+OP(xycb,64) { xycb_66(); } /* BIT 4,H=(XY+o) */
+OP(xycb,65) { xycb_66(); } /* BIT 4,L=(XY+o) */
+OP(xycb,66) { BIT_XY(4,RM(m_ea)); } /* BIT 4,(XY+o) */
+OP(xycb,67) { xycb_66(); } /* BIT 4,A=(XY+o) */
+
+OP(xycb,68) { xycb_6e(); } /* BIT 5,B=(XY+o) */
+OP(xycb,69) { xycb_6e(); } /* BIT 5,C=(XY+o) */
+OP(xycb,6a) { xycb_6e(); } /* BIT 5,D=(XY+o) */
+OP(xycb,6b) { xycb_6e(); } /* BIT 5,E=(XY+o) */
+OP(xycb,6c) { xycb_6e(); } /* BIT 5,H=(XY+o) */
+OP(xycb,6d) { xycb_6e(); } /* BIT 5,L=(XY+o) */
+OP(xycb,6e) { BIT_XY(5,RM(m_ea)); } /* BIT 5,(XY+o) */
+OP(xycb,6f) { xycb_6e(); } /* BIT 5,A=(XY+o) */
+
+OP(xycb,70) { xycb_76(); } /* BIT 6,B=(XY+o) */
+OP(xycb,71) { xycb_76(); } /* BIT 6,C=(XY+o) */
+OP(xycb,72) { xycb_76(); } /* BIT 6,D=(XY+o) */
+OP(xycb,73) { xycb_76(); } /* BIT 6,E=(XY+o) */
+OP(xycb,74) { xycb_76(); } /* BIT 6,H=(XY+o) */
+OP(xycb,75) { xycb_76(); } /* BIT 6,L=(XY+o) */
+OP(xycb,76) { BIT_XY(6,RM(m_ea)); } /* BIT 6,(XY+o) */
+OP(xycb,77) { xycb_76(); } /* BIT 6,A=(XY+o) */
+
+OP(xycb,78) { xycb_7e(); } /* BIT 7,B=(XY+o) */
+OP(xycb,79) { xycb_7e(); } /* BIT 7,C=(XY+o) */
+OP(xycb,7a) { xycb_7e(); } /* BIT 7,D=(XY+o) */
+OP(xycb,7b) { xycb_7e(); } /* BIT 7,E=(XY+o) */
+OP(xycb,7c) { xycb_7e(); } /* BIT 7,H=(XY+o) */
+OP(xycb,7d) { xycb_7e(); } /* BIT 7,L=(XY+o) */
+OP(xycb,7e) { BIT_XY(7,RM(m_ea)); } /* BIT 7,(XY+o) */
+OP(xycb,7f) { xycb_7e(); } /* BIT 7,A=(XY+o) */
+
+OP(xycb,80) { _B = RES(0, RM(m_ea) ); WM( m_ea,_B ); } /* RES 0,B=(XY+o) */
+OP(xycb,81) { _C = RES(0, RM(m_ea) ); WM( m_ea,_C ); } /* RES 0,C=(XY+o) */
+OP(xycb,82) { _D = RES(0, RM(m_ea) ); WM( m_ea,_D ); } /* RES 0,D=(XY+o) */
+OP(xycb,83) { _E = RES(0, RM(m_ea) ); WM( m_ea,_E ); } /* RES 0,E=(XY+o) */
+OP(xycb,84) { _H = RES(0, RM(m_ea) ); WM( m_ea,_H ); } /* RES 0,H=(XY+o) */
+OP(xycb,85) { _L = RES(0, RM(m_ea) ); WM( m_ea,_L ); } /* RES 0,L=(XY+o) */
+OP(xycb,86) { WM( m_ea, RES(0,RM(m_ea)) ); } /* RES 0,(XY+o) */
+OP(xycb,87) { _A = RES(0, RM(m_ea) ); WM( m_ea,_A ); } /* RES 0,A=(XY+o) */
+
+OP(xycb,88) { _B = RES(1, RM(m_ea) ); WM( m_ea,_B ); } /* RES 1,B=(XY+o) */
+OP(xycb,89) { _C = RES(1, RM(m_ea) ); WM( m_ea,_C ); } /* RES 1,C=(XY+o) */
+OP(xycb,8a) { _D = RES(1, RM(m_ea) ); WM( m_ea,_D ); } /* RES 1,D=(XY+o) */
+OP(xycb,8b) { _E = RES(1, RM(m_ea) ); WM( m_ea,_E ); } /* RES 1,E=(XY+o) */
+OP(xycb,8c) { _H = RES(1, RM(m_ea) ); WM( m_ea,_H ); } /* RES 1,H=(XY+o) */
+OP(xycb,8d) { _L = RES(1, RM(m_ea) ); WM( m_ea,_L ); } /* RES 1,L=(XY+o) */
+OP(xycb,8e) { WM( m_ea, RES(1,RM(m_ea)) ); } /* RES 1,(XY+o) */
+OP(xycb,8f) { _A = RES(1, RM(m_ea) ); WM( m_ea,_A ); } /* RES 1,A=(XY+o) */
+
+OP(xycb,90) { _B = RES(2, RM(m_ea) ); WM( m_ea,_B ); } /* RES 2,B=(XY+o) */
+OP(xycb,91) { _C = RES(2, RM(m_ea) ); WM( m_ea,_C ); } /* RES 2,C=(XY+o) */
+OP(xycb,92) { _D = RES(2, RM(m_ea) ); WM( m_ea,_D ); } /* RES 2,D=(XY+o) */
+OP(xycb,93) { _E = RES(2, RM(m_ea) ); WM( m_ea,_E ); } /* RES 2,E=(XY+o) */
+OP(xycb,94) { _H = RES(2, RM(m_ea) ); WM( m_ea,_H ); } /* RES 2,H=(XY+o) */
+OP(xycb,95) { _L = RES(2, RM(m_ea) ); WM( m_ea,_L ); } /* RES 2,L=(XY+o) */
+OP(xycb,96) { WM( m_ea, RES(2,RM(m_ea)) ); } /* RES 2,(XY+o) */
+OP(xycb,97) { _A = RES(2, RM(m_ea) ); WM( m_ea,_A ); } /* RES 2,A=(XY+o) */
+
+OP(xycb,98) { _B = RES(3, RM(m_ea) ); WM( m_ea,_B ); } /* RES 3,B=(XY+o) */
+OP(xycb,99) { _C = RES(3, RM(m_ea) ); WM( m_ea,_C ); } /* RES 3,C=(XY+o) */
+OP(xycb,9a) { _D = RES(3, RM(m_ea) ); WM( m_ea,_D ); } /* RES 3,D=(XY+o) */
+OP(xycb,9b) { _E = RES(3, RM(m_ea) ); WM( m_ea,_E ); } /* RES 3,E=(XY+o) */
+OP(xycb,9c) { _H = RES(3, RM(m_ea) ); WM( m_ea,_H ); } /* RES 3,H=(XY+o) */
+OP(xycb,9d) { _L = RES(3, RM(m_ea) ); WM( m_ea,_L ); } /* RES 3,L=(XY+o) */
+OP(xycb,9e) { WM( m_ea, RES(3,RM(m_ea)) ); } /* RES 3,(XY+o) */
+OP(xycb,9f) { _A = RES(3, RM(m_ea) ); WM( m_ea,_A ); } /* RES 3,A=(XY+o) */
+
+OP(xycb,a0) { _B = RES(4, RM(m_ea) ); WM( m_ea,_B ); } /* RES 4,B=(XY+o) */
+OP(xycb,a1) { _C = RES(4, RM(m_ea) ); WM( m_ea,_C ); } /* RES 4,C=(XY+o) */
+OP(xycb,a2) { _D = RES(4, RM(m_ea) ); WM( m_ea,_D ); } /* RES 4,D=(XY+o) */
+OP(xycb,a3) { _E = RES(4, RM(m_ea) ); WM( m_ea,_E ); } /* RES 4,E=(XY+o) */
+OP(xycb,a4) { _H = RES(4, RM(m_ea) ); WM( m_ea,_H ); } /* RES 4,H=(XY+o) */
+OP(xycb,a5) { _L = RES(4, RM(m_ea) ); WM( m_ea,_L ); } /* RES 4,L=(XY+o) */
+OP(xycb,a6) { WM( m_ea, RES(4,RM(m_ea)) ); } /* RES 4,(XY+o) */
+OP(xycb,a7) { _A = RES(4, RM(m_ea) ); WM( m_ea,_A ); } /* RES 4,A=(XY+o) */
+
+OP(xycb,a8) { _B = RES(5, RM(m_ea) ); WM( m_ea,_B ); } /* RES 5,B=(XY+o) */
+OP(xycb,a9) { _C = RES(5, RM(m_ea) ); WM( m_ea,_C ); } /* RES 5,C=(XY+o) */
+OP(xycb,aa) { _D = RES(5, RM(m_ea) ); WM( m_ea,_D ); } /* RES 5,D=(XY+o) */
+OP(xycb,ab) { _E = RES(5, RM(m_ea) ); WM( m_ea,_E ); } /* RES 5,E=(XY+o) */
+OP(xycb,ac) { _H = RES(5, RM(m_ea) ); WM( m_ea,_H ); } /* RES 5,H=(XY+o) */
+OP(xycb,ad) { _L = RES(5, RM(m_ea) ); WM( m_ea,_L ); } /* RES 5,L=(XY+o) */
+OP(xycb,ae) { WM( m_ea, RES(5,RM(m_ea)) ); } /* RES 5,(XY+o) */
+OP(xycb,af) { _A = RES(5, RM(m_ea) ); WM( m_ea,_A ); } /* RES 5,A=(XY+o) */
+
+OP(xycb,b0) { _B = RES(6, RM(m_ea) ); WM( m_ea,_B ); } /* RES 6,B=(XY+o) */
+OP(xycb,b1) { _C = RES(6, RM(m_ea) ); WM( m_ea,_C ); } /* RES 6,C=(XY+o) */
+OP(xycb,b2) { _D = RES(6, RM(m_ea) ); WM( m_ea,_D ); } /* RES 6,D=(XY+o) */
+OP(xycb,b3) { _E = RES(6, RM(m_ea) ); WM( m_ea,_E ); } /* RES 6,E=(XY+o) */
+OP(xycb,b4) { _H = RES(6, RM(m_ea) ); WM( m_ea,_H ); } /* RES 6,H=(XY+o) */
+OP(xycb,b5) { _L = RES(6, RM(m_ea) ); WM( m_ea,_L ); } /* RES 6,L=(XY+o) */
+OP(xycb,b6) { WM( m_ea, RES(6,RM(m_ea)) ); } /* RES 6,(XY+o) */
+OP(xycb,b7) { _A = RES(6, RM(m_ea) ); WM( m_ea,_A ); } /* RES 6,A=(XY+o) */
+
+OP(xycb,b8) { _B = RES(7, RM(m_ea) ); WM( m_ea,_B ); } /* RES 7,B=(XY+o) */
+OP(xycb,b9) { _C = RES(7, RM(m_ea) ); WM( m_ea,_C ); } /* RES 7,C=(XY+o) */
+OP(xycb,ba) { _D = RES(7, RM(m_ea) ); WM( m_ea,_D ); } /* RES 7,D=(XY+o) */
+OP(xycb,bb) { _E = RES(7, RM(m_ea) ); WM( m_ea,_E ); } /* RES 7,E=(XY+o) */
+OP(xycb,bc) { _H = RES(7, RM(m_ea) ); WM( m_ea,_H ); } /* RES 7,H=(XY+o) */
+OP(xycb,bd) { _L = RES(7, RM(m_ea) ); WM( m_ea,_L ); } /* RES 7,L=(XY+o) */
+OP(xycb,be) { WM( m_ea, RES(7,RM(m_ea)) ); } /* RES 7,(XY+o) */
+OP(xycb,bf) { _A = RES(7, RM(m_ea) ); WM( m_ea,_A ); } /* RES 7,A=(XY+o) */
+
+OP(xycb,c0) { _B = SET(0, RM(m_ea) ); WM( m_ea,_B ); } /* SET 0,B=(XY+o) */
+OP(xycb,c1) { _C = SET(0, RM(m_ea) ); WM( m_ea,_C ); } /* SET 0,C=(XY+o) */
+OP(xycb,c2) { _D = SET(0, RM(m_ea) ); WM( m_ea,_D ); } /* SET 0,D=(XY+o) */
+OP(xycb,c3) { _E = SET(0, RM(m_ea) ); WM( m_ea,_E ); } /* SET 0,E=(XY+o) */
+OP(xycb,c4) { _H = SET(0, RM(m_ea) ); WM( m_ea,_H ); } /* SET 0,H=(XY+o) */
+OP(xycb,c5) { _L = SET(0, RM(m_ea) ); WM( m_ea,_L ); } /* SET 0,L=(XY+o) */
+OP(xycb,c6) { WM( m_ea, SET(0,RM(m_ea)) ); } /* SET 0,(XY+o) */
+OP(xycb,c7) { _A = SET(0, RM(m_ea) ); WM( m_ea,_A ); } /* SET 0,A=(XY+o) */
+
+OP(xycb,c8) { _B = SET(1, RM(m_ea) ); WM( m_ea,_B ); } /* SET 1,B=(XY+o) */
+OP(xycb,c9) { _C = SET(1, RM(m_ea) ); WM( m_ea,_C ); } /* SET 1,C=(XY+o) */
+OP(xycb,ca) { _D = SET(1, RM(m_ea) ); WM( m_ea,_D ); } /* SET 1,D=(XY+o) */
+OP(xycb,cb) { _E = SET(1, RM(m_ea) ); WM( m_ea,_E ); } /* SET 1,E=(XY+o) */
+OP(xycb,cc) { _H = SET(1, RM(m_ea) ); WM( m_ea,_H ); } /* SET 1,H=(XY+o) */
+OP(xycb,cd) { _L = SET(1, RM(m_ea) ); WM( m_ea,_L ); } /* SET 1,L=(XY+o) */
+OP(xycb,ce) { WM( m_ea, SET(1,RM(m_ea)) ); } /* SET 1,(XY+o) */
+OP(xycb,cf) { _A = SET(1, RM(m_ea) ); WM( m_ea,_A ); } /* SET 1,A=(XY+o) */
+
+OP(xycb,d0) { _B = SET(2, RM(m_ea) ); WM( m_ea,_B ); } /* SET 2,B=(XY+o) */
+OP(xycb,d1) { _C = SET(2, RM(m_ea) ); WM( m_ea,_C ); } /* SET 2,C=(XY+o) */
+OP(xycb,d2) { _D = SET(2, RM(m_ea) ); WM( m_ea,_D ); } /* SET 2,D=(XY+o) */
+OP(xycb,d3) { _E = SET(2, RM(m_ea) ); WM( m_ea,_E ); } /* SET 2,E=(XY+o) */
+OP(xycb,d4) { _H = SET(2, RM(m_ea) ); WM( m_ea,_H ); } /* SET 2,H=(XY+o) */
+OP(xycb,d5) { _L = SET(2, RM(m_ea) ); WM( m_ea,_L ); } /* SET 2,L=(XY+o) */
+OP(xycb,d6) { WM( m_ea, SET(2,RM(m_ea)) ); } /* SET 2,(XY+o) */
+OP(xycb,d7) { _A = SET(2, RM(m_ea) ); WM( m_ea,_A ); } /* SET 2,A=(XY+o) */
+
+OP(xycb,d8) { _B = SET(3, RM(m_ea) ); WM( m_ea,_B ); } /* SET 3,B=(XY+o) */
+OP(xycb,d9) { _C = SET(3, RM(m_ea) ); WM( m_ea,_C ); } /* SET 3,C=(XY+o) */
+OP(xycb,da) { _D = SET(3, RM(m_ea) ); WM( m_ea,_D ); } /* SET 3,D=(XY+o) */
+OP(xycb,db) { _E = SET(3, RM(m_ea) ); WM( m_ea,_E ); } /* SET 3,E=(XY+o) */
+OP(xycb,dc) { _H = SET(3, RM(m_ea) ); WM( m_ea,_H ); } /* SET 3,H=(XY+o) */
+OP(xycb,dd) { _L = SET(3, RM(m_ea) ); WM( m_ea,_L ); } /* SET 3,L=(XY+o) */
+OP(xycb,de) { WM( m_ea, SET(3,RM(m_ea)) ); } /* SET 3,(XY+o) */
+OP(xycb,df) { _A = SET(3, RM(m_ea) ); WM( m_ea,_A ); } /* SET 3,A=(XY+o) */
+
+OP(xycb,e0) { _B = SET(4, RM(m_ea) ); WM( m_ea,_B ); } /* SET 4,B=(XY+o) */
+OP(xycb,e1) { _C = SET(4, RM(m_ea) ); WM( m_ea,_C ); } /* SET 4,C=(XY+o) */
+OP(xycb,e2) { _D = SET(4, RM(m_ea) ); WM( m_ea,_D ); } /* SET 4,D=(XY+o) */
+OP(xycb,e3) { _E = SET(4, RM(m_ea) ); WM( m_ea,_E ); } /* SET 4,E=(XY+o) */
+OP(xycb,e4) { _H = SET(4, RM(m_ea) ); WM( m_ea,_H ); } /* SET 4,H=(XY+o) */
+OP(xycb,e5) { _L = SET(4, RM(m_ea) ); WM( m_ea,_L ); } /* SET 4,L=(XY+o) */
+OP(xycb,e6) { WM( m_ea, SET(4,RM(m_ea)) ); } /* SET 4,(XY+o) */
+OP(xycb,e7) { _A = SET(4, RM(m_ea) ); WM( m_ea,_A ); } /* SET 4,A=(XY+o) */
+
+OP(xycb,e8) { _B = SET(5, RM(m_ea) ); WM( m_ea,_B ); } /* SET 5,B=(XY+o) */
+OP(xycb,e9) { _C = SET(5, RM(m_ea) ); WM( m_ea,_C ); } /* SET 5,C=(XY+o) */
+OP(xycb,ea) { _D = SET(5, RM(m_ea) ); WM( m_ea,_D ); } /* SET 5,D=(XY+o) */
+OP(xycb,eb) { _E = SET(5, RM(m_ea) ); WM( m_ea,_E ); } /* SET 5,E=(XY+o) */
+OP(xycb,ec) { _H = SET(5, RM(m_ea) ); WM( m_ea,_H ); } /* SET 5,H=(XY+o) */
+OP(xycb,ed) { _L = SET(5, RM(m_ea) ); WM( m_ea,_L ); } /* SET 5,L=(XY+o) */
+OP(xycb,ee) { WM( m_ea, SET(5,RM(m_ea)) ); } /* SET 5,(XY+o) */
+OP(xycb,ef) { _A = SET(5, RM(m_ea) ); WM( m_ea,_A ); } /* SET 5,A=(XY+o) */
+
+OP(xycb,f0) { _B = SET(6, RM(m_ea) ); WM( m_ea,_B ); } /* SET 6,B=(XY+o) */
+OP(xycb,f1) { _C = SET(6, RM(m_ea) ); WM( m_ea,_C ); } /* SET 6,C=(XY+o) */
+OP(xycb,f2) { _D = SET(6, RM(m_ea) ); WM( m_ea,_D ); } /* SET 6,D=(XY+o) */
+OP(xycb,f3) { _E = SET(6, RM(m_ea) ); WM( m_ea,_E ); } /* SET 6,E=(XY+o) */
+OP(xycb,f4) { _H = SET(6, RM(m_ea) ); WM( m_ea,_H ); } /* SET 6,H=(XY+o) */
+OP(xycb,f5) { _L = SET(6, RM(m_ea) ); WM( m_ea,_L ); } /* SET 6,L=(XY+o) */
+OP(xycb,f6) { WM( m_ea, SET(6,RM(m_ea)) ); } /* SET 6,(XY+o) */
+OP(xycb,f7) { _A = SET(6, RM(m_ea) ); WM( m_ea,_A ); } /* SET 6,A=(XY+o) */
+
+OP(xycb,f8) { _B = SET(7, RM(m_ea) ); WM( m_ea,_B ); } /* SET 7,B=(XY+o) */
+OP(xycb,f9) { _C = SET(7, RM(m_ea) ); WM( m_ea,_C ); } /* SET 7,C=(XY+o) */
+OP(xycb,fa) { _D = SET(7, RM(m_ea) ); WM( m_ea,_D ); } /* SET 7,D=(XY+o) */
+OP(xycb,fb) { _E = SET(7, RM(m_ea) ); WM( m_ea,_E ); } /* SET 7,E=(XY+o) */
+OP(xycb,fc) { _H = SET(7, RM(m_ea) ); WM( m_ea,_H ); } /* SET 7,H=(XY+o) */
+OP(xycb,fd) { _L = SET(7, RM(m_ea) ); WM( m_ea,_L ); } /* SET 7,L=(XY+o) */
+OP(xycb,fe) { WM( m_ea, SET(7,RM(m_ea)) ); } /* SET 7,(XY+o) */
+OP(xycb,ff) { _A = SET(7, RM(m_ea) ); WM( m_ea,_A ); } /* SET 7,A=(XY+o) */
public / Apout.git / commitdiff