1 .\" $Id: z8000_as.6,v 1.3 1994/06/24 14:02:28 ceriel Exp $
2 .TH Z8000_AS 6 "$Revision: 1.3 $"
5 z8000_as \- assembler for Zilog z8000 (segmented version)
7 ~em/lib.bin/z8000/as [options] argument ...
9 This assembler is made with the general framework
10 described in \fIuni_ass\fP(6). It is an assembler\-loader. Output is
11 in \fIack.out\fP(5) format, but not relocatable.
14 Instruction mnemonics are implemented exactly as described in
15 \fIZ8000 PLZ/ASM Assembly Language Programming Manual\fP and
16 \fIAmZ8001/2 Processor Instruction Set\fP.
18 The z8000 has sixteen 16-bit general purpose registers specified
19 as R0 through R15. All sixteen registers can be used as accumulators.
20 In addition to this, fifteen of the sixteen registers may be used
21 in addressing mode calculations as either indirect, index or
22 base-address registers. Because the instruction format encoding
23 uses the value zero to differentiate between various addressing
24 modes, register R0 (or the register pair RR0) cannot be used as an
25 indirect, index or base-address register.
26 It is also possible to address registers as groups of 8, 32 or 64 bits.
27 These registers are specified as follows.
29 .ta 8n 16n 24n 32n 40n 48n
30 - RH0, RL0, RH1, RL1, ..., RH7, RL7 for 8-bit regis-
31 ters. (\fIH\fP stands for high-order byte, and \fIL\fP stands
32 for low-order byte within a word register). These
33 registers overlap 16-bit registers R0 through R7.
34 - RR0, RR2, ..., RR14 for 32-bit register pairs.
35 - RQ0, RQ4, RQ8 and RQ12 for 64-bit register quadruples.
37 Besides register pair RR14 is used as stackpointer.
38 .IP "addressing modes"
40 .ta 8n 16n 24n 32n 40n 48n
41 syntax meaning (name-mnemonic)
43 $expr the value of expr is the operand.
46 reg contents of register reg is operand. Any
47 register as described above is allowed.
50 *reg32 contents of register pair reg32 is add-
51 ress of operand. Any register pair can
53 (indirect register-IR)
55 expr expr is address of operand.
58 expr(reg16) value of expr + contents of word regis-
59 ter reg16 yields address of operand.
60 Any word register can be used except R0.
63 expr expr is address of operand. This mode
64 is implied by its instruction. It is
65 only used by CALR, DJNZ, JR, LDAR and
66 LDR and is the only mode available to
67 these instructions. In fact this mode
68 differs not from the mode DA.
71 reg32($expr) contents of register pair reg32 + value
72 of expr yields address of operand. Any
73 register pair can be used except RR0.
76 reg32(reg16) contents of register pair reg32 + con-
77 tents of word register reg16 yields
78 address of operand. Any register pair/
79 word register can be used except RR0/R0.
80 (based indexed address-BX)
83 .IP "segmented addresses"
84 Segmented addresses require 23 bits, 7 bits for the segment number
85 and 16 bits for the offset within a segment.
86 So segment 0 contains addresses 0-FFFF, segment 1 contains addresses
87 10000-1FFFF, and so on.
89 Assembler syntax of addresses and immediate data is as described above
91 Thus the assembler treats e.g. address 2BC0F as an address in segment 2
92 with offset BC0F within the segment.
93 There is also an explicit way to express this using the, more unusual,
94 syntax <<segment>>offset.
96 There are two internal representations of segmented addresses
97 depending on the size of the offset. If the offset fits into 8 bits
98 the address is stored in one word (the low-order byte containing
99 the offset, bits 8 to 14 containing the segment number and
100 bit 15 containing a zero) otherwise the address is stored in two
101 words (the lower word containing the offset, the upper word as
102 before but bit 15 containing 1 indicating that the offset is in
104 This is important for instructions which has an operand of mode DA
106 .IP "extended branches"
107 When the target address in a relative jump/call (JR/CALR)
108 does not fit into the instruction format, the assembler generates
109 a corresponding `normal' jump/call (JP/CALL).
111 An example of z8000 assembly code.
113 .ta 8n 16n 24n 32n 40n 48n
115 ! This z8000 assembly routine converts a positive number
116 !(in R1) to a string representing the number and puts this
117 !string into a buffer (R3 contains the starting address of
118 !this buffer. The base is in R4 determining %x, %d or %o.
122 exts RR0 !sign-extend R1
123 div RR0, R4 !divide by the base
124 test R1 !R1 contains the quotient
126 !if quotient is 0 convert is ready
127 !else push remainder onto the stack
129 calr convert !and again...
131 5: add R0, $060 !add `0'
132 cp R0, $071 !compare to `9'
134 add R0, $7 !in case of %x `A'-`F'
135 8: ldb 0(R3), RL0 !put character into buffer
145 Z8000 PLZ/ASM Assembly Language Programming Manual, april 1979.
147 AmZ8001/2 Processor Instruction Set, 1979.
149 You cannot use (reg16) instead of 0(reg16).
151 Condition codes \fIZ\fP (meaning zero), \fIC\fP (meaning carry) and <nothing>
152 (meaning always false) are not implemented.
153 The first two because they also represent flags and the third one
154 because it's useless.
155 So for \fIZ\fP/\fIC\fP use \fIEQ\fP/\fIULT\fP.
157 The z8000 assembly instruction set as described in the book
158 \fIAmZ8001/2 Processor Instruction Set\fP differs from the one
159 described in the manual \fIZ8000 PLZ/ASM Assembly Language Programming
160 Manual\fP in that the book includes CLRL, LDL (format F5.1) and
161 PUSHL (format F5.1) which all in fact do not (!) work.
163 On the other side the book excludes SIN, SIND, SINDR, SINI, SINIR,
164 SOUT, SOUTD, SOTDR, SOUTI and SOTIR.
165 Whether these instructions do work as described in the manual has not