1 .\" $Id: pdp_as.6,v 1.4 1994/06/24 14:02:16 ceriel Exp $
2 .TH PDP_AS 6 "$Revision: 1.4 $"
5 pdp_as \- assembler for PDP 11
7 ~em/lib.bin/pdp/as [options] argument ...
9 This assembler is made with the general framework
10 described in \fIuni_ass\fP(6). It is an assembler generating relocatable
11 object code in \fIack.out\fP(5) format.
14 The pdp11 has seven general registers, numbered r0 through r7.
15 Of these, r6 is the stack pointer and can also be referenced to by \fIsp\fP,
16 r7 is the program counter and has \fIpc\fP as synonym. There are also six
17 floating-point registers fr0 through fr5, but the names r0 through r5 can
18 also be used. From the context will be derived what kind of register is meant.
19 .IP "addressing modes"
21 .ta 8n 16n 24n 32n 40n 48n
24 reg contents of register reg is operand.
27 (reg) contents of reg is address of operand.
30 (reg)+ as (reg), but after the operand is fetched
31 the contents of reg is incremented by the
32 size of the operand. (auto-increment)
34 *(reg)+ contents of reg points to address of the operand.
35 after the operand is fetched, reg is incremented
36 by two. (auto-increment deferred)
38 -(reg) as (reg), but before the operand is fetched
39 the contents of reg is decremented by the
40 size of the operand. (auto-decrement)
42 *-(reg) before the operand is fetched, reg is decremented
43 by two. then the contents of reg points to the
44 address of the operand. (auto-decrement deferred)
46 expr(reg) value of expr + contents of reg yields address
49 *expr(reg) value of expr + contents of reg yields pointer
50 to address of operand. (index deferred)
52 $expr the value of expr is the operand. (immediate)
54 *$expr the value of expr is the address of the operand.
57 expr expr is address of operand. (relative)
59 *expr expr points to the address of the operand.
63 .IP "condition code instructions"
64 Two or more of the "clear" instructions (clc, cln, clv, clz), or
65 two or more of the "set" instructions (sec, sen, sev, sez) may be
66 or-ed together with `|' to yield a instruction that clears or sets two or more
67 of the condition-bits. Scc and ccc are not predefined.
68 .IP "extended branches"
69 The assembler recognizes conditional branches with a "j" substituted for
70 the "b". When the target is too remote for a simple branch, a converse branch
71 over a jmp to the target is generated. Likewise jbr assembles into either br
73 .IP "floating-point instructions"
74 The names of several floating-point instructions differ from the names
75 in the handbook mentioned below. Synonyms ending in "d" for instructions ending
76 in "f" are not recognized. Some instructions have different names; the mapping
79 .ta 8n 16n 24n 32n 40n 48n
102 The movf instruction assembles into stf, when the first operand is one of the
103 first three floating-point registers, otherwise it assembles into ldf.
105 This instruction is synonymous with trap.
107 An example of pdp11 assembly code.
109 .ta 8n 16n 24n 32n 40n 48n
111 !this is the routine that reads numbers into r0
112 !the number is terminated by any non digit
113 !the non digit is left in r1
115 innum: clr r3 !r3 will accumulate the number
116 inloop: jsr pc,_getchar !read a character into r0
117 cmp r0,$0121 !is it a Q?
119 cmp r0,$48 !is the character a digit?
120 jlt indone !digits 0-9 have codes 060-071 octal
123 mul $10,r3 !r3 = 10 * r3
124 sub $48,r3 !convert ascii code to numerical value
125 add r0,r3 !r3 = old sum * 10 + new digi
128 indone: mov r0,r1 !put the first non digit into r1
129 mov r3,r0 !put the number read into r0
130 rts pc !return to caller
138 PDP11/60 processor handbook, Digital Equipment Corporation, 1977
140 You cannot use *reg in place of (reg). Likewise *(reg) is not understood as
143 Expressions are computed in two bytes, even the ones in .data4 lists.