mach/z8000/as/mach3.c

   1 /*
   2  * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
   3  * See the copyright notice in the ACK home directory, in the file "Copyright".
   4  */
   5 #define RCSID3 "$Id: mach3.c,v 0.3 1994/06/24 13:56:22 ceriel Exp $"
   6
   7 /*
   8 ** Zilog z8000 keywords
   9 */
  10 0,              R8,             8,              "RL0",
  11 0,              R8,             0,              "RH0",
  12 0,              R8,             9,              "RL1",
  13 0,              R8,             1,              "RH1",
  14 0,              R8,             10,             "RL2",
  15 0,              R8,             2,              "RH2",
  16 0,              R8,             11,             "RL3",
  17 0,              R8,             3,              "RH3",
  18 0,              R8,             12,             "RL4",
  19 0,              R8,             4,              "RH4",
  20 0,              R8,             13,             "RL5",
  21 0,              R8,             5,              "RH5",
  22 0,              R8,             14,             "RL6",
  23 0,              R8,             6,              "RH6",
  24 0,              R8,             15,             "RL7",
  25 0,              R8,             7,              "RH7",
  26 /* Special format for some byte-registers.  Not really available on
  27 ** the z8000 but designed to ease writing a z8000-backend-table.
  28 ** LR[0..7] are equivalent with RL[0..7].
  29 */
  30 0,              R8,             8,              "LR0",
  31 0,              R8,             9,              "LR1",
  32 0,              R8,             10,             "LR2",
  33 0,              R8,             11,             "LR3",
  34 0,              R8,             12,             "LR4",
  35 0,              R8,             13,             "LR5",
  36 0,              R8,             14,             "LR6",
  37 0,              R8,             15,             "LR7",
  38 0,              R16,            0,              "R0",
  39 0,              R16,            1,              "R1",
  40 0,              R16,            2,              "R2",
  41 0,              R16,            3,              "R3",
  42 0,              R16,            4,              "R4",
  43 0,              R16,            5,              "R5",
  44 0,              R16,            6,              "R6",
  45 0,              R16,            7,              "R7",
  46 0,              R16,            8,              "R8",
  47 0,              R16,            9,              "R9",
  48 0,              R16,            10,             "R10",
  49 0,              R16,            11,             "R11",
  50 0,              R16,            12,             "R12",
  51 0,              R16,            13,             "R13",
  52 0,              R16,            14,             "R14",
  53 0,              R16,            15,             "R15",
  54 0,              R32,            0,              "RR0",
  55 0,              R32,            2,              "RR2",
  56 0,              R32,            4,              "RR4",
  57 0,              R32,            6,              "RR6",
  58 0,              R32,            8,              "RR8",
  59 0,              R32,            10,             "RR10",
  60 0,              R32,            12,             "RR12",
  61 0,              R32,            14,             "RR14",
  62 0,              R64,            0,              "RQ0",
  63 0,              R64,            4,              "RQ4",
  64 0,              R64,            8,              "RQ8",
  65 0,              R64,            12,             "RQ12",
  66 0,              CC,             14,             "NZ",
  67 0,              CC,             15,             "NC",
  68 0,              CC,             13,             "PL",
  69 0,              CC,             5,              "MI",
  70 0,              CC,             14,             "NE",
  71 0,              CC,             6,              "EQ",
  72 0,              CC,             4,              "OV",
  73 0,              CC,             12,             "NOV",
  74 0,              CC,             4,              "PE",
  75 0,              CC,             12,             "PO",
  76 0,              CC,             9,              "GE",
  77 0,              CC,             1,              "LT",
  78 0,              CC,             10,             "GT",
  79 0,              CC,             2,              "LE",
  80 0,              CC,             15,             "UGE",
  81 0,              CC,             7,              "ULT",
  82 0,              CC,             11,             "UGT",
  83 0,              CC,             3,              "ULE",
  84 0,              FLAG,           0x80,           "C",
  85 0,              FLAG,           0x40,           "Z",
  86 0,              FLAG,           0x20,           "S",
  87 0,              FLAG,           0x10,           "P",
  88 0,              FLAG,           0x10,           "V",
  89 0,              INTCB,          2,              "VI",
  90 0,              INTCB,          1,              "NVI",
  91 0,              CTLRFLAGS,      1,              "FLAGS",
  92 0,              CTLR,           2,              "FCW",
  93 0,              CTLR,           3,              "REFRESH",
  94 0,              CTLR,           4,              "PSAPSEG",
  95 0,              CTLR,           5,              "PSAPOFF",
  96 0,              CTLR,           6,              "NSPSEG",
  97 0,              CTLR,           7,              "NSPOFF",
  98 0,              CTLR,           5,              "PSAP",
  99 0,              CTLR,           7,              "NSP",
 100
 101         /* TYPE_11a23   */
 102 0,              F1_1F2_3,       0x1F00,         "call",
 103 0,              F1_1F2_3,       0x3900,         "ldps",
 104         /* TYPE_11b23   */
 105 0,              F1_1F2_3,       0x0D08,         "clr",
 106 0,              F1_1F2_3,       0x0C08,         "clrb",
 107 0,              F1_1F2_3,       0x0D00,         "com",
 108 0,              F1_1F2_3,       0x0C00,         "comb",
 109 0,              F1_1F2_3,       0x0D02,         "neg",
 110 0,              F1_1F2_3,       0x0C02,         "negb",
 111 0,              F1_1F2_3,       0x0D04,         "test",
 112 0,              F1_1F2_3,       0x0C04,         "testb",
 113 0,              F1_1F2_3,       0x1C08,         "testl",
 114 0,              F1_1F2_3,       0x0D06,         "tset",
 115 0,              F1_1F2_3,       0x0C06,         "tsetb",
 116
 117 0,              F1_1a,          0xB000,         "dab",
 118 0,              F1_1a,          0xB10A,         "exts",
 119 0,              F1_1a,          0xB100,         "extsb",
 120 0,              F1_1a,          0xB107,         "extsl",
 121
 122 0,              F1_1b,          0xB300,         "rl",
 123 0,              F1_1b,          0xB200,         "rlb",
 124 0,              F1_1b,          0xB308,         "rlc",
 125 0,              F1_1b,          0xB208,         "rlcb",
 126 0,              F1_1b,          0xB304,         "rr",
 127 0,              F1_1b,          0xB204,         "rrb",
 128 0,              F1_1b,          0xB30C,         "rrc",
 129 0,              F1_1b,          0xB20C,         "rrcb",
 130
 131         /* TYPE_12      */
 132 0,              F1_2,           0x2B00,         "dec",
 133 0,              F1_2,           0x2A00,         "decb",
 134 0,              F1_2,           0x2900,         "inc",
 135 0,              F1_2,           0x2800,         "incb",
 136 0,              LDK,            0xBD00,         "ldk",
 137         /* TYPE_1263    */
 138 0,              F1_2F6_3,       0x2700,         "bit",
 139 0,              F1_2F6_3,       0x2600,         "bitb",
 140 0,              F1_2F6_3,       0x2300,         "res",
 141 0,              F1_2F6_3,       0x2200,         "resb",
 142 0,              F1_2F6_3,       0x2500,         "set",
 143 0,              F1_2F6_3,       0x2400,         "setb",
 144
 145         /* TYPE_jp      */
 146 0,              JP,             0x1E00,         "jp",
 147
 148 0,              TCC,            0xAF00,         "tcc",
 149 0,              TCC,            0xAE00,         "tccb",
 150
 151         /* TYPE_21a     */
 152 0,              F2_1,           0x2D00,         "ex",
 153 0,              F2_1,           0x2C00,         "exb",
 154         /* TYPE_21b     */
 155 0,              F2_1,           0x3500,         "adc",
 156 0,              F2_1,           0x3400,         "adcb",
 157 0,              F2_1,           0x3E00,         "rldb",
 158 0,              F2_1,           0x3C00,         "rrdb",
 159 0,              F2_1,           0x3700,         "sbc",
 160 0,              F2_1,           0x3600,         "sbcb",
 161         /* TYPE_2151.
 162         **      Depending on their operands the cp-instructions might
 163         ** have an opcode of 0x201 more then listed below.    This is
 164         ** added at the appropriate place.
 165         **      The difference in opcode between byte-,word- and long-
 166         ** instructions of the F2_1F5_1 group is as follows:
 167         **   If bit 8 is on it is a word instruction;  If it is not a
 168         ** word instruction and bit 12 is on it is a long instruction,
 169         ** else it is a byte instruction.    This information is used
 170         ** when one of the operands is of type IM.
 171         */
 172 0,              F2_1F5_1,       0x0100,         "add",
 173 0,              F2_1F5_1,       0x0000,         "addb",
 174 0,              F2_1F5_1,       0x1600,         "addl",
 175 0,              F2_1F5_1,       0x0700,         "and",
 176 0,              F2_1F5_1,       0x0600,         "andb",
 177 0,              F2_1F5_1,       0x1B00,         "div",
 178 0,              F2_1F5_1,       0x1A00,         "divl",
 179 0,              F2_1F5_1,       0x1900,         "mult",
 180 0,              F2_1F5_1,       0x1800,         "multl",
 181 0,              F2_1F5_1,       0x0500,         "or",
 182 0,              F2_1F5_1,       0x0400,         "orb",
 183 0,              F2_1F5_1,       0x0300,         "sub",
 184 0,              F2_1F5_1,       0x0200,         "subb",
 185 0,              F2_1F5_1,       0x1200,         "subl",
 186 0,              F2_1F5_1,       0x0900,         "xor",
 187 0,              F2_1F5_1,       0x0800,         "xorb",
 188 0,              F2_1F5_1,       0x0B00,         "cp",
 189 0,              F2_1F5_1,       0x0A00,         "cpb",
 190 0,              F2_1F5_1,       0x1000,         "cpl",
 191
 192 0,              LDA,            0,              "lda",
 193         /* TYPE_pop     */
 194 0,              POP,            0x1700,         "pop",
 195 0,              POP,            0x1500,         "popl",
 196         /* TYPE_push    */
 197 0,              PUSH,           0x1300,         "push",
 198 0,              PUSH,           0x1100,         "pushl",
 199
 200         /* TYPE_ld      */
 201 0,              LD,             0x0100,         "ld",
 202 0,              LD,             0,              "ldb",
 203 0,              LDL,            0,              "ldl",
 204
 205 0,              DJNZ,           0xF080,         "djnz",
 206 0,              DJNZ,           0xF000,         "dbjnz",
 207 0,              JR,             0xE000,         "jr",
 208 0,              CALR,           0xD000,         "calr",
 209
 210         /*     Depending on their operands the LDR-instructions might
 211         ** have an opcode of 0x200 more then listed below.    This is
 212         ** or-ed in at the appropriate place.
 213         */
 214 0,              LDR,            0x3100,         "ldr",
 215 0,              LDR,            0x3000,         "ldrb",
 216 0,              LDR,            0x3500,         "ldrl",
 217
 218 0,              LDAR,           0x3400,         "ldar",
 219
 220 0,              F5_1L,          0xB309,         "sla",
 221 0,              F5_1L,          0xB209,         "slab",
 222 0,              F5_1L,          0xB30D,         "slal",
 223 0,              F5_1L,          0xB301,         "sll",
 224 0,              F5_1L,          0xB201,         "sllb",
 225 0,              F5_1L,          0xB305,         "slll",
 226 0,              F5_1R,          0xB309,         "sra",
 227 0,              F5_1R,          0xB209,         "srab",
 228 0,              F5_1R,          0xB30D,         "sral",
 229 0,              F5_1R,          0xB301,         "srl",
 230 0,              F5_1R,          0xB201,         "srlb",
 231 0,              F5_1R,          0xB305,         "srll",
 232
 233         /*    Depending on its operands the LDM-instruction might have
 234         ** an opcode of 8 more then listed below.  This is added at the
 235         ** appropriate place.
 236         ** TYPE_ldm
 237         */
 238 0,              LDM,            0x1C01,         "ldm",
 239
 240         /*   For the F6.4 instructions below the yylval-column contains
 241         ** the opcode for the instruction. However the third hexa-digit
 242         ** should be 0;   But this is the opcode which must be put into
 243         ** the second word of the instruction!
 244         */
 245 0,              F6_4,           0x3B88,         "ind",
 246 0,              F6_4,           0x3A88,         "indb",
 247 0,              F6_4,           0x3B08,         "indr",
 248 0,              F6_4,           0x3A08,         "indrb",
 249 0,              F6_4,           0x3B80,         "ini",
 250 0,              F6_4,           0x3A80,         "inib",
 251 0,              F6_4,           0x3B00,         "inir",
 252 0,              F6_4,           0x3A00,         "inirb",
 253 0,              F6_4,           0xBB89,         "ldd",
 254 0,              F6_4,           0xBA89,         "lddb",
 255 0,              F6_4,           0xBB09,         "lddr",
 256 0,              F6_4,           0xBA09,         "lddrb",
 257 0,              F6_4,           0xBB81,         "ldi",
 258 0,              F6_4,           0xBA81,         "ldib",
 259 0,              F6_4,           0xBB01,         "ldir",
 260 0,              F6_4,           0xBA01,         "ldirb",
 261 0,              F6_4,           0x3B0A,         "otdr",
 262 0,              F6_4,           0x3A0A,         "otdrb",
 263 0,              F6_4,           0x3B02,         "otir",
 264 0,              F6_4,           0x3A02,         "otirb",
 265 0,              F6_4,           0x3B8A,         "outd",
 266 0,              F6_4,           0x3A8A,         "outdb",
 267 0,              F6_4,           0x3B82,         "outi",
 268 0,              F6_4,           0x3A82,         "outib",
 269 0,              F6_4,           0x3B89,         "sind",
 270 0,              F6_4,           0x3A89,         "sindb",
 271 0,              F6_4,           0x3B09,         "sindr",
 272 0,              F6_4,           0x3A09,         "sindrb",
 273 0,              F6_4,           0x3B81,         "sini",
 274 0,              F6_4,           0x3A81,         "sinib",
 275 0,              F6_4,           0x3B01,         "sinir",
 276 0,              F6_4,           0x3A01,         "sinirb",
 277 0,              F6_4,           0x3B0B,         "sotdr",
 278 0,              F6_4,           0x3A0B,         "sotdrb",
 279 0,              F6_4,           0x3B03,         "sotir",
 280 0,              F6_4,           0x3A03,         "sotirb",
 281 0,              F6_4,           0x3B8B,         "soutd",
 282 0,              F6_4,           0x3A8B,         "soutdb",
 283 0,              F6_4,           0x3B83,         "souti",
 284 0,              F6_4,           0x3A83,         "soutib",
 285 0,              F6_4,           0xB808,         "trdb",
 286 0,              F6_4,           0xB80C,         "trdrb",
 287 0,              F6_4,           0xB800,         "trib",
 288 0,              F6_4,           0xB804,         "trirb",
 289 0,              F6_4,           0xB80A,         "trtdb",
 290 0,              F6_4,           0xB8EE,         "trtdrb",
 291 0,              F6_4,           0xB802,         "trtib",
 292 0,              F6_4,           0xB8E6,         "trtirb",
 293
 294         /*   From the F6.5 instructions below the last eight ('string'-
 295         ** instructions) want an 'ir' as operand; The others want a 'r'.
 296         ** In the opcode for the string-instructions bit 1 is on, which
 297         ** indicates the difference.
 298         */
 299 0,              F6_5,           0xBB08,         "cpd",
 300 0,              F6_5,           0xBA08,         "cpdb",
 301 0,              F6_5,           0xBB0C,         "cpdr",
 302 0,              F6_5,           0xBA0C,         "cpdrb",
 303 0,              F6_5,           0xBB00,         "cpi",
 304 0,              F6_5,           0xBA00,         "cpib",
 305 0,              F6_5,           0xBB04,         "cpir",
 306 0,              F6_5,           0xBA04,         "cpirb",
 307 0,              F6_5,           0xBB0A,         "cpsd",
 308 0,              F6_5,           0xBA0A,         "cpsdb",
 309 0,              F6_5,           0xBB0E,         "cpsdr",
 310 0,              F6_5,           0xBA0E,         "cpsdrb",
 311 0,              F6_5,           0xBB02,         "cpsi",
 312 0,              F6_5,           0xBA02,         "cpsib",
 313 0,              F6_5,           0xBB06,         "cpsir",
 314 0,              F6_5,           0xBA06,         "cpsirb",
 315
 316 0,              F6_6,           0xB30B,         "sda",
 317 0,              F6_6,           0xB20B,         "sdab",
 318 0,              F6_6,           0xB30F,         "sdal",
 319 0,              F6_6,           0xB303,         "sdl",
 320 0,              F6_6,           0xB203,         "sdlb",
 321 0,              F6_6,           0xB307,         "sdll",
 322
 323         /* The instructions in\b and out\b have two different opcodes
 324         ** depending on their operands (...).   Therefore the opcodes
 325         ** below are not complete.    The rest is or-ed in at the ap-
 326         ** propriate place!
 327         **      rest    |  r and da     r and ir
 328         **      ---------------------------------
 329         **      in\b    |   0xA04       0xC00
 330         **      out\b   |   0xA06       OxE00
 331         ** Furthermore the 'special'-instructions don't allow an 'ir'
 332         ** as operand.   In their opcode bit 0 is on, which indicates
 333         ** the difference with the other instructions of this group.
 334         */
 335 0,              IN,             0x3100,         "in",
 336 0,              IN,             0x3000,         "inb",
 337 0,              IN,             0x3B05,         "sin",
 338 0,              IN,             0x3A05,         "sinb",
 339 0,              OUT,            0x3100,         "out",
 340 0,              OUT,            0x3000,         "outb",
 341 0,              OUT,            0x3B07,         "sout",
 342 0,              OUT,            0x3A07,         "soutb",
 343
 344         /*   Depending on their operands the LDCTL-instructions might
 345         ** have an opcode of 8 more then listed below.  This is or-ed
 346         ** in at the appropriate place.
 347         */
 348 0,              LDCTL,          0x7D00,         "ldctl",
 349 0,              LDCTLB,         0x8C00,         "ldctlb",
 350 0,              MREQ,           0x7B0D,         "mreq",
 351
 352 0,              F9_1,           0x8D05,         "comflg",
 353 0,              F9_1,           0x8D03,         "resflg",
 354 0,              F9_1,           0x8D01,         "setflg",
 355
 356 0,              F9_2,           0x7C00,         "di",
 357 0,              F9_2,           0x7C04,         "ei",
 358
 359 0,              F9_3,           0x7A00,         "halt",
 360 0,              F9_3,           0x7B00,         "iret",
 361 0,              F9_3,           0x7B0A,         "mbit",
 362 0,              F9_3,           0x7B09,         "mres",
 363 0,              F9_3,           0x7B08,         "mset",
 364 0,              F9_3,           0x8D07,         "nop",
 365
 366         /* Rest of the opcode-0x200 is or-ed in at the appropriate place
 367         */
 368 0,              RET,            0x9E00,         "ret",
 369 0,              SC,             0x7F00,         "sc",