2 * (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands.
3 * See the copyright notice in the ACK home directory, in the file "Copyright".
5 #define RCSID3 "$Id: mach3.c,v 1.5 1994/06/24 13:41:13 ceriel Exp $"
32 /* For immediate mode, we need the size as specified by the instruction.
33 Ordinary operands are therefore encoded as _w, _b, and _l to indicate
35 For now, immediate floating point and immediate values of size > 4 are not
36 implemented. _u is used for this.
37 The valu_t field is used for the opcode. Most opcodes take one byte.
38 The ones that don't take two bytes.
41 /* integer arithmetic and logical instructions */
43 0, OP2_w_w, 0x58, "adawi",
44 0, OP2_b_b, 0x80, "addb2",
45 0, OP3_b_b_b, 0x81, "addb3",
46 0, OP2_w_w, 0xa0, "addw2",
47 0, OP3_w_w_w, 0xa1, "addw3",
48 0, OP2_l_l, 0xc0, "addl2",
49 0, OP3_l_l_l, 0xc1, "addl3",
50 0, OP2_l_l, 0xd8, "adwc",
51 0, OP3_b_l_l, 0x78, "ashl",
52 0, OP3_b_u_u, 0x79, "ashq",
53 0, OP2_b_b, 0x8a, "bicb2",
54 0, OP3_b_b_b, 0x8b, "bicb3",
55 0, OP2_w_w, 0xaa, "bicw2",
56 0, OP3_w_w_w, 0xab, "bicw3",
57 0, OP2_l_l, 0xca, "bicl2",
58 0, OP3_l_l_l, 0xcb, "bicl3",
59 0, OP2_b_b, 0x88, "bisb2",
60 0, OP3_b_b_b, 0x89, "bisb3",
61 0, OP2_w_w, 0xa8, "bisw2",
62 0, OP3_w_w_w, 0xa9, "bisw3",
63 0, OP2_l_l, 0xc8, "bisl2",
64 0, OP3_l_l_l, 0xc9, "bisl3",
65 0, OP2_b_b, 0x93, "bitb",
66 0, OP2_w_w, 0xb3, "bitw",
67 0, OP2_l_l, 0xd3, "bitl",
68 0, OP1_X, 0x94|(1L<<16), "clrb",
69 0, OP1_X, 0xb4|(2L<<16), "clrw",
70 0, OP1_X, 0xd4|(4L<<16), "clrl",
71 0, OP1_u, 0x7c, "clrq",
72 0, OP1_u, 0x7cfd, "clro",
73 0, OP2_b_b, 0x91, "cmpb",
74 0, OP2_w_w, 0xb1, "cmpw",
75 0, OP2_l_l, 0xd1, "cmpl",
76 0, OP2_b_w, 0x99, "cvtbw",
77 0, OP2_b_l, 0x98, "cvtbl",
78 0, OP2_w_b, 0x33, "cvtwb",
79 0, OP2_w_l, 0x32, "cvtwl",
80 0, OP2_l_b, 0xf6, "cvtlb",
81 0, OP2_l_w, 0xf7, "cvtlw",
82 0, OP1_X, 0x97|(1L<<16), "decb",
83 0, OP1_X, 0xb7|(2L<<16), "decw",
84 0, OP1_X, 0xd7|(4L<<16), "decl",
85 0, OP2_b_b, 0x86, "divb2",
86 0, OP3_b_b_b, 0x87, "divb3",
87 0, OP2_w_w, 0xa6, "divw2",
88 0, OP3_w_w_w, 0xa7, "divw3",
89 0, OP2_l_l, 0xc6, "divl2",
90 0, OP3_l_l_l, 0xc7, "divl3",
91 0, OP4_l_u_l_l, 0x7b, "ediv",
92 0, OP4_l_l_l_u, 0x7a, "emul",
93 0, OP1_X, 0x96|(1L<<16), "incb",
94 0, OP1_X, 0xb6|(2L<<16), "incw",
95 0, OP1_X, 0xd6|(4L<<16), "incl",
96 0, OP2_b_b, 0x92, "mcomb",
97 0, OP2_w_w, 0xb2, "mcomw",
98 0, OP2_l_l, 0xd2, "mcoml",
99 0, OP2_b_b, 0x8e, "mnegb",
100 0, OP2_w_w, 0xae, "mnegw",
101 0, OP2_l_l, 0xce, "mnegl",
102 0, OP2_b_b, 0x90, "movb",
103 0, OP2_w_w, 0xb0, "movw",
104 0, OP2_l_l, 0xd0, "movl",
105 0, OP2_u_u, 0x7d, "movq",
106 0, OP2_u_u, 0x7dfd, "movo",
107 0, OP2_b_w, 0x9b, "movzbw",
108 0, OP2_b_l, 0x9a, "movzbl",
109 0, OP2_w_l, 0x3c, "movzwl",
110 0, OP2_b_b, 0x84, "mulb2",
111 0, OP3_b_b_b, 0x85, "mulb3",
112 0, OP2_w_w, 0xa4, "mulw2",
113 0, OP3_w_w_w, 0xa5, "mulw3",
114 0, OP2_l_l, 0xc4, "mull2",
115 0, OP3_l_l_l, 0xc5, "mull3",
116 0, OP1_X, 0xdd|(4L<<16), "pushl",
117 0, OP3_b_l_l, 0x9c, "rotl",
118 0, OP2_l_l, 0xd9, "sbwc",
119 0, OP2_b_b, 0x82, "subb2",
120 0, OP3_b_b_b, 0x83, "subb3",
121 0, OP2_w_w, 0xa2, "subw2",
122 0, OP3_w_w_w, 0xa3, "subw3",
123 0, OP2_l_l, 0xc2, "subl2",
124 0, OP3_l_l_l, 0xc3, "subl3",
125 0, OP1_X, 0x95|(1L<<16), "tstb",
126 0, OP1_X, 0xb5|(2L<<16), "tstw",
127 0, OP1_X, 0xd5|(4L<<16), "tstl",
128 0, OP2_b_b, 0x8c, "xorb2",
129 0, OP3_b_b_b, 0x8d, "xorb3",
130 0, OP2_w_w, 0xac, "xorw2",
131 0, OP3_w_w_w, 0xad, "xorw3",
132 0, OP2_l_l, 0xcc, "xorl2",
133 0, OP3_l_l_l, 0xcd, "xorl3",
135 /* Address instructions */
137 0, OP2_A_l, 0x9e, "movab",
138 0, OP2_A_l, 0x3e, "movaw",
139 0, OP2_A_l, 0xde, "moval",
140 0, OP2_A_l, 0xde, "movaf",
141 0, OP2_A_l, 0x7e, "movaq",
142 0, OP2_A_l, 0x7e, "movad",
143 0, OP2_A_l, 0x7e, "movag",
144 0, OP2_A_l, 0x7efd, "movah",
145 0, OP2_A_l, 0x7efd, "movao",
146 0, OP1_A, 0x9f, "pushab",
147 0, OP1_A, 0x3f, "pushaw",
148 0, OP1_A, 0xdf, "pushal",
149 0, OP1_A, 0xdf, "pushaf",
150 0, OP1_A, 0x7f, "pushaq",
151 0, OP1_A, 0x7f, "pushad",
152 0, OP1_A, 0x7f, "pushag",
153 0, OP1_A, 0x7ffd, "pushah",
154 0, OP1_A, 0x7ffd, "pushao",
156 /* Variable length bit-field instructions */
158 0, OP4_l_b_V_l, 0xec, "cmpv",
159 0, OP4_l_b_V_l, 0xed, "cmpzv",
160 0, OP4_l_b_V_l, 0xee, "extv",
161 0, OP4_l_b_V_l, 0xef, "extzv",
162 0, OP4_l_b_V_l, 0xeb, "ffc",
163 0, OP4_l_b_V_l, 0xea, "ffs",
164 0, OP4_l_l_b_V, 0xf0, "insv",
166 /* Control instructions */
168 0, OP4_b_b_b_Bw, 0x9d, "acbb",
169 0, OP4_w_w_w_Bw, 0x3d, "acbw",
170 0, OP4_l_l_l_Bw, 0xf1, "acbl",
171 0, OP4_u_u_u_Bw, 0x4f, "acbf",
172 0, OP4_u_u_u_Bw, 0x6f, "acbd",
173 0, OP4_u_u_u_Bw, 0x4ffd, "acbg",
174 0, OP4_u_u_u_Bw, 0x6ffd, "acbh",
175 0, OP3_l_l_Bb, 0xf3, "aobleq",
176 0, OP3_l_l_Bb, 0xf2, "aoblss",
177 0, OP1_BX, 0x14|(1L<<16), "bgtr",
178 0, OP1_BX, 0x15|(1L<<16), "bleq",
179 0, OP1_BX, 0x12|(1L<<16), "bneq",
180 0, OP1_BX, 0x12|(1L<<16), "bnequ",
181 0, OP1_BX, 0x13|(1L<<16), "beql",
182 0, OP1_BX, 0x13|(1L<<16), "beqlu",
183 0, OP1_BX, 0x18|(1L<<16), "bgeq",
184 0, OP1_BX, 0x19|(1L<<16), "blss",
185 0, OP1_BX, 0x1a|(1L<<16), "bgtru",
186 0, OP1_BX, 0x1b|(1L<<16), "blequ",
187 0, OP1_BX, 0x1c|(1L<<16), "bvc",
188 0, OP1_BX, 0x1d|(1L<<16), "bvs",
189 0, OP1_BX, 0x1e|(1L<<16), "bgequ",
190 0, OP1_BX, 0x1e|(1L<<16), "bcc",
191 0, OP1_BX, 0x1f|(1L<<16), "blssu",
192 0, OP1_BX, 0x1f|(1L<<16), "bcs",
193 0, OP3_l_V_Bb, 0xe0, "bbs",
194 0, OP3_l_V_Bb, 0xe1, "bbc",
195 0, OP3_l_V_Bb, 0xe2, "bbss",
196 0, OP3_l_V_Bb, 0xe3, "bbcs",
197 0, OP3_l_V_Bb, 0xe4, "bbsc",
198 0, OP3_l_V_Bb, 0xe5, "bbcc",
199 0, OP3_l_V_Bb, 0xe6, "bbssi",
200 0, OP3_l_V_Bb, 0xe7, "bbcci",
201 0, OP2_l_Bb, 0xe8, "blbs",
202 0, OP2_l_Bb, 0xe9, "blbc",
203 0, OP1_Be, 0x14, "jgtr",
204 0, OP1_Be, 0x15, "jleq",
205 0, OP1_Be, 0x12, "jneq",
206 0, OP1_Be, 0x12, "jnequ",
207 0, OP1_Be, 0x13, "jeql",
208 0, OP1_Be, 0x13, "jeqlu",
209 0, OP1_Be, 0x18, "jgeq",
210 0, OP1_Be, 0x19, "jlss",
211 0, OP1_Be, 0x1a, "jgtru",
212 0, OP1_Be, 0x1b, "jlequ",
213 0, OP1_Be, 0x1c, "jvc",
214 0, OP1_Be, 0x1d, "jvs",
215 0, OP1_Be, 0x1e, "jgequ",
216 0, OP1_Be, 0x1e, "jcc",
217 0, OP1_Be, 0x1f, "jlssu",
218 0, OP1_Be, 0x1f, "jcs",
219 0, OP2_l_Be, 0xe8, "jlbs",
220 0, OP2_l_Be, 0xe9, "jlbc",
221 0, OP3_l_V_Be, 0xe0, "jbs",
222 0, OP3_l_V_Be, 0xe1, "jbc",
223 0, OP3_l_V_Be, 0xe2, "jbss",
224 0, OP3_l_V_Be, 0xe3, "jbcs",
225 0, OP3_l_V_Be, 0xe4, "jbsc",
226 0, OP3_l_V_Be, 0xe5, "jbcc",
227 0, OP3_l_V_Be, 0xe6, "jbssi",
228 0, OP3_l_V_Be, 0xe7, "jbcci",
229 0, OP1_Bx, 0x11, "br",
230 0, OP1_BX, 0x11|(1L<<16), "brb",
231 0, OP1_BX, 0x31|(2L<<16), "brw",
232 0, OP1_Be, 0x11, "jbr",
233 0, OP1_Bx, 0x10, "bsb",
234 0, OP1_BX, 0x10|(1L<<16), "bsbb",
235 0, OP1_BX, 0x30|(2L<<16), "bsbw",
236 0, CASE_X_X_X, 0x8f|(1L<<16), "caseb",
237 0, CASE_X_X_X, 0xaf|(2L<<16), "casew",
238 0, CASE_X_X_X, 0xcf|(4L<<16), "casel",
239 0, OP1_A, 0x17, "jmp",
240 0, OP1_A, 0x16, "jsb",
242 0, OP2_l_Bb, 0xf4, "sobgeq",
243 0, OP2_l_Bb, 0xf5, "sobgtr",
245 /* Procedure call instructions */
247 0, OP2_A_A, 0xfa, "callg",
248 0, OP2_l_A, 0xfb, "calls",
251 /* Miscellaneous instructions */
253 0, OP1_X, 0xb9|(2L<<16), "bicpsw",
254 0, OP1_X, 0xb8|(2L<<16), "bispsw",
256 0, OP0, 0x00, "halt",
257 0, OP6_l_l_l_l_l_l,0x0a, "index",
258 0, OP1_X, 0xdc|(4L<<16), "movpsl",
260 0, OP1_X, 0xba|(2L<<16), "popr",
261 0, OP1_X, 0xbb|(2L<<16), "pushr",
264 /* Queue instructions */
266 0, OP2_A_A, 0x5c, "insqhi",
267 0, OP2_A_A, 0x5d, "insqti",
268 0, OP2_A_A, 0x0e, "insque",
269 0, OP2_A_l, 0x5e, "remqhi",
270 0, OP2_A_l, 0x5f, "remqti",
271 0, OP2_A_l, 0x0f, "remque",
273 /* Floating point instructions */
275 0, OP2_u_u, 0x40, "addf2",
276 0, OP3_u_u_u, 0x41, "addf3",
277 0, OP2_u_u, 0x60, "addd2",
278 0, OP3_u_u_u, 0x61, "addd3",
279 0, OP2_u_u, 0x40fd, "addg2",
280 0, OP3_u_u_u, 0x41fd, "addg3",
281 0, OP2_u_u, 0x60fd, "addh2",
282 0, OP3_u_u_u, 0x61fd, "addh3",
283 0, OP1_u, 0xd4, "clrf",
284 0, OP1_u, 0x7c, "clrd",
285 0, OP1_u, 0x7c, "clrg",
286 0, OP1_u, 0x7cfd, "clrh",
287 0, OP2_u_u, 0x51, "cmpf",
288 0, OP2_u_u, 0x71, "cmpd",
289 0, OP2_u_u, 0x51fd, "cmpg",
290 0, OP2_u_u, 0x71fd, "cmph",
291 0, OP2_b_u, 0x4c, "cvtbf",
292 0, OP2_b_u, 0x6c, "cvtbd",
293 0, OP2_b_u, 0x4cfd, "cvtbg",
294 0, OP2_b_u, 0x6cfd, "cvtbh",
295 0, OP2_w_u, 0x4d, "cvtwf",
296 0, OP2_w_u, 0x6d, "cvtwd",
297 0, OP2_w_u, 0x4dfd, "cvtwg",
298 0, OP2_w_u, 0x6dfd, "cvtwh",
299 0, OP2_l_u, 0x4e, "cvtlf",
300 0, OP2_l_u, 0x6e, "cvtld",
301 0, OP2_l_u, 0x4efd, "cvtlg",
302 0, OP2_l_u, 0x6efd, "cvtlh",
303 0, OP2_u_b, 0x48, "cvtfb",
304 0, OP2_u_b, 0x68, "cvtdb",
305 0, OP2_u_b, 0x48fd, "cvtgb",
306 0, OP2_u_b, 0x68fd, "cvthb",
307 0, OP2_u_w, 0x49, "cvtfw",
308 0, OP2_u_w, 0x69, "cvtdw",
309 0, OP2_u_w, 0x49fd, "cvtgw",
310 0, OP2_u_w, 0x69fd, "cvthw",
311 0, OP2_u_l, 0x4a, "cvtfl",
312 0, OP2_u_l, 0x6a, "cvtdl",
313 0, OP2_u_l, 0x4afd, "cvtgl",
314 0, OP2_u_l, 0x6afd, "cvthl",
315 0, OP2_u_l, 0x4b, "cvtrfl",
316 0, OP2_u_l, 0x6b, "cvtrdl",
317 0, OP2_u_l, 0x4bfd, "cvtrgl",
318 0, OP2_u_l, 0x6bfd, "cvtrhl",
319 0, OP2_u_u, 0x56, "cvtfd",
320 0, OP2_u_u, 0x99fd, "cvtfg",
321 0, OP2_u_u, 0x98fd, "cvtfh",
322 0, OP2_u_u, 0x76, "cvtdf",
323 0, OP2_u_u, 0x32fd, "cvtdh",
324 0, OP2_u_u, 0x33fd, "cvtgf",
325 0, OP2_u_u, 0x56fd, "cvtgh",
326 0, OP2_u_u, 0xf6fd, "cvthf",
327 0, OP2_u_u, 0xf7fd, "cvthd",
328 0, OP2_u_u, 0x76fd, "cvthg",
329 0, OP2_u_u, 0x46, "divf2",
330 0, OP3_u_u_u, 0x47, "divf3",
331 0, OP2_u_u, 0x66, "divd2",
332 0, OP3_u_u_u, 0x67, "divd3",
333 0, OP2_u_u, 0x46fd, "divg2",
334 0, OP3_u_u_u, 0x47fd, "divg3",
335 0, OP2_u_u, 0x66fd, "divh2",
336 0, OP3_u_u_u, 0x67fd, "divh3",
337 0, OP5_u_b_u_l_u, 0x54, "emodf",
338 0, OP5_u_b_u_l_u, 0x74, "emodd",
339 0, OP5_u_w_u_l_u, 0x54fd, "emodg",
340 0, OP5_u_w_u_l_u, 0x74fd, "emodh",
341 0, OP2_u_u, 0x52, "mnegf",
342 0, OP2_u_u, 0x72, "mnegd",
343 0, OP2_u_u, 0x52fd, "mnegg",
344 0, OP2_u_u, 0x72fd, "mnegh",
345 0, OP2_u_u, 0x50, "movf",
346 0, OP2_u_u, 0x70, "movd",
347 0, OP2_u_u, 0x50fd, "movg",
348 0, OP2_u_u, 0x70fd, "movh",
349 0, OP2_u_u, 0x44, "mulf2",
350 0, OP3_u_u_u, 0x45, "mulf3",
351 0, OP2_u_u, 0x64, "muld2",
352 0, OP3_u_u_u, 0x65, "muld3",
353 0, OP2_u_u, 0x44fd, "mulg2",
354 0, OP3_u_u_u, 0x45fd, "mulg3",
355 0, OP2_u_u, 0x64fd, "mulh2",
356 0, OP3_u_u_u, 0x65fd, "mulh3",
357 0, OP3_u_w_A, 0x55, "polyf",
358 0, OP3_u_w_A, 0x75, "polyd",
359 0, OP3_u_w_A, 0x55fd, "polyg",
360 0, OP3_u_w_A, 0x75fd, "polyh",
361 0, OP2_u_u, 0x42, "subf2",
362 0, OP3_u_u_u, 0x43, "subf3",
363 0, OP2_u_u, 0x62, "subd2",
364 0, OP3_u_u_u, 0x63, "subd3",
365 0, OP2_u_u, 0x42fd, "subg2",
366 0, OP3_u_u_u, 0x43fd, "subg3",
367 0, OP2_u_u, 0x62fd, "subh2",
368 0, OP3_u_u_u, 0x63fd, "subh3",
369 0, OP1_u, 0x53, "tstf",
370 0, OP1_u, 0x73, "tstd",
371 0, OP1_u, 0x53fd, "tstg",
372 0, OP1_u, 0x73fd, "tsth",
374 /* Character string instructions */
376 0, OP3_w_A_A, 0x29, "cmpc3",
377 0, OP5_w_A_b_w_A, 0x2d, "cmpc5",
378 0, OP3_b_w_A, 0x3a, "locc",
379 0, OP4_w_A_w_A, 0x39, "matchc",
380 0, OP3_w_A_A, 0x28, "movc3",
381 0, OP5_w_A_b_w_A, 0x2c, "movc5",
382 0, OP6_w_A_b_A_w_A,0x2e, "movtc",
383 0, OP6_w_A_b_A_w_A,0x2f, "movtuc",
384 0, OP4_w_A_A_b, 0x2a, "scanc",
385 0, OP3_b_w_A, 0x3b, "skpc",
386 0, OP4_w_A_A_b, 0x2b, "spanc",
388 /* Cyclic redundancy check instructions */
390 0, OP4_A_l_w_A, 0x0b, "crc",
392 /* Decimal string instructions */
394 0, OP4_w_A_w_A, 0x20, "addp4",
395 0, OP6_w_A_w_A_w_A,0x21, "addp6",
396 0, OP6_b_w_A_b_w_A,0xf8, "ashp",
397 0, OP3_w_A_A, 0x35, "cmpp3",
398 0, OP4_w_A_w_A, 0x37, "cmpp4",
399 0, OP3_l_w_A, 0xf9, "cvtlp",
400 0, OP3_w_A_l, 0x36, "cvtpl",
401 0, OP4_w_A_w_A, 0x08, "cvtps",
402 0, OP5_w_A_A_w_A, 0x24, "cvtpt",
403 0, OP4_w_A_w_A, 0x09, "cvtsp",
404 0, OP5_w_A_A_w_A, 0x26, "cvttp",
405 0, OP6_w_A_w_A_w_A,0x27, "divp",
406 0, OP3_w_A_A, 0x34, "movp",
407 0, OP6_w_A_w_A_w_A,0x25, "mulp",
408 0, OP4_w_A_w_A, 0x22, "subp4",
409 0, OP6_w_A_w_A_w_A,0x23, "subp6",
411 /* Edit instruction */
413 0, OP4_w_A_A_A, 0x38, "editpc",
415 /* Other VAX-11 instructions */
417 /* BSD 4.3 adb has a different opinion of the bugw and bugl instructions:
418 it thinks that an addressing mode byte is required. However, according
419 to the VAX-11 Architecture Reference Manual, Revision 6.1, 1982, the
420 access type is b, which means that the operand is a branch displacement.
422 0, OP1_BX, 0xfeff|(2L<<16),"bugw",
423 0, OP1_BX, 0xfdff|(4L<<16),"bugl",
425 0, OP3_b_w_A, 0x0c, "prober",
426 0, OP3_b_w_A, 0x0d, "probew",
429 0, OP1_X, 0xbc|(2L<<16), "chmk",
430 0, OP1_X, 0xbd|(2L<<16), "chme",
431 0, OP1_X, 0xbe|(2L<<16), "chms",
432 0, OP1_X, 0xbf|(2L<<16), "chmu",
434 0, OP0, 0x06, "ldpctx",
435 0, OP0, 0x07, "svpctx",
436 0, OP2_l_l, 0xda, "mtpr",
437 0, OP2_l_l, 0xdb, "mfpr",