2 * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
3 * See the copyright notice in the ACK home directory, in the file "Copyright".
6 rscid = "$Id: table,v 1.79 1998/09/03 12:51:38 ceriel Exp $"
8 /********************************
10 * 68000, 68010 and 68020 *
13 ********************************/
17 #if TBL68881 && ! TBL68020
18 Something very wrong here!
20 #if WORD_SIZE!=2 && WORD_SIZE!=4
21 Something very wrong here!
25 #define SYNTAX_68020 1
28 /* #define FANCY_MODES 1
29 /* On the M68020, there are some real fancy addressing modes.
30 Their use makes the code a bit shorter, but also much slower.
31 The FANCY_MODES #define enables the use of these addressing
35 #define small(x) ((x)>=1 && (x)<=8)
36 #define directadd(x) (small(x) || (x)>128)
37 #define directsub(x) (directadd(0-x))
38 #define nicesize(x) ((x)==1||(x)==2||(x)==4||(x)==8)
39 #define low8(x) ((x) & 0377)
40 #define low16(x) ((x) & 0177777)
41 #define in_1(x) sfit(x,8)
42 #define in_2(x) sfit(x,16)
56 D_REG /* data registers */
57 A_REG(4) /* address registers */
58 DD_REG /* allocatable D_REG, may not be a register variable */
59 AA_REG(4) /* allocatable A_REG, may not be a register variable */
60 RD_REG /* data register, register var */
61 RA_REG(4) /* address register, register var */
63 D_REG4(4) /* data register, 4 bytes */
64 DD_REG4(4) /* allocatable D_REG, 4 bytes */
67 #define DD_REG4 DD_REG
70 FS_REG(4) /* floating point register */
71 FD_REG(8) /* double floating point register */
78 d0, d1, d2 :D_REG, DD_REG.
79 d3, d4, d5, d6, d7 :D_REG, RD_REG regvar.
81 dl0("d0")=d0, dl1("d1")=d1, dl2("d2")=d2 :D_REG4, DD_REG4.
87 a0, a1 :A_REG, AA_REG.
88 a2, a3, a4, a5 :A_REG, RA_REG regvar(reg_pointer).
89 lb ("a6"), sp :A_REG. /* localbase and stack pointer */
91 F0 ("fp0"), F1 ("fp1"), F2 ("fp2"), F3 ("fp3"), F4 ("fp4"), F5 ("fp5"),
92 F6 ("fp6"), F7 ("fp7") :FS_REG.
93 fp0=F0,fp1=F1,fp2=F2,fp3=F3,fp4=F4,fp5=F5,fp6=F6,fp7=F7
101 /* Not all addressing modes available on the MC68020 are used in this
102 * table. E.g (Dn), data register indirect is not used. Compared to
103 * (An), address register indirect, (Dn) requires two more bytes and
104 * several more clock cycles. Using (Dn) is even more expensive in
105 * time than first moving Dn to an address register An, and then using
106 * (An). For this kind of reasons several addressing modes are
107 * not used in this table.
109 * Cost in bytes may sometimes be incorrect. Several effective addresses
110 * use displacements that can occupy either 2 or 4 bytes. These are not
111 * considered different TOKENS in this table.
113 * Data registers are the only registers used as index registers in this
114 * table; address registers are only used to hold addresses.
116 * For the m68k2 and m68k4 table: the MC68000 and MC68010 have two
117 * modes that use displacements (offsets) of limited size:
118 * - offset(A_REG, Index_reg), where offset is only 8 bits, and
119 * - offset(A_REG), where offset can only be 16 bits.
120 * To make sure that no output is given with offsets too large, two
121 * extra tokens are declared: t_regAregXcon and t_regAcon. These are
122 * used as addresses to these modes. Whenever the displacements become
123 * too large, they are transformed into different tokens.
125 * Sometimes some TOKENS are used with displacements (offsets) of 0.
126 * It would have been possible to provide separate TOKENS for these, in
127 * case the assembler doesn't handle zero offsets optimally. This
128 * however would mean a very large amount of extra TOKENS and SETS for
129 * a very small profit in code bytes, so we won't do that.
131 * To prevent the TOKENS list from getting too unreadable, #ifdefs are
132 * used to form three parts:
133 * (i) the common part;
134 * (ii) the m68k2 and m68k4 part;
135 * (iii) the m68020 part;
139 zero_const = {INT num;} WORD_SIZE cost(0,0) "#" num .
140 small_const = {INT num;} WORD_SIZE cost(0,0) "#" num .
141 bconst = {INT num;} WORD_SIZE cost(0,0) "#" num .
142 const = {INT num;} WORD_SIZE cost(4,4) "#" num .
144 /* ??? "string+const */
145 zero_const4 = {INT num;} 4 cost(0,0) "#" num .
146 small_const4 = {INT num;} 4 cost(0,0) "#" num .
147 bconst4 = {INT num;} 4 cost(0,0) "#" num .
148 const4 = {ADDR num;} 4 cost(4,4) "#" num .
150 indirect4 = {A_REG reg;} 4 cost(0,4) "(" reg ")" .
151 post_inc4 = {A_REG reg;} 4 cost(0,4) "(" reg ")+" .
152 pre_dec4 = {A_REG reg;} 4 cost(0,5) "-(" reg ")" .
153 dreg4 = {D_REG4 reg;} 4 cost(0,0) reg .
154 areg = {A_REG reg;} 4 cost(0,0) reg .
155 dreg2 = {D_REG reg;} WORD_SIZE cost(0,0) reg .
156 indirect2 = {A_REG reg;} WORD_SIZE cost(0,4) "(" reg ")" .
157 post_inc2 = {A_REG reg;} WORD_SIZE cost(0,4) "(" reg ")+" .
158 pre_dec2 = {A_REG reg;} WORD_SIZE cost(0,5) "-(" reg ")" .
159 dreg1 = {D_REG reg;} WORD_SIZE cost(0,0) reg .
160 indirect1 = {A_REG reg;} WORD_SIZE cost(0,4) "(" reg ")" .
161 post_inc1 = {A_REG reg;} WORD_SIZE cost(0,4) "(" reg ")+" .
162 pre_dec1 = {A_REG reg;} WORD_SIZE cost(0,5) "-(" reg ")" .
164 ext_addr = {ADDR bd;} 4 cost(4,5) "#" bd .
165 llabel = {ADDR bd;} 4 cost(2,0) bd .
166 slabel = {ADDR bd;} 4 cost(0,0) bd .
169 extend1 = {D_REG reg;} WORD_SIZE cost(0,0) reg .
171 extend1_4 = {D_REG4 reg;} 4 cost(0,0) reg .
173 #define extend1_4 extend1
175 extend2 = {D_REG4 reg;} 4 cost(0,0) reg .
178 /* Part (ii) in m68k2/4 syntax */
179 absolute4 = {ADDR bd;} 4 cost(4,8) bd .
180 offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) bd "(" reg ")" .
181 index_off4 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,7)
182 bd "(" reg "," xreg ".l)" .
183 absolute2 = {ADDR bd;} WORD_SIZE cost(4,6) bd .
184 offsetted2 = {A_REG reg; INT bd;} WORD_SIZE cost(2,4) bd "(" reg ")" .
185 index_off2 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} WORD_SIZE cost(2,5)
186 bd "(" reg "," xreg ".l)" .
187 absolute1 = {ADDR bd;} WORD_SIZE cost(4,6) bd .
188 offsetted1 = {A_REG reg; INT bd;} WORD_SIZE cost(2,4) bd "(" reg ")" .
189 index_off1 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} WORD_SIZE cost(2,5)
190 bd "(" reg "," xreg ".l)" .
192 LOCAL = {INT bd;} WORD_SIZE cost(2,6) bd "(a6)" .
194 /* pointers may go into DLOCAL's */
195 DLOCAL = {INT bd;} 4 cost(2,6) bd "(a6)" .
198 local_addr = {INT bd;} 4 cost(2,6) bd "(a6)" .
199 regAcon = {A_REG reg; INT bd;} 4 cost(2,6) bd "(" reg ")" .
200 regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8)
201 bd "(" reg "," xreg ".l)" .
202 /* note: in the m68k[24] version %sc always equals 1 */
206 /* Part (ii) in m68020 syntax */
207 absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
208 offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
209 index_off4 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(4,9)
210 "(" bd "," reg "," xreg ".l*" sc ")" .
211 absolute2 = {ADDR bd;} WORD_SIZE cost(4,7) "(" bd ")" .
212 offsetted2 = {A_REG reg; INT bd;} WORD_SIZE cost(2,6) "(" bd "," reg ")" .
213 index_off2 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} WORD_SIZE cost(4,9)
214 "(" bd "," reg "," xreg ".l*" sc ")" .
215 absolute1 = {ADDR bd;} WORD_SIZE cost(4,7) "(" bd ")" .
216 offsetted1 = {A_REG reg; INT bd;} WORD_SIZE cost(2,6) "(" bd "," reg ")" .
217 index_off1 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} WORD_SIZE cost(4,9)
218 "(" bd "," reg "," xreg ".l*" sc ")" .
220 LOCAL = {INT bd;} WORD_SIZE cost(2,6) "(" bd ",a6)" .
222 /* pointers may go into DLOCAL's */
223 DLOCAL = {INT bd;} 4 cost(2,6) "(" bd ",a6)" .
225 local_addr = {INT bd;} 4 cost(2,3) "(" bd ",a6)" .
226 regAcon = {A_REG reg; INT bd;} 4 cost(2,3) "(" bd "," reg ")" .
227 regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,7)
228 "(" bd "," reg "," xreg ".l*" sc ")" .
232 abs_index4 = {INT sc; D_REG4 xreg; ADDR bd;} 4 cost(6,9)
233 "(" bd "," xreg ".l*" sc ")" .
234 OFF_off4 = {A_REG reg; INT bd; ADDR od;} 4 cost(6,19)
235 "([" bd "," reg "]," od ")" .
236 OFF_indoff4 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} 4 cost(6,19)
237 "([" bd "," reg "]," xreg ".l*" sc "," od ")" .
238 INDOFF_off4 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} 4 cost(6,19)
239 "([" bd "," reg "," xreg ".l*" sc "]," od ")" .
240 ABS_off4 = {ADDR bd; ADDR od;} 4 cost(8,22) "([" bd "]," od ")" .
241 ABS_indoff4 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} 4 cost(8,22)
242 "([" bd "]," xreg ".l*" sc "," od ")" .
243 ABSIND_off4 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} 4 cost(8,22)
244 "([" bd "," xreg ".l*" sc "]," od ")" .
246 abs_index2 = {INT sc; D_REG4 xreg; ADDR bd;} WORD_SIZE cost(6,9)
247 "(" bd "," xreg ".l*" sc ")" .
248 OFF_off2 = {A_REG reg; INT bd; ADDR od;} WORD_SIZE cost(6,19)
249 "([" bd "," reg "]," od ")" .
250 OFF_indoff2 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} WORD_SIZE cost(6,19)
251 "([" bd "," reg "]," xreg ".l*" sc "," od ")" .
252 INDOFF_off2 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} WORD_SIZE cost(6,19)
253 "([" bd "," reg "," xreg ".l*" sc "]," od ")" .
254 ABS_off2 = {ADDR bd; ADDR od;} WORD_SIZE cost(8,22) "([" bd "]," od ")" .
255 ABS_indoff2 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} WORD_SIZE cost(8,22)
256 "([" bd "]," xreg ".l*" sc "," od ")" .
257 ABSIND_off2 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} WORD_SIZE cost(8,22)
258 "([" bd "," xreg ".l*" sc "]," od ")" .
260 abs_index1 = {INT sc; D_REG4 xreg; ADDR bd;} WORD_SIZE cost(6,9)
261 "(" bd "," xreg ".l*" sc ")" .
262 OFF_off1 = {A_REG reg; INT bd; ADDR od;} WORD_SIZE cost(6,19)
263 "([" bd "," reg "]," od ")" .
264 OFF_indoff1 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} WORD_SIZE cost(6,19)
265 "([" bd "," reg "]," xreg ".l*" sc "," od ")" .
266 INDOFF_off1 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} WORD_SIZE cost(6,19)
267 "([" bd "," reg "," xreg ".l*" sc "]," od ")" .
268 ABS_off1 = {ADDR bd; ADDR od;} WORD_SIZE cost(8,22) "([" bd "]," od ")" .
269 ABS_indoff1 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} WORD_SIZE cost(8,22)
270 "([" bd "]," xreg ".l*" sc "," od ")" .
271 ABSIND_off1 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} WORD_SIZE cost(8,22)
272 "([" bd "," xreg ".l*" sc "]," od ")" .
274 ILOCAL = {INT bd;} WORD_SIZE cost(4,16) "([" bd ",a6])" .
276 off_con = {A_REG reg; INT bd; ADDR od;} 4 cost(6,18)
277 "([" bd "," reg "]," od ")".
278 off_regXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} 4 cost(6,18)
279 "([" bd "," reg "]," xreg ".l*" sc "," od ")" .
280 indoff_con = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} 4 cost(6,18)
281 "([" bd "," reg "," xreg ".l*" sc "]," od ")" .
282 abs_con = {ADDR bd; ADDR od;} 4 cost(8,21) "([" bd "]," od ")" .
283 abs_regXcon = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} 4 cost(8,21)
284 "([" bd "]," xreg ".l*" sc "," od ")" .
285 absind_con = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} 4 cost(8,21)
286 "([" bd "," xreg ".l*" sc "]," od ")" .
287 ext_regX = {INT sc; D_REG4 xreg; ADDR bd;} 4 cost(6,15)
288 "(" bd "," xreg ".l*" sc ")" .
290 regX = {INT sc; D_REG4 xreg;} 4 cost(2,7) "(" xreg ".l*" sc ")" .
291 DREG_pair = {D_REG4 reg1; D_REG4 reg2;} 8 cost(2,0) reg1 ":" reg2 .
293 #define t_regAregXcon regAregXcon
294 #define t_regAcon regAcon
297 t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
298 t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
307 /* The SETS list cannot be kept as 'readable' as the TOKENS
308 * list because cgg is one pass.
309 * We makes use of the fact that sets are indeed sets. Thus
310 * D_REG + D_REG4 == D_REG, when the wordsize is 4.
313 sconsts = small_const + bconst .
314 consts = const + sconsts + zero_const.
316 #define small_const4 small_const
317 #define zero_const4 zero_const
318 #define bconst4 bconst
320 #define sconsts4 sconsts
321 #define consts4 consts
323 sconsts4 = small_const4 + bconst4 .
324 consts4 = const4 + sconsts4 + zero_const4.
328 /* A m68k2/m68k4 part */
329 data4 = D_REG4 + DLOCAL + consts4 + post_inc4 + pre_dec4 +
330 indirect4 + offsetted4 + index_off4 + absolute4 +
332 memory4 = data4 - D_REG4 - dreg4 .
333 control4 = indirect4 + offsetted4 + index_off4 + absolute4 +
335 alterable4 = data4 + A_REG - consts4 - ext_addr .
336 any4 = data4 + A_REG . /* all four above together */
339 data2 = D_REG + LOCAL + dreg2 + post_inc2 + pre_dec2 +
340 indirect2 + offsetted2 + index_off2 + absolute2 +
342 memory2 = data2 - D_REG - dreg2 .
343 control2 = indirect2 + offsetted2 + index_off2 + absolute2 + LOCAL.
345 data2 = dreg2 + post_inc2 + pre_dec2 + indirect2 +
346 offsetted2 + index_off2 + absolute2 + consts .
347 memory2 = data2 - dreg2 .
348 control2 = indirect2 + offsetted2 + index_off2 + absolute2 .
350 alterable2 = data2 + D_REG - consts .
351 any2 = data2 + D_REG .
353 data1 = dreg1 + post_inc1 + pre_dec1 + indirect1 +
354 offsetted1 + index_off1 + absolute1 + consts .
355 memory1 = data1 - dreg1 .
356 control1 = indirect1 + offsetted1 + index_off1 + absolute1 .
357 alterable1 = data1 + D_REG - consts .
358 any1 = data1 + D_REG .
362 data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
363 offsetted4 + OFF_off4 + OFF_indoff4 +
364 INDOFF_off4 + dreg4 +
365 ABS_off4 + ABS_indoff4 + ABSIND_off4 +
366 absolute4 + abs_index4 + consts4 + ext_addr +
372 memory4 = data4 - D_REG4 - dreg4 .
373 control4 = memory4 - (post_inc4 + pre_dec4 + consts4 + ext_addr).
374 alterable4 = data4 + A_REG - consts - ext_addr .
375 any4 = data4 + A_REG . /* all four above together */
378 data2 = D_REG + LOCAL+ ILOCAL+
379 dreg2 + indirect2 + post_inc2 + pre_dec2 + index_off2 +
380 offsetted2 + OFF_off2 + OFF_indoff2 +
382 ABS_off2 + ABS_indoff2 + ABSIND_off2 +
383 absolute2 + abs_index2 + consts .
384 memory2 = data2 - D_REG - dreg2 .
386 data2 = dreg2 + indirect2 + post_inc2 + pre_dec2 + index_off2 +
387 offsetted2 + OFF_off2 + OFF_indoff2 +
389 ABS_off2 + ABS_indoff2 + ABSIND_off2 +
390 absolute2 + abs_index2 + consts .
391 memory2 = data2 - dreg2 .
393 control2 = memory2 - (post_inc2 + pre_dec2 + consts ) .
394 alterable2 = data2 + D_REG - consts .
395 any2 = data2 + D_REG. /* all four above together */
397 data1 = dreg1 + indirect1 + post_inc1 + pre_dec1 + index_off1 +
398 offsetted1 + OFF_off1 + OFF_indoff1 +
400 ABS_off1 + ABS_indoff1 + ABSIND_off1 +
401 absolute1 + abs_index1 + consts .
402 memory1 = data1 - dreg1 .
403 control1 = memory1 - (post_inc1 + pre_dec1 + consts ) .
404 alterable1 = data1 + D_REG - consts .
405 any1 = data1 + D_REG. /* all four above together */
407 #endif /* TBL68020 */
408 /* This is a common part */
410 /* Not any4, since any is used in 'with' and not in 'kills' */
413 any = any4 + any2 + any1 .
415 control = control4 + control2 + control1 .
416 indirect = indirect4 + indirect2 + indirect1 .
417 offsetted = offsetted4 + offsetted2 + offsetted1 .
418 index_off = index_off4 + index_off2 + index_off1 .
419 absolute = absolute4 + absolute2 + absolute1 .
420 pre_post = pre_dec4 + pre_dec2 + pre_dec1 +
421 post_inc4 + post_inc2 + post_inc1 .
424 /* A m68k2/m68k4 part */
425 regind_addr = regAcon + regAregXcon + t_regAcon + t_regAregXcon .
426 address = ext_addr + local_addr + regAcon + regAregXcon .
427 all_regind = indirect + offsetted + pre_post + index_off +
429 all_indir = all_regind .
430 allexceptcon = ALL - ( D_REG + A_REG + consts + dreg2 + dreg1 +
431 local_addr + ext_addr + regAcon + regAregXcon +
432 t_regAcon + t_regAregXcon ) .
433 use_index = index_off4 + index_off2 + index_off1 .
437 reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
438 memind4 = reg_memind4 +
439 ABS_off4 + ABS_indoff4 .
440 reg_memind2 = OFF_off2 + OFF_indoff2 + INDOFF_off2 .
441 memind2 = reg_memind2 +
442 ABS_off2 + ABS_indoff2 .
443 reg_memind1 = OFF_off1 + OFF_indoff1 + INDOFF_off1 .
444 memind1 = reg_memind1 +
445 ABS_off1 + ABS_indoff1 .
446 reg_memind = reg_memind4 + reg_memind2 + reg_memind1 .
447 memind = memind4 + memind2 + memind1 .
448 regind_addr = regAcon + regAregXcon +
449 off_con + off_regXcon +
451 address = regind_addr +
452 ext_addr + local_addr +
453 abs_con + abs_regXcon +
456 all_regind = indirect + offsetted + index_off + pre_post +
457 reg_memind + regind_addr + areg .
458 all_indir = all_regind + memind + ILOCAL .
459 allexceptcon = ALL - ( D_REG + A_REG + consts + dreg2 + dreg1 +
460 local_addr + ext_addr + regAcon + regAregXcon + ext_regX ) .
461 use_index4 = index_off4 + abs_index4 +
462 OFF_indoff4 + INDOFF_off4 +
463 ABS_indoff4 + ABSIND_off4 .
464 use_index2 = index_off2 + abs_index2 +
465 OFF_indoff2 + INDOFF_off2 +
466 ABS_indoff2 + ABSIND_off2 .
467 use_index1 = index_off1 + abs_index1 +
468 OFF_indoff1 + INDOFF_off1 +
469 ABS_indoff1 + ABSIND_off1 .
470 use_indaddr = regAregXcon +
471 off_regXcon + indoff_con +
472 abs_regXcon + absind_con +
475 use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
477 #endif /* TBL68020 */
479 posextern = absolute + all_indir .
483 #define genreg genreg2
485 #define genreg genreg4
487 genreg4 = D_REG4 + A_REG.
488 label = llabel + slabel .
489 immediate4 = consts4 + ext_addr .
491 immediate2 = consts .
493 conreg4 = D_REG4 + immediate4 .
494 conreg2 = dreg2 + consts + D_REG .
495 conreg1 = dreg1 + consts + D_REG .
497 conreg = conreg1 + conreg2 .
499 conreg = conreg1 + conreg2 + conreg4 .
501 shconreg = D_REG + small_const .
502 datalt4 = data4 * alterable4 .
503 datalt2 = data2 * alterable2 .
504 datalt1 = data1 * alterable1 .
505 datalt = datalt4 + datalt2 + datalt1 .
506 memalt4 = memory4 * alterable4 .
507 memalt2 = memory2 * alterable2 .
508 memalt1 = memory1 * alterable1 .
511 /* A m68k2/m68k4 part */
512 imm_cmp4 = alterable4 - A_REG .
513 imm_cmp2 = alterable2 + D_REG .
514 imm_cmp1 = datalt1 + D_REG .
516 test_set4 = datalt4 + extend2 + extend1_4 .
518 test_set2 = datalt2 + extend1 .
520 test_set2 = datalt2 .
522 test_set1 = datalt1 .
526 imm_cmp4 = any4 - immediate4 - A_REG .
527 imm_cmp2 = any2 - consts .
528 imm_cmp1 = any1 - consts .
530 test_set4 = any4 - immediate4 + extend2 + extend1_4 .
532 test_set2 = data2 + extend1 - immediate2 .
534 test_set2 = data2 - consts .
536 test_set1 = data1 - consts .
538 #endif /* TBL68020 */
540 test_set = test_set4 + test_set2 + test_set1 .
543 t_address = address + t_regAregXcon + t_regAcon .
545 #define t_address address
546 #endif /* TBL68020 */
549 freg = FD_REG + FS_REG .
550 store4 = any4 + FS_REG .
559 #include "instrmacs.h"
563 /* Since the 68000 , the 68010 and the 68020 instruction sets are rather
564 * extensive, especially because e.g. 'add.l' and 'add.w' are
565 * considered different instructions, only those instructions are
566 * listed here that are used in the rest of this table.
568 * Instruction timing cost cannot be accurately given, nor the timing
569 * cost for getting operands. Detailed information about this can be
570 * found in the "MC68020 User's Manual", section 9, about instruction
571 * timing. The cost used in this table are 'worst case' cost, as
572 * mentioned in section 9 of the user's manual. Furthermore, the
573 * timing information for the 68k[24] and the 68020 differ, which
574 * means that the 68k[24] will not always have the best code
577 * The first few instructions had to be added because register
578 * variables are used. The LOCALs below are register variables.
579 * One may not conclude that these operations are also allowed
580 * on LOCALs that are not register variables.
581 * The cost have been adapted, but are not accurate; when 'real'
582 * LOCALs are used the cost are very inaccurate.
585 add_i ADD_I any_int:ro, LOCAL:rw:cc cost(0,0).
586 sub_i SUB_I any_int:ro, LOCAL:rw:cc cost(0,0).
587 lea address:ro, DLOCAL:wo cost(0,0).
588 sh "illegal" shconreg+LOCAL:ro, LOCAL:rw:cc cost(0,0).
589 xxx "illegal" data4:ro, LOCAL:rw:cc cost(0,0).
590 xxx "illegal" LOCAL:ro, alterable4:rw:cc cost(0,0).
592 /* divs_w "divs.w" data2:ro, LOCAL:rw:cc cost(0,56). */
593 /* divu_w "divu.w" data2:ro, LOCAL:rw:cc cost(0,44). */
594 muls_w "muls.w" data2:ro, LOCAL:rw:cc cost(0,28).
595 mulu_w "mulu.w" data2:ro, LOCAL:rw:cc cost(0,28).
597 #if TBL68020 && WORD_SIZE!=2
598 divs_l "divs.l" data4:ro, LOCAL:rw:cc cost(0,90).
599 divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
600 muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
601 mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
602 #endif /* TBL68020 */
605 add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
607 add_l "add.l" any4:ro, D_REG+LOCAL:rw:cc cost(2,3).
609 add_l "add.l" any4:ro, A_REG+DLOCAL+areg:rw cost(2,3).
610 add_l "add.l" conreg4:ro, alterable4:rw:cc cost(2,6).
612 add_w "add.w" any2:ro, D_REG+LOCAL:rw:cc cost(2,3).
613 add_w "add.w" conreg2:ro, alterable2:rw:cc cost(2,6).
615 and_l "and.l" data4:ro, D_REG4:rw:cc cost(2,3).
616 and_l "and.l" D_REG4:ro, memalt4:rw:cc cost(2,6).
617 and_l "and.l" consts4:ro, datalt4:rw:cc cost(2,6).
619 and_w "and.w" data2:ro, D_REG:rw:cc cost(2,3).
620 and_w "and.w" D_REG:ro, memalt2:rw:cc cost(2,6).
621 and_w "and.w" consts:ro, datalt2:rw:cc cost(2,6).
623 asl_l "asl.l" shconreg:ro, D_REG4:rw:cc cost(2,5).
624 asl "asl #1," memalt2:rw:cc cost(2,4).
625 asr_l "asr.l" shconreg:ro, D_REG4:rw:cc cost(2,4).
626 asr "asr #1," memalt2:rw:cc cost(2,4).
628 asl_w "asl.w" shconreg:ro, D_REG:rw:cc cost(2,5).
629 asr_w "asr.w" shconreg:ro, D_REG:rw:cc cost(2,4).
631 bclr const:ro, D_REG:rw kills:cc cost(2,4).
647 bset conreg2:ro, D_REG+D_REG4:rw kills :cc cost(2,4).
648 btst conreg2:ro, any1:rw kills :cc cost(2,3).
649 /* Check dreg[21] for m68020 and m68k2 */
650 clr_l "clr.l" D_REG4+dreg4:wo:cc cost(2,3).
651 clr_l "clr.l" memalt4:wo:cc cost(2,6).
652 clr_w "clr.w" D_REG+dreg2:wo:cc cost(2,2).
653 clr_w "clr.w" memalt2:wo:cc cost(2,4).
654 clr_b "clr.b" D_REG+dreg1:wo:cc cost(2,2).
655 clr_b "clr.b" memalt1:wo:cc cost(2,4).
656 cmp_l "cmp.l" any4:ro, genreg4:ro kills :cc cost(2,3).
657 cmp_l "cmp.l" post_inc4:ro, post_inc4:ro kills :cc cost(2,2).
658 cmp_l "cmp.l" immediate4:ro, imm_cmp4:ro kills :cc cost(2,2).
660 cmp_w "cmp.w" any2+extend2:ro, D_REG+dreg2+extend2:ro kills :cc cost(2,2).
662 cmp_w "cmp.w" any2+extend2:ro, dreg2+extend2:ro kills :cc cost(2,2).
664 cmp_w "cmp.w" post_inc2:ro, post_inc2:ro kills :cc cost(2,2).
665 cmp_w "cmp.w" consts:ro, imm_cmp2:ro kills :cc cost(2,2).
666 cmp_b "cmp.b" any1+extend1+extend1_4:ro, dreg1+extend1+extend1_4:ro kills :cc cost(2,3).
667 cmp_b "cmp.b" post_inc1:ro, post_inc1:ro kills :cc cost(2,2).
668 cmp_b "cmp.b" consts:ro, imm_cmp1:ro kills :cc cost(2,2).
669 dbf D_REG4:rw, label cost(2,5).
670 eor_l "eor.l" conreg4:ro, datalt4:rw:cc cost(2,6).
672 eor_w "eor.w" conreg2:ro, datalt2:rw:cc cost(2,4).
674 /* in the next two instructions: LOCAL only allowed if register var */
675 ext_l "ext.l" D_REG+LOCAL+D_REG4:rw:cc cost(2,2).
676 ext_w "ext.w" D_REG+LOCAL+D_REG4:rw:cc cost(2,2).
677 jmp address+control4 cost(2,0).
678 jsr address+control4 kills :cc d0 d1 d2 a0 a1 cost(2,3).
679 lea address+control4:ro, A_REG+areg:wo cost(2,0).
681 lsl_l "lsl.l" shconreg:ro, D_REG:rw:cc cost(2,4).
682 lsl "lsl #1," memalt2:rw:cc cost(2,4).
684 lsr_l "lsr.l" shconreg:ro, D_REG4:rw:cc cost(2,4).
686 lsr_w "lsr.w" shconreg:ro, D_REG:rw:cc cost(2,4).
688 lsr "lsr #1," memalt2:rw:cc cost(2,4).
689 /* move_l does not set the condition codes if the destination is an
692 move_l "move.l" any4:ro, A_REG+areg:wo cost(2,2).
693 move_l "move.l" any4:ro, alterable4+dreg4-(areg+A_REG):wo:cc cost(2,2).
695 move_l "move.l" sconsts:ro, D_REG+dreg2:wo:cc cost(2,2).
697 move_l "move.l" any2:ro, alterable4+dreg4-(areg+A_REG):wo:cc cost(2,2).
699 move_w "move.w" any2:ro, alterable2+dreg2:wo:cc cost(2,2).
700 move_b "move.b" any1:ro, alterable1+dreg2:wo:cc cost(2,2).
702 move_w "move.w" any2:ro, alterable2+dreg4:wo:cc cost(2,2).
703 move_b "move.b" any1:ro, alterable1+dreg4:wo:cc cost(2,2).
705 neg_b "neg.b" D_REG:rw:cc cost(2,3).
706 neg_w "neg.w" D_REG:rw:cc cost(2,3).
707 neg_l "neg.l" D_REG4:rw:cc cost(2,3).
708 neg_l "neg.l" memory4:rw:cc cost(2,6).
710 neg_w "neg.w" memory2:rw:cc cost(2,6).
712 not_l "not.l" D_REG4:rw:cc cost(2,3).
713 not_l "not.l" memory4:rw:cc cost(2,6).
715 not_w "not.w" D_REG:rw:cc cost(2,3).
716 not_w "not.w" memory2:rw:cc cost(2,6).
718 or_l "or.l" data4:ro, D_REG4:rw:cc cost(2,3).
719 or_l "or.l" D_REG4:ro, memalt4:rw:cc cost(2,6).
720 or_l "or.l" consts4:ro, datalt4:rw:cc cost(2,6).
722 or_w "or.w" data2:ro, D_REG:rw:cc cost(2,3).
723 or_w "or.w" D_REG:ro, memalt2:rw:cc cost(2,6).
724 or_w "or.w" consts:ro, datalt2:rw:cc cost(2,6).
726 rol_l "rol.l" shconreg:ro, D_REG4:rw:cc cost(2,4).
727 rol "rol #1," memalt2:rw:cc cost(2,4).
728 ror_l "ror.l" shconreg:ro, D_REG4:rw:cc cost(2,4).
729 ror "ror #1," memalt2:rw:cc cost(2,4).
731 rol_w "rol.w" shconreg:ro, D_REG:rw:cc cost(2,4).
732 ror_w "ror.w" shconreg:ro, D_REG:rw:cc cost(2,4).
734 roxl "roxl #1," memalt2:rw:cc cost(2,4).
735 roxr "roxr #1," memalt2:rw:cc cost(2,4).
736 sne datalt1:rw cost(2,3).
737 sub_l "sub.l" any4:ro, D_REG4:rw:cc cost(2,3).
738 sub_l "sub.l" any4+areg:ro, A_REG+areg:rw cost(2,3).
739 sub_l "sub.l" conreg4:ro, alterable4:rw:cc cost(2,6).
741 sub_w "sub.w" any2:ro, D_REG+LOCAL:rw:cc cost(2,3).
742 sub_w "sub.w" conreg2:ro, alterable2:rw:cc cost(2,6).
743 /* On a swap, we only want the lower part of D_REG, so don't set cc */
744 swap D_REG:rw kills :cc cost(2,2).
746 tst_l "tst.l" test_set4:ro:cc cost(2,3).
747 tst_w "tst.w" test_set2+extend2:ro:cc cost(2,3).
748 tst_b "tst.b" test_set1+extend1+extend1_4:ro:cc cost(2,3).
749 unlk A_REG cost(2,6).
751 bxx "illegal" label cost(2,5).
752 sxx "illegal" any_int:wo cost(2,5).
754 s4xx "illegal" any4:wo cost(2,5).
755 xxx "illegal" any4+any2:ro, any4+any2:rw:cc cost(2,3).
756 bit "illegal" control4+control2:rw:cc cost(2,6).
758 xxx "illegal" any4:ro, any4:rw:cc cost(2,3).
759 bit "illegal" control4:rw:cc cost(2,6).
761 sh "illegal" shconreg:ro, D_REG:rw:cc cost(2,4).
762 shw "illegal" control2:rw:cc cost(2,4).
765 divs_w "divs.w" data2:ro, D_REG:rw:cc cost(0,56).
766 divu_w "divu.w" data2:ro, D_REG:rw:cc cost(0,44).
767 muls_w "muls.w" data2:ro, D_REG:rw:cc cost(0,28).
768 mulu_w "mulu.w" data2:ro, D_REG:rw:cc cost(0,28).
771 cmp2_l "cmp2.l" address+control4:ro, genreg4:ro kills :cc cost(2,18).
772 divs_l "divs.l" data4:ro, D_REG4:rw:cc cost(2,90).
773 divu_l "divu.l" data4:ro, D_REG4:rw:cc cost(2,78).
774 divsl_l "divsl.l" data4:ro, DREG_pair:rw kills :cc cost(2,90).
775 divul_l "divul.l" data4:ro, DREG_pair:rw kills :cc cost(2,78).
776 pea address+control4+regX cost(2,4).
778 cmp2_w "cmp2.w" address+control2:ro, genreg2:ro kills :cc cost(2,18).
779 extb_l "extb.l" extend1_4+D_REG4:rw:cc cost(2,4).
780 muls_l "muls.l" data4:ro, D_REG4:rw:cc cost(2,44).
781 mulu_l "mulu.l" data4:ro, D_REG4:rw:cc cost(2,44).
783 /* in the next instruction: LOCAL only allowed if register var */
784 extb_l "extb.l" extend1_4+D_REG+LOCAL:rw:cc cost(2,4).
785 muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
786 mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
789 pea address+control4 cost(2,4).
790 #endif /* TBL68020 */
792 /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
793 * Extra pseudo instruction; it just kills a D_REG;
794 * it is necessary with long divides where remainders are important;
795 * see also: 'pat rmi' and 'pat rmu'
796 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
797 killreg "! kill" D_REG+D_REG4+A_REG:wo cost(0,0).
798 killcc "! killcc" kills :cc cost(0,0).
800 /* These descriptions are not very accurate, because we have no
801 other 8-byte objects in the table.
803 fmove_s "fmove.s" data4:ro, freg:wo cost(4,100).
804 fmove_s "fmove.s" freg:ro, data4:wo cost(4,100).
805 fmove_d "fmove.d" freg:ro, data4:wo cost(4,100).
806 fmove_d "fmove.d" data4:ro, freg:ro cost(4,100).
807 fmove_l "fmove.l" freg:ro, D_REG:wo cost(4,100).
808 fmove_l "fmove.l" data4:ro, freg:wo cost(4,100).
809 fmove freg:ro,freg:wo cost(4,100).
810 fadd_s "fadd.s" data4:ro, freg:rw cost(4,100).
811 fadd_d "fadd.d" data4:ro, freg:rw cost(4,100).
812 fsub_s "fsub.s" data4:ro, freg:rw cost(4,100).
813 fsub_d "fsub.d" data4:ro, freg:rw cost(4,100).
814 fsub freg:ro, freg:rw cost(4,100).
815 fmul freg:ro, freg:rw cost(4,100).
816 fmul_s "fmul.s" data4:ro, freg:rw cost(4,100).
817 fmul_d "fmul.d" data4:ro, freg:rw cost(4,100).
818 fdiv freg:ro, freg:rw cost(4,100).
819 fdiv_s "fdiv.s" data4:ro, freg:rw cost(4,100).
820 fdiv_d "fdiv.d" data4:ro, freg:rw cost(4,100).
821 fcmp freg:ro, freg:ro cost(4,100).
822 fbeq label:ro cost(4,4).
823 fblt label:ro cost(4,4).
824 fmovecr const:ro, freg:rw cost(4,100).
825 fabs freg:rw cost(4,100).
826 fneg freg:rw cost(4,100).
827 fgetman freg:rw cost(4,100).
828 fintrz freg:ro, freg:wo cost(4,100).
829 fgetexp freg:ro, freg:wo cost(4,100).
830 fsub_l "fsub.l" const:ro, freg:rw cost(4,100).
836 from consts %num==0 to D_REG4+dreg4
840 from zero_const4 %num==0 to A_REG+areg
843 from zero_const4 %num==0 to D_REG4+dreg4
847 from consts %num==0 to A_REG+areg
851 from consts %num==0 to D_REG+dreg2
854 from sconsts to D_REG+dreg2
855 gen move_l %1,%2 /* uses moveq */
857 from consts to D_REG4+dreg4
858 gen move_l {const4, %1.num},%2
862 from sconsts4+zero_const4 %num==0 to memalt4
864 from consts %num==0 to memalt4
868 from consts %num==0 to memalt2
871 from consts %num==0 to memalt1
874 from consts to memalt1
875 gen move_b {const, low8(%1.num)}, %2
878 from consts to memalt2
879 gen move_w {const, low16(%1.num)}, %2
882 from regAcon %bd==0 to A_REG+areg
883 gen move_l %1.reg, %2
886 from t_regAregXcon sfit(%bd, 8) to A_REG+areg
887 gen lea {regAregXcon, %1.reg, %1.xreg, 1, %1.bd}, %2
889 from t_regAregXcon to A_REG+areg
890 gen lea {regAregXcon, %1.reg, %1.xreg, 1, 0}, %2
891 add_l {const4, %1.bd}, %2
893 from t_regAcon sfit(%bd, 16) to A_REG+areg
894 gen lea {regAcon, %1.reg, %1.bd}, %2
896 from t_regAcon to A_REG+areg
897 gen move_l %1.reg, %2
898 add_l {const4, %1.bd}, %2
899 #endif /* TBL68020 */
901 from address - ext_addr to A_REG+areg
905 from ext_addr to A_REG+areg
906 gen lea {absolute4, %1.bd}, %2
909 from any4 to areg+A_REG
912 from any4 to alterable4-(areg+A_REG)
915 from any2 to alterable2
918 from any1 to alterable1
922 from any4-sconsts4 to A_REG+areg
930 from any1 to dreg_int
944 from FS_REG to datalt4
950 /* For the 68020 and m68k4, the extend1_4 will be extend1 */
951 to test test_set4-(extend2+extend1+extend1_4)
954 to test test_set2+extend2
957 to test test_set1+extend1+extend1_4
965 from consts %num==0 to STACK
966 gen clr_l {pre_dec4, sp}
968 from zero_const4 to STACK
969 gen clr_l {pre_dec4, sp}
970 from consts %num==0 to STACK
971 gen clr_w {pre_dec2, sp}
975 from t_regAregXcon sfit(%bd, 8) to STACK
976 gen pea {regAregXcon, %1.reg, %1.xreg, 1, %1.bd}
978 from t_regAregXcon to STACK
979 gen pea {regAregXcon, %1.reg, %1.xreg, 1, 0}
980 add_l {const4, %1.bd}, {indirect4, sp}
982 from t_regAcon sfit(%bd, 16) to STACK
983 gen pea {regAcon, %1.reg, %1.bd}
985 from t_regAcon to STACK
986 gen move_l %1.reg, {pre_dec4, sp}
987 add_l {const4, %1.bd}, {indirect4, sp}
988 #endif /* TBL68020 */
991 gen pea {indirect4, %1}
993 from address - ext_addr to STACK
996 from ext_addr to STACK
997 gen pea {absolute4, %1.bd}
1000 from consts to STACK
1001 gen pea {absolute4, %1.num}
1003 from sconsts4 to STACK
1004 gen pea {absolute4, %1.num}
1005 from const4 to STACK
1006 gen pea {absolute4, %1.num}
1010 gen move_l %1, {pre_dec4, sp}
1016 move_w %1, {dreg2, %a}
1017 move_l %a, {pre_dec4, sp}
1020 gen clr_l {pre_dec4, sp}
1021 move_w %1, {offsetted2, sp, 2}
1024 gen move_w %1, {pre_dec2, sp}
1031 move_b %1, {dreg1, %a}
1032 move_l %a, {pre_dec4, sp}
1035 move_b %1, {dreg1, %a}
1036 move_w %a, {pre_dec2, sp}
1041 gen clr_l {pre_dec4, sp}
1042 move_b %1, {offsetted1, sp, 3}
1044 gen clr_w {pre_dec2, sp}
1045 move_b %1, {offsetted1, sp, 1}
1048 from extend2 to STACK
1050 move_l %1.reg,{pre_dec4, sp}
1052 from extend1_4 to STACK
1059 move_l %1.reg,{pre_dec4, sp}
1062 from extend1 to STACK
1064 move_w %1.reg,{pre_dec2, sp}
1070 #endif /* TBL68020 */
1071 /* This last stackingrule is never used: whenever regX is put on
1072 * the fakestack, some em-instuctions are left that remove it
1073 * immediately. However cgg complained about not having a
1074 * stackingrule for regX, so here it is
1078 from FS_REG to STACK
1079 gen fmove_s %1,{pre_dec4,sp}
1081 from FD_REG to STACK
1082 gen fmove_d %1,{pre_dec4,sp}
1089 gen move_l {post_inc4, sp}, %a
1095 gen move_w {post_inc2,sp}, %a
1101 gen move_l {post_inc4, sp}, %a
1107 gen fmove_s {post_inc4, sp}, %a
1111 gen fmove_d {post_inc4, sp}, %a
1116 from t_regAregXcon sfit(%bd, 8)
1117 yields {regAregXcon, %1.reg, %1.xreg, 1, %1.bd}
1121 gen add_l {const4, %1.bd}, %a
1122 yields {regAregXcon, %a, %1.xreg, 1, 0}
1125 * The following coercions are necessary because the code generator
1126 * must be able to make the token from the real stack, otherwise the
1127 * coercion will not be made. Unfortunatly, inside a coercion, we are only
1128 * allowed to allocate 1 register, which means that there is no way to make
1129 * a regAregXcon from the stack, which, in its turn, means that the other
1130 * coercions will not be taken.
1133 uses AA_REG, DD_REG4 = {zero_const4, 0}
1134 gen move_l {post_inc4, sp}, %a
1135 yields {regAregXcon, %a, %b, 1, 0}
1139 gen move_l {post_inc4, sp}, %a
1140 yields {regAcon, %a, 0}
1142 from t_regAcon sfit(%bd, 16)
1143 yields {regAcon, %1.reg, %1.bd}
1146 uses reusing %1, AA_REG=%1.reg
1147 gen add_l {const4, %1.bd}, %a
1149 #endif /* TBL68020 */
1152 from regAregXcon %bd==0 && %sc==1
1153 uses reusing %1, AA_REG = %1.reg
1154 gen add_l {dreg4,%1.xreg},%a
1157 from regAregXcon %sc==1
1158 uses reusing %1, AA_REG = %1.reg
1159 gen add_l {dreg4, %1.xreg}, %a
1160 yields {regAcon, %a, %1.bd}
1165 uses DD_REG4={const4, %1.num} /* uses moveq */
1171 uses reusing %1, DD_REG = %1 yields %a
1175 uses reusing %1, DD_REG4 = %1
1179 uses reusing %1, AA_REG = %1
1183 uses reusing %1, AA_REG = %1
1188 uses reusing %1, FS_REG = %1
1197 gen move_w %1, %a yields %a
1200 uses DD_REG = {zero_const, 0}
1201 gen move_b %1, %a yields %a
1205 gen move_w %1, %a yields {dreg2, %a}
1209 gen move_b %1, %a yields {dreg1, %a}
1212 gen ext_l %1.reg yields %1.reg
1216 gen ext_w %1.reg yields %1.reg
1230 /********************************
1231 * First some longer patterns *
1232 ********************************/
1234 pat lol sbi stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1236 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1237 gen sub_i %1, {LOCAL, $1}
1240 pat lol sbi stl $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_pointer
1241 with conreg_int-bconst
1242 kills all_indir, LOCAL %bd==$1
1243 gen sub_i %1, {LOCAL, $1}
1246 pat lol sbu stl $1==$3 && $2==WORD_SIZE
1247 leaving lol $1 sbi WORD_SIZE stl $1
1249 pat lil sbi sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
1250 with conreg_int-bconst
1252 gen sub_i %1, {indirect_int, regvar($1, reg_pointer)}
1253 neg_i {indirect_int, regvar($1, reg_pointer)}
1255 pat lil sbi sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
1256 with conreg_int-bconst
1258 uses AA_REG = {DLOCAL, $1}
1259 gen sub_i %1, {indirect_int, %a}
1260 neg_i {indirect_int, %a}
1262 pat lil sbu sil $1==$3 && $2==WORD_SIZE
1263 leaving lil $1 sbi WORD_SIZE sil $1
1265 proc lolrbitstl example lol ngi stl
1266 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1267 gen bit* {LOCAL, $1}
1269 pat lol ngi stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1270 call lolrbitstl(NEG_I)
1271 pat lol com stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1272 call lolrbitstl(NOT_I)
1274 proc lolbitstl example lol ngi stl
1275 kills all_indir, LOCAL %bd==$1
1276 gen bit* {LOCAL, $1}
1278 pat lol ngi stl $1==$3 && $2==WORD_SIZE call lolbitstl(NEG_I)
1279 pat lol com stl $1==$3 && $2==WORD_SIZE call lolbitstl(NOT_I)
1281 proc ldlbitsdl example ldl ngi sdl
1282 kills all_indir, DLOCAL %bd==$1
1283 gen bit* {DLOCAL, $1}
1285 pat ldl ngi sdl $1==$3 && $2==4 call ldlbitsdl("neg.l")
1286 pat ldl com sdl $1==$3 && $2==4 call ldlbitsdl("not.l")
1289 proc loebitste example loe ngi ste
1291 gen bit* {absolute_int, $1}
1293 pat loe ngi ste $1==$3 && $2==WORD_SIZE call loebitste(NEG_I)
1294 pat loe com ste $1==$3 && $2==WORD_SIZE call loebitste(NOT_I)
1296 proc ldebitsde example lde ngi sde
1298 gen bit* {absolute4, $1}
1300 pat lde ngi sde $1==$3 && $2==4 call ldebitsde("neg.l")
1301 pat lde com sde $1==$3 && $2==4 call ldebitsde("not.l")
1304 proc lilrbitsil example lil ngi sil
1306 gen bit* {indirect_int, regvar($1, reg_pointer)}
1308 pat lil ngi sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
1309 call lilrbitsil(NEG_I)
1310 pat lil com sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
1311 call lilrbitsil(NOT_I)
1312 pat lil dec sil $1==$3 && inreg($1)==reg_pointer
1313 call lilrbitsil(DEC)
1314 pat lil inc sil $1==$3 && inreg($1)==reg_pointer
1315 call lilrbitsil(INC)
1317 proc lilbitsil example lil ngi sil
1320 gen bit* {ILOCAL, $1}
1322 uses AA_REG = {DLOCAL, $1}
1323 gen bit* {indirect_int, %a}
1326 pat lil ngi sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
1327 call lilbitsil(NEG_I)
1328 pat lil com sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
1329 call lilbitsil(NOT_I)
1330 pat lil dec sil $1==$3 && inreg($1)!=reg_any
1332 pat lil inc sil $1==$3 && inreg($1)!=reg_any
1335 proc lolcshstl example lol loc sli stl
1336 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1337 gen sh* {small_const, $2}, {LOCAL, $1}
1339 pat lol loc sli stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
1340 call lolcshstl(ASL_I)
1341 pat lol loc sri stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
1342 call lolcshstl(ASR_I)
1343 pat lol loc slu stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
1344 call lolcshstl(ASL_I)
1345 pat lol loc sru stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
1346 call lolcshstl(LSR_I)
1347 pat lol loc rol stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
1348 call lolcshstl(ROL_I)
1349 pat lol loc ror stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
1350 call lolcshstl(ROR_I)
1352 proc lolrshstl example lol lol sli stl
1353 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1354 gen sh* {LOCAL, $2}, {LOCAL, $1}
1356 pat lol lol sli stl $1==$4 && inreg($1)==reg_any && $3==WORD_SIZE
1357 && inreg($2)==reg_any
1358 call lolrshstl(ASL_I)
1359 pat lol lol slu stl $1==$4 && inreg($1)==reg_any && $3==WORD_SIZE
1360 && inreg($2)==reg_any
1361 call lolrshstl(ASL_I)
1362 pat lol lol sri stl $1==$4 && inreg($1)==reg_any && $3==WORD_SIZE
1363 && inreg($2)==reg_any
1364 call lolrshstl(ASR_I)
1365 pat lol lol sru stl $1==$4 && inreg($1)==reg_any && $3==WORD_SIZE
1366 && inreg($2)==reg_any
1367 call lolrshstl(LSR_I)
1368 pat lol lol rol stl $1==$4 && inreg($2)==reg_any && $3==WORD_SIZE
1369 && inreg($1)==reg_any
1370 call lolrshstl(ROL_I)
1371 pat lol lol ror stl $1==$4 && inreg($2)==reg_any && $3==WORD_SIZE
1372 && inreg($1)==reg_any
1373 call lolrshstl(ROR_I)
1376 proc lil1shlsil example lil loc sli sil /* only left */
1378 gen shw* {offsetted2, regvar($1, reg_pointer), 2}
1379 roxl {indirect2, regvar($1, reg_pointer)}
1381 pat lil loc sli sil $1==$4 && $2==1 && $3==WORD_SIZE && inreg($1)==reg_pointer
1382 call lil1shlsil("asl #1,")
1383 pat lil loc slu sil $1==$4 && $2==1 && $3==WORD_SIZE && inreg($1)==reg_pointer
1384 call lil1shlsil("asl #1,")
1386 proc lil1shrsil example lil loc sli sil /* only right */
1388 gen shw* {indirect2, regvar($1, reg_pointer)}
1389 roxr {offsetted2, regvar($1, reg_pointer), 2}
1391 pat lil loc sri sil $1==$4 && $2==1 && $3==WORD_SIZE && inreg($1)==reg_pointer
1392 call lil1shrsil("asr #1,")
1393 pat lil loc sru sil $1==$4 && $2==1 && $3==WORD_SIZE && inreg($1)==reg_pointer
1394 call lil1shrsil("lsr #1,")
1399 pat LLP lof inc LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
1401 gen add_i {const, 1}, {offsetted_int, regvar($1, reg_pointer), $2}
1403 pat LLP lof dec LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
1405 gen sub_i {const, 1}, {offsetted_int, regvar($1, reg_pointer), $2}
1407 /* the patterns with adp should use add_l */
1408 pat LLP LFP adp LLP SFP $1==$4 && $2==$5 && inreg($1)==reg_pointer
1410 gen add_l {const4, $3}, {offsetted4, regvar($1, reg_pointer), $2}
1412 pat LEP LFP adp LEP SFP $1==$4 && $2==$5
1414 #if TBL68020 && FANCY_MODES
1415 gen add_l {const4, $3}, {ABS_off4, $1, $2}
1417 uses AA_REG={absolute4, $1}
1418 gen add_l {const4, $3}, {offsetted4, %a, $2}
1421 pat LEP loi adp LEP sti $1==$4 && $2==4 && $5==4
1423 #if TBL68020 && FANCY_MODES
1424 gen add_l {const4, $3}, {ABS_off4, $1, 0}
1426 uses AA_REG={absolute4, $1}
1427 gen add_l {const4, $3}, {indirect4, %a}
1431 pat lil lof adp lil stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
1433 #if TBL68020 && FANCY_MODES
1434 gen add_l {const4, $3}, {OFF_off4, regvar($1, reg_pointer), 0, $2}
1436 uses AA_REG={indirect4, regvar($1, reg_pointer)}
1437 gen add_l {const4, $3}, {offsetted4, %a, $2}
1440 pat lil loi adp lil sti $1==$4 && $2==4 && $5==4 && inreg($1)==reg_pointer
1442 #if TBL68020 && FANCY_MODES
1443 gen add_l {const4, $3}, {OFF_off4, regvar($1, reg_pointer), 0, 0}
1445 uses AA_REG={indirect4, regvar($1, reg_pointer)}
1446 gen add_l {const4, $3}, {indirect4, %a}
1448 #endif /* WORD_SIZE==2 */
1450 pat lol inl $1==$2 && inreg($1)==reg_any
1451 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1452 uses DD_REG = {LOCAL, $1}
1453 gen add_i {const, 1}, {LOCAL, $1}
1457 pat lol del $1==$2 && inreg($1)==reg_any
1458 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1459 uses DD_REG = {LOCAL, $1}
1460 gen sub_i {const, 1}, {LOCAL, $1}
1464 /* the following rules are for unsigneds, since del and inl work on ints */
1465 pat lol loc lol adu stl $1==$3 && $3==$5 && $4==WORD_SIZE && inreg($1)==reg_any
1466 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1467 uses DD_REG = {LOCAL, $1}
1468 gen add_i {const, $2}, {LOCAL, $1}
1472 pat lol loc lol adu stl $1==$3 && $3==$5 && $4==WORD_SIZE
1473 kills all_indir, LOCAL %bd==$1
1474 uses DD_REG = {LOCAL, $1}
1475 gen add_i {const, $2}, {LOCAL, $1}
1479 pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE && inreg($1)==reg_any
1480 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1481 uses DD_REG = {LOCAL, $1}
1482 gen sub_i {const, $3}, {LOCAL, $1}
1486 pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
1487 kills all_indir, LOCAL %bd==$1
1488 uses DD_REG = {LOCAL, $1}
1489 gen sub_i {const, $3}, {LOCAL, $1}
1493 pat loe loc loe adu ste $1==$3 && $3==$5 && $4==WORD_SIZE
1495 uses DD_REG = {absolute_int, $1}
1496 gen add_i {const,$2}, {absolute_int, $1}
1500 pat loe dup loc sbu ste $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
1502 uses DD_REG = {absolute_int, $1}
1503 gen sub_i {const,$3}, {absolute_int, $1}
1507 pat lil loc lil adu sil $1==$3 && $3==$5 && $4==WORD_SIZE
1508 && inreg($1)==reg_pointer
1510 uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
1511 gen add_i {const, $2}, {indirect_int, regvar($1, reg_pointer)}
1515 pat lil dup loc sbu sil $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
1516 && inreg($1)==reg_pointer
1518 uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
1519 gen sub_i {const, $3}, {indirect_int, regvar($1, reg_pointer)}
1523 proc lolxxstl example lol and stl
1524 with data_int-bconst
1525 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1526 gen xxx* %1, {LOCAL, $1}
1528 pat lol adi stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1529 call lolxxstl(ADD_I)
1530 pat lol adu stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1531 call lolxxstl(ADD_I)
1532 pat lol and stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1533 call lolxxstl(AND_I)
1534 pat lol ior stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1536 pat lol xor stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1537 with conreg_int-bconst
1538 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1539 gen eor_i %1, {LOCAL, $1}
1541 #if TBL68020 || WORD_SIZE==2
1542 pat lol mli stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1544 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1545 gen muls_i %1, {LOCAL, $1}
1546 pat lol mlu stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
1548 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1549 gen mulu_i %1, {LOCAL, $1}
1550 #endif /* TBL68020 */
1552 proc lolxxxstl example lol adi stl
1553 with conreg_int-bconst
1554 kills all_indir, LOCAL %bd==$1
1555 gen xxx* %1, {LOCAL, $1}
1557 pat lol adi stl $1==$3 && $2==WORD_SIZE call lolxxxstl(ADD_I)
1558 pat lol adu stl $1==$3 && $2==WORD_SIZE call lolxxxstl(ADD_I)
1559 pat lol and stl $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_pointer
1560 call lolxxxstl(AND_I)
1561 pat lol ior stl $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_pointer
1562 call lolxxxstl(OR_I)
1563 pat lol xor stl $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_pointer
1564 call lolxxxstl(EOR_I)
1567 proc ldlxxxsdl example lol adi stl
1568 with conreg4-bconst4
1569 kills all_indir, DLOCAL %bd==$1
1570 gen xxx* %1, {DLOCAL, $1}
1572 pat ldl adi sdl $1==$3 && $2==4 call ldlxxxsdl("add.l")
1573 pat ldl adu sdl $1==$3 && $2==4 call ldlxxxsdl("add.l")
1574 pat ldl and sdl $1==$3 && $2==4 && inreg($1)!=reg_pointer
1575 call ldlxxxsdl("and.l")
1576 pat ldl ior sdl $1==$3 && $2==4 && inreg($1)!=reg_pointer
1577 call ldlxxxsdl("or.l")
1578 pat ldl xor sdl $1==$3 && $2==4 && inreg($1)!=reg_pointer
1579 call ldlxxxsdl("eor.l")
1582 proc lilxxsil example lil and sil
1583 with conreg_int-bconst
1585 gen xxx* %1, {indirect_int, regvar($1, reg_pointer)}
1587 pat lil adi sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
1588 call lilxxsil(ADD_I)
1589 pat lil adu sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
1590 call lilxxsil(ADD_I)
1591 pat lil and sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
1592 call lilxxsil(AND_I)
1593 pat lil ior sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
1595 pat lil xor sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
1596 call lilxxsil(EOR_I)
1598 pat lil ads sil $1==$3 && $2==4 && inreg($1)==reg_pointer
1599 call lilxxsil("add.l")
1602 proc lilxxxsil example lil adi sil
1603 with conreg_int-bconst
1606 gen xxx* %1, {ILOCAL, $1}
1608 uses AA_REG = {DLOCAL, $1}
1609 gen xxx* %1, {indirect_int, %a}
1612 pat lil adi sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
1613 call lilxxxsil(ADD_I)
1614 pat lil adu sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
1615 call lilxxxsil(ADD_I)
1616 pat lil and sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
1617 call lilxxxsil(AND_I)
1618 pat lil ior sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
1619 call lilxxxsil(OR_I)
1620 pat lil xor sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
1621 call lilxxxsil(EOR_I)
1623 pat lil ads sil $1==$3 && $2==4 && inreg($1)!=reg_any
1624 call lilxxxsil("add.l")
1627 proc loexxxste example loe adi ste
1628 with conreg_int-bconst
1630 gen xxx* %1, {absolute_int, $1}
1632 pat loe adi ste $1==$3 && $2==WORD_SIZE call loexxxste(ADD_I)
1633 pat loe adu ste $1==$3 && $2==WORD_SIZE call loexxxste(ADD_I)
1634 pat loe and ste $1==$3 && $2==WORD_SIZE call loexxxste(AND_I)
1635 pat loe ior ste $1==$3 && $2==WORD_SIZE call loexxxste(OR_I)
1636 pat loe xor ste $1==$3 && $2==WORD_SIZE call loexxxste(EOR_I)
1638 pat loe ads ste $1==$3 && $2==4 call loexxxste("add.l")
1642 proc ldexxxsde example lde adi sde
1643 with conreg4-bconst4
1645 gen xxx* %1, {absolute4, $1}
1647 pat lde adi sde $1==$3 && $2==4 call ldexxxsde("add.l")
1648 pat lde adu sde $1==$3 && $2==4 call ldexxxsde("add.l")
1649 pat lde and sde $1==$3 && $2==4 call ldexxxsde("and.l")
1650 pat lde ior sde $1==$3 && $2==4 call ldexxxsde("or.l")
1651 pat lde xor sde $1==$3 && $2==4 call ldexxxsde("eor.l")
1654 proc lollilxxxstl example lol lil adi stl
1655 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1656 gen xxx* {indirect_int, regvar($2, reg_pointer)}, {LOCAL, $1}
1658 pat lol lil adi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1659 && inreg($2)==reg_pointer
1660 call lollilxxxstl(ADD_I)
1661 pat lol lil adu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1662 && inreg($2)==reg_pointer
1663 call lollilxxxstl(ADD_I)
1664 pat lol lil sbi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1665 && inreg($2)==reg_pointer
1666 call lollilxxxstl(SUB_I)
1667 pat lol lil sbu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1668 && inreg($2)==reg_pointer
1669 call lollilxxxstl(SUB_I)
1670 pat lol lil and stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1671 && inreg($2)==reg_pointer
1672 call lollilxxxstl(AND_I)
1673 pat lol lil ior stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1674 && inreg($2)==reg_pointer
1675 call lollilxxxstl(OR_I)
1677 proc lollfixxxstl example lol LLP lof adi stl
1678 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1679 gen xxx* {offsetted_int, regvar($2, reg_pointer), $3}, {LOCAL, $1}
1681 pat lol LLP lof adi stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
1682 && inreg($2)==reg_pointer
1683 call lollfixxxstl(ADD_I)
1684 pat lol LLP lof adu stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
1685 && inreg($2)==reg_pointer
1686 call lollfixxxstl(ADD_I)
1687 pat lol LLP lof sbi stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
1688 && inreg($2)==reg_pointer
1689 call lollfixxxstl(SUB_I)
1690 pat lol LLP lof sbu stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
1691 && inreg($2)==reg_pointer
1692 call lollfixxxstl(SUB_I)
1693 pat lol LLP lof and stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
1694 && inreg($2)==reg_pointer
1695 call lollfixxxstl(AND_I)
1696 pat lol LLP lof ior stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
1697 && inreg($2)==reg_pointer
1698 call lollfixxxstl(OR_I)
1701 proc lolfrxlolf example LLP lof and LLP stf
1702 with conreg_int-bconst
1704 gen xxx* %1, {offsetted_int, regvar($1, reg_pointer), $2}
1706 pat LLP lof adi LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1707 && inreg($1)==reg_pointer
1708 call lolfrxlolf(ADD_I)
1709 pat LLP lof adu LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1710 && inreg($1)==reg_pointer
1711 call lolfrxlolf(ADD_I)
1712 pat LLP lof and LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1713 && inreg($1)==reg_pointer
1714 call lolfrxlolf(AND_I)
1715 pat LLP lof ior LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1716 && inreg($1)==reg_pointer
1717 call lolfrxlolf(OR_I)
1718 pat LLP lof xor LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1719 && inreg($1)==reg_pointer
1720 call lolfrxlolf(EOR_I)
1722 pat LLP lof ads LLP stf $1==$4 && $2==$5 && $3==4
1723 && inreg($1)==reg_pointer
1724 call lolfrxlolf("add.l")
1727 proc lolfxxlolf example LLP lof and LLP stf
1728 with conreg_int-bconst
1730 #if TBL68020 && FANCY_MODES
1731 gen xxx* %1, {OFF_off_int, lb, $1, $2}
1733 uses AA_REG={DLOCAL, $1}
1734 gen xxx* %1, {offsetted_int, %a, $2}
1737 pat LLP lof adi LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1738 call lolfxxlolf(ADD_I)
1739 pat LLP lof adu LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1740 call lolfxxlolf(ADD_I)
1741 pat LLP lof and LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1742 call lolfxxlolf(AND_I)
1743 pat LLP lof ior LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1744 call lolfxxlolf(OR_I)
1745 pat LLP lof xor LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1746 call lolfxxlolf(EOR_I)
1748 pat LLP lof ads LLP stf $1==$4 && $2==$5 && $3==4
1749 call lolfxxlolf("add.l")
1753 proc lilfxxlilf example lil lof and lil stf
1754 with conreg_int-bconst
1756 #if TBL68020 && FANCY_MODES
1757 gen xxx* %1, {OFF_off4, regvar($1, reg_pointer), 0, $2}
1759 uses AA_REG={indirect4, regvar($1, reg_pointer)}
1760 gen xxx* %1, {offsetted_int, %a, $2}
1763 pat lil lof adi lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
1764 call lilfxxlilf("add.l")
1765 pat lil lof adu lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
1766 call lilfxxlilf("add.l")
1767 pat lil lof and lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
1768 call lilfxxlilf("and.l")
1769 pat lil lof ior lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
1770 call lilfxxlilf("or.l")
1771 pat lil lof xor lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
1772 call lilfxxlilf("eor.l")
1773 pat lil lof ads lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
1774 call lilfxxlilf("add.l")
1777 proc lefxxxsef example loe lof and loe stf
1778 with conreg_int-bconst
1780 #if TBL68020 && FANCY_MODES
1781 gen xxx* %1, {ABS_off_int, $1, $2}
1783 uses AA_REG={absolute4, $1}
1784 gen xxx* %1, {offsetted_int, %a, $2}
1787 pat LEP lof adi LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1788 call lefxxxsef(ADD_I)
1789 pat LEP lof adu LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1790 call lefxxxsef(ADD_I)
1791 pat LEP lof and LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1792 call lefxxxsef(AND_I)
1793 pat LEP lof ior LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1794 call lefxxxsef(OR_I)
1795 pat LEP lof xor LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1796 call lefxxxsef(EOR_I)
1798 pat LEP lof ads LEP stf $1==$4 && $2==$5 && $3==4
1799 call lefxxxsef("add.l")
1802 /* lil gets a word, not necessarily a pointer */
1804 proc lilixxlili example lil loi and lil sti
1805 with conreg_int-bconst
1807 #if TBL68020 && FANCY_MODES
1808 gen xxx* %1, {OFF_off4, regvar($1, reg_pointer), 0, 0}
1810 uses AA_REG={indirect4, regvar($1, reg_pointer)}
1811 gen xxx* %1, {indirect4, %a}
1814 pat lil loi adi lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
1815 && inreg($1)==reg_pointer
1816 call lilixxlili("add.l")
1817 pat lil loi adu lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
1818 && inreg($1)==reg_pointer
1819 call lilixxlili("add.l")
1820 pat lil loi and lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
1821 && inreg($1)==reg_pointer
1822 call lilixxlili("and.l")
1823 pat lil loi ior lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
1824 && inreg($1)==reg_pointer
1825 call lilixxlili("or.l")
1826 pat lil loi xor lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
1827 && inreg($1)==reg_pointer
1828 call lilixxlili("eor.l")
1829 pat lil loi ads lil sti $1==$4 && $2==$3 && $2==$5 && $3==4
1830 && inreg($1)==reg_pointer
1831 call lilixxlili("add.l")
1834 proc leixxxsei example loe loi and loe sti
1835 with conreg_int-bconst
1837 #if TBL68020 && FANCY_MODES
1838 gen xxx* %1, {ABS_off_int, $1, 0}
1840 uses AA_REG={absolute4, $1}
1841 gen xxx* %1, {indirect_int, %a}
1844 pat LEP loi adi LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
1845 call leixxxsei(ADD_I)
1846 pat LEP loi adu LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
1847 call leixxxsei(ADD_I)
1848 pat LEP loi and LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
1849 call leixxxsei(AND_I)
1850 pat LEP loi ior LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
1851 call leixxxsei(OR_I)
1852 pat LEP loi xor LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
1853 call leixxxsei(EOR_I)
1855 pat LEP loi ads LEP sti $1==$4 && $2==$3 && $2==$5 && $2==4
1856 call leixxxsei("add.l")
1859 proc lofruxxsof example LLP lof inc LLP stf
1861 gen bit* {offsetted_int, regvar($1, reg_pointer), $2}
1863 pat LLP lof inc LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
1864 call lofruxxsof(INC)
1865 pat LLP lof dec LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
1866 call lofruxxsof(DEC)
1867 pat LLP lof ngi LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
1869 call lofruxxsof(NEG_I)
1870 pat LLP lof com LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
1872 call lofruxxsof(NOT_I)
1874 proc lofuxxsof example LLP lof inc LLP stf
1876 #if TBL68020 && FANCY_MODES
1877 gen bit* {OFF_off_int, lb, $1, $2}
1879 uses AA_REG={DLOCAL,$1}
1880 gen bit* {offsetted_int,%a,$2}
1883 pat LLP lof inc LLP stf $1==$4 && $2==$5
1885 pat LLP lof dec LLP stf $1==$4 && $2==$5
1887 pat LLP lof ngi LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1888 call lofuxxsof(NEG_I)
1889 pat LLP lof com LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
1890 call lofuxxsof(NOT_I)
1893 proc lifuxxsif example lil lof inc lil stf
1895 #if TBL68020 && FANCY_MODES
1896 gen bit* {OFF_off4, regvar($1, reg_pointer), 0, $2}
1898 uses AA_REG={indirect4, regvar($1, reg_pointer)}
1899 gen bit* {offsetted4,%a,$2}
1902 pat lil lof inc lil stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
1903 call lifuxxsif("add.l #1,")
1904 pat lil lof dec lil stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
1905 call lifuxxsif("sub.l #1,")
1906 pat lil lof ngi lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
1907 call lifuxxsif("neg.l")
1908 pat lil lof com lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
1909 call lifuxxsif("not.l")
1913 proc liiuxxsii example lil loi inc lil sti
1915 #if TBL68020 && FANCY_MODES
1916 gen bit* {OFF_off4, regvar($1, reg_pointer), 0, 0}
1918 uses AA_REG={indirect4, regvar($1, reg_pointer)}
1919 gen bit* {indirect4, %a}
1922 pat lil loi inc lil sti $1==$4 && $2==4 && $5==4 && inreg($1)==reg_pointer
1923 call liiuxxsii("add.l #1,")
1924 pat lil loi dec lil sti $1==$4 && $2==4 && $5==4 && inreg($1)==reg_pointer
1925 call liiuxxsii("sub.l #1,")
1926 pat lil loi ngi lil sti $1==$4 && $2==4 && $5==4 && $3==4 && inreg($1)==reg_pointer
1927 call liiuxxsii("neg.l")
1928 pat lil loi com lil sti $1==$4 && $2==4 && $5==4 && $3==4 && inreg($1)==reg_pointer
1929 call liiuxxsii("not.l")
1932 proc lefuxxsef example loe lof inc loe stf
1934 #if TBL68020 && FANCY_MODES
1935 gen bit* {ABS_off_int, $1, $2}
1937 uses AA_REG={absolute4, $1}
1938 gen bit* {offsetted_int, %a, $2}
1941 pat LEP lof inc LEP stf $1==$4 && $2==$5
1943 pat LEP lof dec LEP stf $1==$4 && $2==$5
1945 pat LEP lof ngi LEP stf $1==$4 && $2==$5 && $3==4
1946 call lefuxxsef(NEG_I)
1947 pat LEP lof com LEP stf $1==$4 && $2==$5 && $3==4
1948 call lefuxxsef(NOT_I)
1950 proc leiuxxsei example loe loi inc loe sti
1952 #if TBL68020 && FANCY_MODES
1953 gen bit* {ABS_off_int, $1, 0}
1955 uses AA_REG={absolute4, $1}
1956 gen bit* {indirect_int, %a}
1959 pat LEP loi inc LEP sti $1==$4 && $2==$5 && $2==WORD_SIZE
1961 pat LEP loi dec LEP sti $1==$4 && $2==$5 && $2==WORD_SIZE
1963 pat LEP loi ngi LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
1964 call leiuxxsei(NEG_I)
1965 pat LEP loi com LEP sti $1==$4 && $2==$3 && 2==$5 && $2==WORD_SIZE
1966 call leiuxxsei(NOT_I)
1968 proc lolcxxstl example lol loc and stl
1969 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
1970 gen xxx* {const, $2}, {LOCAL, $1}
1973 pat lol loc adi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1974 call lolcxxstl(ADD_I)
1975 pat lol loc adu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1976 call lolcxxstl(ADD_I)
1977 peephole optimizer replaces these
1979 pat lol loc sbi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1980 call lolcxxstl(SUB_I)
1981 pat lol loc sbu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1982 call lolcxxstl(SUB_I)
1984 pat lol loc and stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1985 call lolcxxstl(AND_I)
1986 pat lol loc ior stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1987 call lolcxxstl(OR_I)
1988 pat lol loc xor stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1989 call lolcxxstl(EOR_I)
1990 peephole optimizer replaces these
1992 #if TBL68020 || WORDSIZE==2
1994 pat lol loc dvi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1995 call lolcxxstl(DIVS_I)
1996 pat lol loc dvu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
1997 call lolcxxstl(DIVU_I)
1999 pat lol loc mli stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
2000 call lolcxxstl(MULS_I)
2001 pat lol loc mlu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
2002 call lolcxxstl(MULU_I)
2005 proc lolcxxxstl example lol loc adi stl
2006 kills all_indir, LOCAL %bd==$1
2007 gen xxx* {const, $2}, {LOCAL, $1}
2010 pat lol loc adi stl $1==$4 && $3==WORD_SIZE call lolcxxxstl(ADD_I)
2011 pat lol loc adu stl $1==$4 && $3==WORD_SIZE call lolcxxxstl(ADD_I)
2012 peephole optimizer replaces these
2014 pat lol loc sbi stl $1==$4 && $3==WORD_SIZE call lolcxxxstl(SUB_I)
2015 pat lol loc sbu stl $1==$4 && $3==WORD_SIZE call lolcxxxstl(SUB_I)
2017 pat lol loc and stl $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_pointer
2018 call lolcxxxstl(AND_I)
2019 pat lol loc ior stl $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_pointer
2020 call lolcxxxstl(OR_I)
2021 pat lol loc xor stl $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_pointer
2022 call lolcxxxstl(EOR_I)
2023 peephole optimizer replaces these
2026 proc ldlcxxxsdl example ldl ldc adi sdl
2027 kills all_indir, DLOCAL %bd==$1
2028 gen xxx* {const4, $2}, {DLOCAL, $1}
2030 pat ldl ldc sbi sdl $1==$4 && $3==4 call ldlcxxxsdl("sub.l")
2031 pat ldl ldc sbu sdl $1==$4 && $3==4 call ldlcxxxsdl("sub.l")
2034 proc lilcxxsil example lil loc and sil
2036 gen xxx* {const, $2}, {indirect_int, regvar($1, reg_pointer)}
2038 pat lil loc adi sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
2039 call lilcxxsil(ADD_I)
2040 pat lil loc adu sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
2041 call lilcxxsil(ADD_I)
2042 pat lil loc sbi sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
2043 call lilcxxsil(SUB_I)
2044 pat lil loc sbu sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
2045 call lilcxxsil(SUB_I)
2046 pat lil loc and sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
2047 call lilcxxsil(AND_I)
2048 pat lil loc ior sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
2049 call lilcxxsil(OR_I)
2050 pat lil loc xor sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
2051 call lilcxxsil(EOR_I)
2053 proc lilcxxxsil example lil loc adi sil
2056 gen xxx* {const, $2}, {ILOCAL, $1}
2058 uses AA_REG = {DLOCAL, $1}
2059 gen xxx* {const, $2}, {indirect_int, %a}
2062 pat lil loc adi sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
2063 call lilcxxxsil(ADD_I)
2064 pat lil loc adu sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
2065 call lilcxxxsil(ADD_I)
2066 pat lil loc sbi sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
2067 call lilcxxxsil(SUB_I)
2068 pat lil loc sbu sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
2069 call lilcxxxsil(SUB_I)
2070 pat lil loc and sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
2071 call lilcxxxsil(AND_I)
2072 pat lil loc ior sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
2073 call lilcxxxsil(OR_I)
2074 pat lil loc xor sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
2075 call lilcxxxsil(EOR_I)
2077 proc loecxxxste example loe loc adi ste
2079 gen xxx* {const, $2}, {absolute4, $1}
2082 pat loe loc adi ste $1==$4 && $3==WORD_SIZE call loecxxxste(ADD_I)
2083 pat loe loc adu ste $1==$4 && $3==WORD_SIZE call loecxxxste(ADD_I)
2084 peephole optimizer replaces these
2086 pat loe loc sbi ste $1==$4 && $3==WORD_SIZE call loecxxxste(SUB_I)
2087 pat loe loc sbu ste $1==$4 && $3==WORD_SIZE call loecxxxste(SUB_I)
2089 pat loe loc and ste $1==$4 && $3==WORD_SIZE call loecxxxste(AND_I)
2090 pat loe loc ior ste $1==$4 && $3==WORD_SIZE call loecxxxste(OR_I)
2091 pat loe loc xor ste $1==$4 && $3==WORD_SIZE call loecxxxste(EOR_I)
2092 peephole optimizer replaces these
2095 proc lolrxxstl example lol lol and stl
2096 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
2097 gen xxx* {LOCAL, $2}, {LOCAL, $1}
2100 pat lol lol adi stl $1==$4 && $3==WORD_SIZE
2101 && inreg($1)==reg_any && inreg($2)==reg_any
2102 call lolrxxstl(ADD_I)
2103 pat lol lol adu stl $1==$4 && $3==WORD_SIZE
2104 && inreg($1)==reg_any && inreg($2)==reg_any
2105 call lolrxxstl(ADD_I)
2106 peephole optimizer replaces these
2108 pat lol lol sbi stl $1==$4 && $3==WORD_SIZE
2109 && inreg($1)==reg_any && inreg($2)==reg_any
2110 call lolrxxstl(SUB_I)
2111 pat lol lol sbu stl $1==$4 && $3==WORD_SIZE
2112 && inreg($1)==reg_any && inreg($2)==reg_any
2113 call lolrxxstl(SUB_I)
2115 pat lol lol and stl $1==$4 && $3==WORD_SIZE
2116 && inreg($1)==reg_any && inreg($2)==reg_any
2117 call lolrxxstl(AND_I)
2118 pat lol lol ior stl $1==$4 && $3==WORD_SIZE
2119 && inreg($1)==reg_any && inreg($2)==reg_any
2120 call lolrxxstl(OR_I)
2121 pat lol lol xor stl $1==$4 && $3==WORD_SIZE
2122 && inreg($1)==reg_any && inreg($2)==reg_any
2123 call lolrxxstl(EOR_I)
2124 peephole optimizer replaces these
2127 proc lolrxxxstl example lol lol adi stl
2128 kills all_indir, LOCAL %bd==$1
2129 gen xxx* {LOCAL, $2}, {LOCAL, $1}
2132 pat lol lol adi stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2133 call lolrxxxstl(ADD_I)
2134 pat lol lol adu stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2135 call lolrxxxstl(ADD_I)
2136 peephole optimizer replaces these
2139 pat lol lol ads stl $1==$4 && $3==4 && inreg($2)==reg_any
2140 call lolrxxxstl("add.l")
2142 pat lol lol sbi stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2143 call lolrxxxstl(SUB_I)
2144 pat lol lol sbu stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2145 call lolrxxxstl(SUB_I)
2147 pat lol lol and stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any && inreg($1)!=reg_pointer
2148 call lolrxxxstl(AND_I)
2149 pat lol lol ior stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any &&
2150 inreg($1)!=reg_pointer
2151 call lolrxxxstl(OR_I)
2152 pat lol lol xor stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any &&
2153 inreg($1)!=reg_pointer
2154 call lolrxxxstl(EOR_I)
2155 peephole optimizer replaces these
2158 proc lilrxxsil example lil lol and sil
2160 gen xxx* {LOCAL, $2}, {indirect_int, regvar($1, reg_pointer)}
2162 pat lil lol adi sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
2164 call lilrxxsil(ADD_I)
2165 pat lil lol adu sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
2167 call lilrxxsil(ADD_I)
2168 pat lil lol sbi sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
2170 call lilrxxsil(SUB_I)
2171 pat lil lol sbu sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
2173 call lilrxxsil(SUB_I)
2174 pat lil lol and sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
2176 call lilrxxsil(AND_I)
2177 pat lil lol ior sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
2179 call lilrxxsil(OR_I)
2180 pat lil lol xor sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
2182 call lilrxxsil(EOR_I)
2184 pat lil lol ads sil $1==$4 && $3==4 && inreg($1)==reg_pointer &&
2186 call lilrxxsil("add.l")
2189 proc lilrxxxsil example lil lol adi sil
2192 gen xxx* {LOCAL, $2}, {ILOCAL, $1}
2194 uses AA_REG = {DLOCAL, $1}
2195 gen xxx* {LOCAL, $2}, {indirect_int, %a}
2198 pat lil lol adi sil $1==$4 && $3==WORD_SIZE
2199 && inreg($2)==reg_any && inreg($1)!=reg_any
2200 call lilrxxxsil(ADD_I)
2201 pat lil lol adu sil $1==$4 && $3==WORD_SIZE
2202 && inreg($2)==reg_any && inreg($1)!=reg_any
2203 call lilrxxxsil(ADD_I)
2204 pat lil lol sbi sil $1==$4 && $3==WORD_SIZE
2205 && inreg($2)==reg_any && inreg($1)!=reg_any
2206 call lilrxxxsil(SUB_I)
2207 pat lil lol sbu sil $1==$4 && $3==WORD_SIZE
2208 && inreg($2)==reg_any && inreg($1)!=reg_any
2209 call lilrxxxsil(SUB_I)
2210 pat lil lol and sil $1==$4 && $3==WORD_SIZE
2211 && inreg($2)==reg_any && inreg($1)!=reg_any
2212 call lilrxxxsil(AND_I)
2213 pat lil lol ior sil $1==$4 && $3==WORD_SIZE
2214 && inreg($2)==reg_any && inreg($1)!=reg_any
2215 call lilrxxxsil(OR_I)
2216 pat lil lol xor sil $1==$4 && $3==WORD_SIZE
2217 && inreg($2)==reg_any && inreg($1)!=reg_any
2218 call lilrxxxsil(EOR_I)
2220 pat lil lol ads sil $1==$4 && $3==4 && inreg($2)==reg_any && inreg($1)!=reg_any
2221 call lilrxxxsil("add.l")
2224 proc loerxxxste example loe lol adi ste
2226 gen xxx* {LOCAL, $2}, {absolute_int, $1}
2228 pat loe lol adi ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2229 call loerxxxste(ADD_I)
2230 pat loe lol adu ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2231 call loerxxxste(ADD_I)
2232 pat loe lol sbi ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2233 call loerxxxste(SUB_I)
2234 pat loe lol sbu ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2235 call loerxxxste(SUB_I)
2236 pat loe lol and ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2237 call loerxxxste(AND_I)
2238 pat loe lol ior ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2239 call loerxxxste(OR_I)
2240 pat loe lol xor ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
2241 call loerxxxste(EOR_I)
2243 pat loe lol ads ste $1==$4 && $3==4 && inreg($2)==reg_any
2244 call loerxxxste("add.l")
2247 proc xxxstl example adi stl
2248 with any_int-RD_REG-dreg_int any-RD_REG-dreg_int
2249 kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
2250 gen move %2,{dreg_int, regvar($2)}
2252 with exact any_int-RD_REG-dreg_int STACK
2253 kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
2254 gen move_i {post_inc_int, sp}, {dreg_int, regvar($2)}
2257 pat adi stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(ADD_I)
2258 pat adu stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(ADD_I)
2259 pat sbi stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(SUB_I)
2260 pat sbu stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(SUB_I)
2261 pat and stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(AND_I)
2262 pat ior stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(OR_I)
2264 pat xor stl $1==WORD_SIZE && inreg($2)==reg_any
2266 kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
2267 gen move %2,{dreg_int, regvar($2)}
2268 eor_i %1,{dreg_int, regvar($2)}
2270 pat ads SLP $1==4 && inreg($2)==reg_pointer
2271 with any4-areg-RA_REG any4+address-areg-RA_REG
2272 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2273 gen move %2,{areg,regvar($2,reg_pointer)}
2274 add_l %1,{areg,regvar($2,reg_pointer)}
2276 with regX any4+address-areg-RA_REG
2277 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2278 gen move %2,{areg,regvar($2,reg_pointer)}
2279 move {regAregXcon, regvar($2,reg_pointer), %1.xreg, %1.sc, 0},{areg,regvar($2,reg_pointer)}
2280 with exact regX STACK
2281 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2282 gen move_l {post_inc4, sp},{areg,regvar($2,reg_pointer)}
2283 move {regAregXcon, regvar($2,reg_pointer), %1.xreg, %1.sc, 0},{areg,regvar($2,reg_pointer)}
2284 with exact regX regAcon
2285 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2286 gen move {regAregXcon, %2.reg, %1.xreg, %1.sc, %2.bd},{areg,regvar($2,reg_pointer)}
2287 with exact regX local_addr
2288 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2289 gen move {regAregXcon, lb, %1.xreg, %1.sc, %2.bd},{areg,regvar($2,reg_pointer)}
2291 with exact regX indirect4
2292 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2293 gen move {off_regXcon, %2.reg, %1.xreg,%1.sc,0,0},{areg,regvar($2,reg_pointer)}
2294 with exact regX offsetted4
2295 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2296 gen move {off_regXcon, %2.reg, %1.xreg, %1.sc, %2.bd, 0},{areg,regvar($2,reg_pointer)}
2297 with exact regX LOCAL
2298 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2299 gen move {off_regXcon, lb, %1.xreg, %1.sc, %2.bd, 0},{areg,regvar($2,reg_pointer)}
2300 with exact regX off_con
2301 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2302 gen move {off_regXcon, %2.reg, %1.xreg,%1.sc,%2.bd,%2.od},{areg,regvar($2,reg_pointer)}
2303 with exact regX ext_addr
2304 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2305 gen move{ext_regX, %1.sc, %1.xreg, %2.bd},{areg,regvar($2,reg_pointer)}
2306 with exact regX absolute4
2307 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2308 gen move {abs_regXcon, %1.sc, %1.xreg, %2.bd, 0},{areg,regvar($2,reg_pointer)}
2309 with exact regX abs_con
2310 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2311 gen move {abs_regXcon, %1.sc, %1.xreg, %2.bd, %2.od},{areg,regvar($2,reg_pointer)}
2312 with exact indirect4 ext_addr
2313 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2314 gen move {off_con, %1.reg, 0, %2.bd},{areg,regvar($2,reg_pointer)}
2315 with exact offsetted4 ext_addr
2316 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2317 gen move {off_con, %1.reg, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
2318 with exact LOCAL ext_addr
2319 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2320 gen move {off_con, lb, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
2321 with exact index_off4 ext_addr
2322 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2323 gen move {indoff_con, %1.reg, %1.xreg, %1.sc,%1.bd,%2.bd},{areg,regvar($2,reg_pointer)}
2324 with exact absolute4 ext_addr
2325 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2326 gen move {abs_con, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
2327 with exact abs_index4 ext_addr
2328 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2329 gen move {absind_con, %1.sc, %1.xreg, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
2330 with exact indirect4 ext_regX
2331 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2332 gen move {off_regXcon, %1.reg, %2.xreg, %2.sc, 0, %2.bd},{areg,regvar($2,reg_pointer)}
2333 with exact offsetted4 ext_regX
2334 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2335 gen move {off_regXcon, %1.reg, %2.xreg,%2.sc,%1.bd,%2.bd},{areg,regvar($2,reg_pointer)}
2336 with exact LOCAL ext_regX
2337 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2338 gen move {off_regXcon, lb, %2.xreg, %2.sc, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
2339 with exact absolute4 ext_regX
2340 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2341 gen move {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
2342 #endif /* FANCY_MODES */
2343 #endif /* TBL68020 */
2346 proc xxxdupstl example adi dup stl
2347 with any_int-RD_REG-dreg_int any-RD_REG-dreg_int
2348 kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
2349 gen move %2,{dreg_int, regvar($3)}
2350 xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
2351 with exact any_int-RD_REG-dreg_int STACK
2352 kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
2353 gen move_i {post_inc_int, sp}, {dreg_int, regvar($3)}
2354 xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
2356 pat adi dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
2357 call xxxdupstl(ADD_I)
2358 pat adu dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
2359 call xxxdupstl(ADD_I)
2360 pat sbi dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
2361 call xxxdupstl(SUB_I)
2362 pat sbu dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
2363 call xxxdupstl(SUB_I)
2364 pat and dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
2365 call xxxdupstl(AND_I)
2366 pat ior dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
2367 call xxxdupstl(OR_I)
2369 pat xor dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
2370 call xxxdupstl(EOR_I)
2371 incorrect for eor.l !!!
2374 pat dup stl $1==WORD_SIZE && inreg($2)==reg_any
2376 kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
2377 gen move %1,{dreg_int, regvar($2,reg_any)}
2380 pat dup stl $1==4 && inreg($2)==reg_pointer
2382 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2383 gen move_l %1,{areg, regvar($2, reg_pointer)}
2386 pat dup LLP sti LLP adp SLP zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
2387 $2==$4 && $2==$6 && $3==1 && $5==1
2389 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2390 gen move_b %1,{post_inc1, regvar($2,reg_pointer)}
2393 pat dup LLP sti LLP adp SLP zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
2394 $2==$4 && $2==$6 && $3==1 && $5==1
2396 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2397 gen move_b %1,{post_inc1, regvar($2,reg_pointer)}
2400 /* Normally, LLP sti wth word size will be optimized to sil */
2401 pat dup LLP sti LLP adp SLP zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
2402 $2==$4 && $2==$6 && $3==2 && $5==2
2404 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2405 gen move_w %1,{post_inc2, regvar($2,reg_pointer)}
2408 pat dup LLP sti LLP adp SLP zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
2409 $2==$4 && $2==$6 && $3==2 && $5==2
2411 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2412 gen move_w %1,{post_inc2, regvar($2,reg_pointer)}
2416 /* m68k2 can't do zne/zeq on 4-byte */
2417 pat dup LLP sti LLP adp SLP zne $1==4 && inreg($2)==reg_pointer &&
2418 $2==$4 && $2==$6 && $3==4 && $5==4
2420 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2421 gen move_l %1,{post_inc4, regvar($2,reg_pointer)}
2424 pat dup LLP sti LLP adp SLP zeq $1==4 && inreg($2)==reg_pointer &&
2425 $2==$4 && $2==$6 && $3==4 && $5==4
2427 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2428 gen move_l %1,{post_inc4, regvar($2,reg_pointer)}
2432 pat dup sil LLP adp SLP zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
2433 $2==$3 && $3==$5 && $4==WORD_SIZE
2435 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2436 gen move_i %1,{post_inc_int, regvar($2, reg_pointer)}
2439 pat dup sil LLP adp SLP zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
2440 $2==$3 && $3==$5 && $4==WORD_SIZE
2442 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2443 gen move_i %1,{post_inc_int, regvar($2, reg_pointer)}
2446 pat sil lil LLP adp SLP zne $1==$2 && $2==$3 && $3==$5 && $4==WORD_SIZE
2447 && inreg($1)==reg_pointer
2449 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2450 gen move_i %1,{post_inc_int, regvar($1,reg_pointer)}
2453 pat sil lil LLP adp SLP zeq $1==$2 && $2==$3 && $3==$5 && $4==WORD_SIZE
2454 && inreg($1)==reg_pointer
2456 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2457 gen move_i %1,{post_inc_int, regvar($1,reg_pointer)}
2460 pat dup LLP adp SLP LLP sti zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
2461 $2==$4 && $4==$5 && $6==1 && $4==(0-1)
2463 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2464 gen move_b %1,{pre_dec1, regvar($2,reg_pointer)}
2467 pat dup LLP adp SLP LLP sti zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
2468 $2==$4 && $4==$5 && $6==1 && $4==(0-1)
2470 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2471 gen move_b %1,{pre_dec1, regvar($2,reg_pointer)}
2475 pat dup LLP adp SLP LLP sti zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
2476 $2==$4 && $4==$5 && $6==2 && $4==(0-2)
2478 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2479 gen move_w %1,{pre_dec2, regvar($2,reg_pointer)}
2482 pat dup LLP adp SLP LLP sti zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
2483 $2==$4 && $4==$5 && $6==2 && $4==(0-2)
2485 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2486 gen move_w %1,{pre_dec2, regvar($2,reg_pointer)}
2491 pat dup lol adp stl lol sti zne $1==4 && inreg($2)==reg_pointer &&
2492 $2==$4 && $4==$5 && $6==4 && $4==(0-4)
2494 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2495 gen move_l %1,{pre_dec4, regvar($2,reg_pointer)}
2498 pat dup lol adp stl lol sti zeq $1==4 && inreg($2)==reg_pointer &&
2499 $2==$4 && $4==$5 && $6==4 && $4==(0-4)
2501 kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
2502 gen move_l %1,{pre_dec4, regvar($2,reg_pointer)}
2506 pat LLP ads SLP $1==$3 && $2==4 && inreg($1)==reg_pointer
2508 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2509 gen add_l %1, {DLOCAL, $1}
2511 pat lil dup inc sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
2513 uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
2514 gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
2518 pat lil dup dec sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
2520 uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
2521 gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
2525 pat LLP LFP dup adp LLP SFP sti $3==4 && $1==$5 && $2==$6 && inreg($1)==reg_pointer && $7 <= 4
2528 uses AA_REG = {offsetted4, regvar($1, reg_pointer), $2}
2529 gen add_l {const4, $4}, {offsetted4, regvar($1, reg_pointer), $2}
2531 yields %1 %a leaving sti $7
2533 pat LLP LFP dup adp LLP SFP $3==4 && $1==$5 && $2==$6 && inreg($1)==reg_pointer
2535 uses AA_REG = {offsetted4, regvar($1, reg_pointer), $2}
2536 gen add_l {const4, $4}, {offsetted4, regvar($1, reg_pointer), $2}
2540 pat LLP LFP dup adp LLP SFP sti $3==4 && $1==$5 && $2==$6 && $7 <= 4
2543 uses AA_REG = {DLOCAL, $1}, AA_REG
2544 gen move_l {offsetted4, %a, $2}, %b
2545 add_l {const4, $4}, {offsetted4, %a, $2}
2546 yields %1 %b leaving sti $7
2548 pat LLP LFP dup adp LLP SFP $3==4 && $1==$5 && $2==$6
2550 uses AA_REG = {DLOCAL, $1}, AA_REG
2551 gen move_l {offsetted4, %a, $2}, %b
2552 add_l {const4, $4}, {offsetted4, %a, $2}
2555 pat LEP LFP dup adp LEP SFP sti $3==4 && $1==$5 && $2==$6 && $7 <= 4
2558 uses AA_REG = {absolute4, $1}, AA_REG
2559 gen move_l {offsetted4, %a, $2}, %b
2560 add_l {const4, $4}, {offsetted4, %a, $2}
2561 yields %1 %b leaving sti $7
2563 pat LEP LFP dup adp LEP SFP $3==4 && $1==$5 && $2==$6
2565 uses AA_REG = {absolute4, $1}, AA_REG
2566 gen move_l {offsetted4, %a, $2}, %b
2567 add_l {const4, $4}, {offsetted4, %a, $2}
2571 pat lil lof dup adp lil stf sti $3==4 && $1==$5 && $2==$6 && inreg($1)==reg_pointer && $7 <= 4
2574 uses AA_REG = {indirect4, regvar($1, reg_pointer)}, AA_REG
2575 gen move_l {offsetted4, %a, $2}, %b
2576 add_l {const4, $4}, {offsetted4, %a, $2}
2577 yields %1 %b leaving sti $7
2579 pat lil lof dup adp lil stf $3==4 && $1==$5 && $2==$6 && inreg($1)==reg_pointer
2581 uses AA_REG = {indirect4, regvar($1, reg_pointer)}, AA_REG
2582 gen move_l {offsetted4, %a, $2}, %b
2583 add_l {const4, $4}, {offsetted4, %a, $2}
2585 #endif /* WORD_SIZE==2 */
2587 pat LEP loi dup adp LEP sti sti $3==4 && $1==$5 && $2==4 && $6==4 && $7 <= 4
2590 uses AA_REG = {absolute4, $1}, AA_REG
2591 gen move_l {indirect4, %a}, %b
2592 add_l {const4, $4}, {indirect4, %a}
2593 yields %1 %b leaving sti $7
2595 pat LEP loi dup adp LEP sti $3==4 && $1==$5 && $2==4 && $6==4
2597 uses AA_REG = {absolute4, $1}, AA_REG
2598 gen move_l {indirect4, %a}, %b
2599 add_l {const4, $4}, {indirect4, %a}
2603 pat lil loi dup adp lil sti sti $3==4 && $1==$5 && $2==4 && $6==4 && $7 <= 4
2606 uses AA_REG = {indirect4, regvar($1, reg_pointer)}, AA_REG
2607 gen move_l {indirect4, %a}, %b
2608 add_l {const4, $4}, {indirect4, %a}
2609 yields %1 %b leaving sti $7
2611 pat lil loi dup adp lil sti $3==4 && $1==$5 && $2==4 && $6==4
2613 uses AA_REG = {indirect4, regvar($1, reg_pointer)}, AA_REG
2614 gen move_l {indirect4, %a}, %b
2615 add_l {const4, $4}, {indirect4, %a}
2619 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 < 0
2620 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2621 gen sub_l {const4,0-$3},{DLOCAL,$1}
2622 yields {DLOCAL,$1} {ext_addr, $5+$3}
2625 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 > 0
2626 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2627 gen add_l {const4,$3},{DLOCAL,$1}
2628 yields {DLOCAL,$1} {ext_addr, $5+$3}
2631 pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==4 && $5==4 &&
2632 inreg($1)==reg_pointer
2633 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2634 yields {post_inc4, regvar($1, reg_pointer)}
2636 pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
2637 leaving LLP $1 loi $5 LLP $4 adp $3 SLP $4
2639 pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
2640 inreg($1)==reg_pointer
2641 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2642 yields {post_inc1, regvar($1, reg_pointer)}
2644 /* Normally, LLP loi will be optimized to lil */
2645 pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==2 && $4==2 &&
2646 inreg($1)==reg_pointer
2647 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2648 yields {post_inc2, regvar($1, reg_pointer)}
2650 pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==4 && $4==4 &&
2651 inreg($1)==reg_pointer
2652 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2653 yields {post_inc4, regvar($1, reg_pointer)}
2655 pat lil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
2656 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2657 yields {post_inc_int, regvar($1, reg_pointer)}
2659 pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
2660 leaving LLP $1 sti $5 LLP $4 adp $3 SLP $4
2662 pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
2663 inreg($1)==reg_pointer
2665 kills allexceptcon, regvar($1, reg_pointer)
2666 gen move %1, {post_inc1, regvar($1, reg_pointer)}
2668 /* Normally, LLP sti will ve optimzed into sil */
2669 pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==2 && $4==2 &&
2670 inreg($1)==reg_pointer
2672 kills allexceptcon, regvar($1, reg_pointer)
2673 gen move %1, {post_inc2, regvar($1, reg_pointer)}
2675 pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==4 && $4==4 &&
2676 inreg($1)==reg_pointer
2678 kills allexceptcon, regvar($1, reg_pointer)
2679 gen move %1, {post_inc4, regvar($1, reg_pointer)}
2681 pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==WORD_SIZE && $5==WORD_SIZE &&
2682 inreg($1)==reg_pointer
2683 with any_int-sconsts
2684 kills allexceptcon, regvar($1, reg_pointer)
2685 gen move %1, {post_inc_int, regvar($1, reg_pointer)}
2687 pat sil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
2688 with any_int-sconsts
2689 kills allexceptcon, regvar($1, reg_pointer)
2690 gen move %1, {post_inc_int, regvar($1, reg_pointer)}
2692 pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
2693 inreg($1)==reg_pointer
2694 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2695 yields {pre_dec1, regvar($1, reg_pointer)}
2697 /* Normally, LLP loi will be optimized to lil */
2698 pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-2 && $5==2 &&
2699 inreg($1)==reg_pointer
2700 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2701 yields {pre_dec2, regvar($1, reg_pointer)}
2703 pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-4 && $5==4 &&
2704 inreg($1)==reg_pointer
2705 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2706 yields {pre_dec4, regvar($1, reg_pointer)}
2708 pat LLP adp SLP lil $1==$3 && $1==$4 && $2==0-WORD_SIZE &&
2709 inreg($1)==reg_pointer
2710 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2711 yields {pre_dec_int, regvar($1, reg_pointer)}
2713 pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
2714 inreg($1)==reg_pointer
2716 kills allexceptcon, regvar($1, reg_pointer)
2717 gen move %1, {pre_dec1, regvar($1, reg_pointer)}
2720 pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-2 && $5==2 &&
2721 inreg($1)==reg_pointer
2723 kills allexceptcon, regvar($1, reg_pointer)
2724 gen move %1, {pre_dec2, regvar($1, reg_pointer)}
2726 pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-4 && $5==4 &&
2727 inreg($1)==reg_pointer
2729 kills allexceptcon, regvar($1, reg_pointer)
2730 gen move %1, {pre_dec4, regvar($1, reg_pointer)}
2733 pat LLP adp SLP sil $1==$3 && $1==$4 && $2==0-WORD_SIZE &&
2734 inreg($1)==reg_pointer
2735 with any_int-sconsts
2736 kills allexceptcon, regvar($1, reg_pointer)
2737 gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
2739 pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directadd($3)
2740 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2741 uses AA_REG = {DLOCAL, $1}
2742 gen add_l {const4, $3}, {DLOCAL, $1}
2746 pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directsub($3)
2747 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2748 uses AA_REG = {DLOCAL, $1}
2749 gen sub_l {const4, 0-$3}, {DLOCAL, $1}
2753 pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer
2754 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2755 uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
2756 gen add_l %b, {DLOCAL, $1}
2760 pat LLP dup adp SLP $1==$4 && $2==4 && directadd($3)
2761 kills all_indir, DLOCAL %bd==$1
2762 uses AA_REG = {DLOCAL, $1}
2763 gen add_l {const4, $3}, {DLOCAL, $1}
2767 pat LLP dup adp SLP $1==$4 && $2==4 && directsub($3)
2768 kills all_indir, DLOCAL %bd==$1
2769 uses AA_REG = {DLOCAL, $1}
2770 gen sub_l {const4, 0-$3}, {DLOCAL, $1}
2774 pat LLP dup adp SLP $1==$4 && $2==4
2775 kills all_indir, DLOCAL %bd==$1
2776 uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
2777 gen add_l %b, {DLOCAL, $1}
2781 pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directadd($2)
2782 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2783 gen add_l {const4, $2}, {DLOCAL, $1}
2785 pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directsub($2)
2786 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2787 gen sub_l {const4, 0-$2}, {DLOCAL, $1}
2789 pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer
2790 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
2791 uses DD_REG4 = {const4, $2}
2792 gen add_l %a, {DLOCAL, $1}
2794 pat LLP adp SLP $1==$3 && directadd($2)
2795 kills all_indir, DLOCAL %bd==$1
2796 gen add_l {const4, $2}, {DLOCAL, $1}
2798 pat LLP adp SLP $1==$3 && directsub($2)
2799 kills all_indir, DLOCAL %bd==$1
2800 gen sub_l {const4, 0-$2}, {DLOCAL, $1}
2802 pat LLP adp SLP $1==$3
2803 kills all_indir, DLOCAL %bd==$1
2804 uses DD_REG4 = {const4, $2}
2805 gen add_l %a, {DLOCAL, $1}
2808 pat lil dup adp sil sti $1==$4 && $2==4 && inreg($1)==reg_pointer && $5<=4
2811 uses AA_REG = {indirect4, regvar($1, reg_pointer)}
2812 gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)}
2814 yields %1 %a leaving sti $5
2816 pat lil dup adp sil $1==$4 && $2==4 && inreg($1)==reg_pointer
2818 uses AA_REG = {indirect4, regvar($1, reg_pointer)}
2819 gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)}
2823 pat lil dup adp sil $1==$4 && $2==4
2825 uses AA_REG, AA_REG = {LOCAL, $1}
2826 gen move {indirect4, %b}, %a
2827 add_l {const, $3}, {indirect4, %b}
2831 pat lil adp sil $1==$3 && inreg($1)==reg_pointer
2833 gen add_l {const, $2}, {indirect4, regvar($1, reg_pointer)}
2835 pat lil adp sil $1==$3 && inreg($1)!=reg_any
2837 #if TBL68020 /* WORD_SIZE==4 */
2838 gen add_l {const, $2}, {ILOCAL,$1}
2840 uses AA_REG = {LOCAL, $1}
2841 gen add_l {const, $2}, {indirect4, %a}
2843 #endif /* WORD_SIZE==2 */
2845 pat LEP dup adp SEP $1==$4 && $2==4
2847 uses AA_REG = {absolute4, $1}
2848 gen add_l {const4, $3}, {absolute4, $1}
2852 pat LEP adp SEP $1==$3
2854 gen add_l {const4, $2}, {absolute4, $1}
2856 pat loc and $1==255 && $2==WORD_SIZE
2858 with exact absolute_int yields {absolute1,%1.bd+1}
2859 with exact offsetted_int yields {offsetted1,%1.reg,%1.bd+1}
2860 with exact LOCAL yields {offsetted1,lb,%1.bd+1}
2862 with exact absolute_int yields {absolute1,%1.bd+3}
2863 with exact offsetted_int yields {offsetted1,%1.reg,%1.bd+3}
2864 with exact LOCAL yields {offsetted1,lb,%1.bd+3}
2866 with yields {const, $1} leaving and WORD_SIZE
2868 /************************************************
2869 * Group 1: load instructions *
2870 ************************************************/
2872 pat loc $1==0 yields {zero_const, $1}
2874 pat loc small($1) yields {small_const, $1}
2876 pat loc in_1($1) yields {bconst, $1}
2878 pat loc yields {const, $1}
2881 pat ldc leaving loc 18 trp
2883 pat ldc highw($1)==0 && loww($1)==0 yields {zero_const4, 0}
2885 pat ldc highw($1)==0 && small(loww($1)) yields {small_const4, loww($1)}
2887 pat ldc highw($1)==0 && in_1(loww($1)) yields {bconst4, loww($1)}
2889 pat ldc yields {const4, $1}
2892 pat LLP inreg($1)==reg_pointer
2893 kills pre_post %reg==regvar($1, reg_pointer)
2896 pat lol yields {LOCAL, $1}
2899 pat ldl leaving lol $1+4 lol $1
2901 pat ldl yields {DLOCAL, $1}
2904 pat loe yields {absolute_int, $1}
2906 /* replace ste loe by dup ste, but not if followed by a test ... */
2907 proc steloezxx example ste loe zne
2908 with any_int-sconsts
2910 gen move_i %1, {absolute_int, $1}
2914 gen move_i {post_inc_int, sp}, {absolute_int, $1}
2917 pat ste loe zlt $1==$2 call steloezxx("blt")
2918 pat ste loe zle $1==$2 call steloezxx("ble")
2919 pat ste loe zeq $1==$2 call steloezxx("beq")
2920 pat ste loe zne $1==$2 call steloezxx("bne")
2921 pat ste loe zge $1==$2 call steloezxx("bge")
2922 pat ste loe zgt $1==$2 call steloezxx("bgt")
2924 pat ste loe $1==$2 leaving dup WORD_SIZE ste $1
2926 pat lil inreg($1)==reg_pointer
2927 kills pre_post %reg==regvar($1, reg_pointer)
2928 yields {indirect_int, regvar($1, reg_pointer)}
2930 pat lil inreg($1)==reg_any
2931 uses AA_REG = {DLOCAL, $1}
2932 yields {indirect_int, %a}
2939 uses AA_REG = {DLOCAL, $1}
2940 yields {indirect_int, %a}
2943 /* When using the 'offsetted' intructions regAregXcon cannot be used
2944 * for the m68k[24]; there is no way of knowing about the size of
2945 * %1.bd+$1, because expressions are not allowed in stack patterns, and
2946 * this may lead to outputting too large displacements. With regAcon
2947 * the chance that this will happen is very slim, because it can
2948 * have displacements of 16 bits. Besides, leaving out regAcon here
2949 * would make it very hard to handle this instruction efficiently.
2952 with A_REG yields {offsetted_int, %1, $1}
2953 with exact local_addr yields {LOCAL, %1.bd+$1}
2954 with exact ext_addr yields {absolute_int, %1.bd+$1}
2956 with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
2957 #else /* TBL68020 */
2958 with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
2959 with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
2961 with exact offsetted4 yields {OFF_off_int, %1.reg, %1.bd, $1}
2962 with exact indirect yields {OFF_off_int, %1.reg, 0, $1}
2963 with exact DLOCAL yields {OFF_off_int, lb, %1.bd, $1}
2964 with exact off_con yields {OFF_off_int, %1.reg, %1.bd, %1.od+$1}
2965 with exact index_off4 yields {INDOFF_off_int, %1.reg, %1.xreg, %1.sc, %1.bd, $1}
2966 with exact indoff_con yields {INDOFF_off_int,
2967 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
2968 with exact off_regXcon yields {OFF_indoff_int,
2969 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
2970 with exact absolute4 yields {ABS_off_int, %1.bd, $1}
2971 with exact abs_con yields {ABS_off_int, %1.bd, %1.od+$1}
2972 with exact abs_regXcon yields {ABS_indoff_int, %1.sc, %1.xreg, %1.bd, %1.od+$1}
2973 with exact abs_index4 yields {ABSIND_off_int, %1.sc, %1.xreg, %1.bd, $1}
2974 with exact absind_con yields {ABSIND_off_int, %1.sc, %1.xreg, %1.bd, %1.od+$1}
2975 with exact ext_regX yields {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
2976 #endif /* FANCY_MODES */
2977 #endif /* TBL68020 */
2979 pat lal yields {local_addr, $1}
2981 pat lae yields {ext_addr, $1}
2983 pat lxl $1==0 yields lb
2985 pat lxl $1==1 yields {DLOCAL, SL}
2988 #if TBL68020 && FANCY_MODES
2989 yields {OFF_off4, lb, SL, SL}
2991 uses AA_REG = {DLOCAL, SL}
2992 yields {offsetted4, %a, SL}
2996 #if TBL68020 && FANCY_MODES
2997 uses AA_REG = {OFF_off4, lb, SL, SL}
2999 uses AA_REG = {DLOCAL, SL}
3000 gen move_l {offsetted4, %a, SL}, %a
3002 yields {offsetted4, %a, SL}
3005 uses AA_REG = {DLOCAL, SL},
3006 DD_REG4 = {const, $1-2}
3008 move_l {offsetted4, %a, SL} ,%a
3009 dbf %b, {slabel, 1b}
3012 pat lxa $1==0 yields {local_addr, SL}
3015 #if TBL68020 && FANCY_MODES
3016 yields {off_con, lb, SL, SL}
3018 uses AA_REG = {DLOCAL, SL}
3019 yields {regAcon, %a, SL}
3023 #if TBL68020 && FANCY_MODES
3024 uses AA_REG = {OFF_off4, lb, SL, SL}
3026 uses AA_REG = {DLOCAL, SL}
3027 gen move_l {offsetted4, %a, SL}, %a
3029 yields {regAcon, %a, SL}
3032 uses AA_REG = {DLOCAL, SL},
3033 DD_REG4 = {const, $1-2}
3035 move_l {offsetted4, %a, SL} ,%a
3036 dbf %b, {slabel, 1b}
3037 yields {regAcon, %a, SL}
3040 with A_REG yields {indirect1, %1}
3041 with exact local_addr yields {offsetted1, lb, %1.bd}
3042 with exact ext_addr yields {absolute1, %1.bd}
3044 with regAcon yields {offsetted1, %1.reg, %1.bd}
3045 with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
3046 #else /* TBL68020 */
3047 with exact regAcon yields {offsetted1, %1.reg, %1.bd}
3048 with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
3050 with exact indirect4 yields {OFF_off1, %1.reg, 0, 0}
3051 with exact offsetted4 yields {OFF_off1, %1.reg, %1.bd, 0}
3052 with exact LOCAL yields {OFF_off1, lb, %1.bd, 0}
3053 with exact off_con yields {OFF_off1, %1.reg, %1.bd, %1.od}
3054 with exact index_off4 yields {INDOFF_off1, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
3055 with exact indoff_con yields {INDOFF_off1,
3056 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3057 with exact off_regXcon yields {OFF_indoff1,
3058 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3059 with exact absolute4 yields {ABS_off1, %1.bd, 0}
3060 with exact abs_con yields {ABS_off1, %1.bd, %1.od}
3061 with exact abs_regXcon yields {ABS_indoff1, %1.sc, %1.xreg, %1.bd, %1.od}
3062 with exact abs_index4 yields {ABSIND_off1, %1.sc, %1.xreg, %1.bd, 0}
3063 with exact absind_con yields {ABSIND_off1, %1.sc, %1.xreg, %1.bd, %1.od}
3064 with exact ext_regX yields {abs_index1, %1.sc, %1.xreg, %1.bd}
3065 #endif /* FANCY_MODES */
3066 #endif /* TBL68020 */
3069 with A_REG yields {indirect2, %1}
3071 with exact local_addr yields {offsetted2, lb, %1.bd}
3073 with exact local_addr yields {LOCAL, %1.bd}
3075 with exact ext_addr yields {absolute2, %1.bd}
3077 with regAcon yields {offsetted2, %1.reg, %1.bd}
3078 with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
3079 #else /* TBL68020 */
3080 with exact regAcon yields {offsetted2, %1.reg, %1.bd}
3081 with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
3083 with exact DLOCAL yields {ILOCAL, %1.bd}
3086 with exact indirect4 yields {OFF_off2, %1.reg, 0, 0}
3087 with exact offsetted4 yields {OFF_off2, %1.reg, %1.bd, 0}
3088 with exact LOCAL yields {OFF_off2, lb, %1.bd, 0}
3089 with exact off_con yields {OFF_off2, %1.reg, %1.bd, %1.od}
3090 with exact index_off4 yields {INDOFF_off2, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
3091 with exact indoff_con yields {INDOFF_off2,
3092 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3093 with exact off_regXcon yields {OFF_indoff2,
3094 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3095 with exact absolute4 yields {ABS_off2, %1.bd, 0}
3096 with exact abs_con yields {ABS_off2, %1.bd, %1.od}
3097 with exact abs_regXcon yields {ABS_indoff2, %1.sc, %1.xreg, %1.bd, %1.od}
3098 with exact abs_index4 yields {ABSIND_off2, %1.sc, %1.xreg, %1.bd, 0}
3099 with exact absind_con yields {ABSIND_off2, %1.sc, %1.xreg, %1.bd, %1.od}
3100 with exact ext_regX yields {abs_index2, %1.sc, %1.xreg, %1.bd}
3101 #endif /* FANCY_MODES */
3102 #endif /* TBL68020 */
3105 with A_REG yields {indirect4, %1}
3106 with exact local_addr yields {DLOCAL, %1.bd}
3107 with exact ext_addr yields {absolute4, %1.bd}
3109 with regAcon yields {offsetted4, %1.reg, %1.bd}
3110 with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
3111 #else /* TBL68020 */
3112 with exact regAcon yields {offsetted4, %1.reg, %1.bd}
3113 with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
3115 with exact LOCAL yields {ILOCAL, %1.bd}
3118 with exact indirect4 yields {OFF_off4, %1.reg, 0, 0}
3119 with exact offsetted4 yields {OFF_off4, %1.reg, %1.bd, 0}
3120 with exact off_con yields {OFF_off4, %1.reg, %1.bd, %1.od}
3121 with exact index_off4 yields {INDOFF_off4, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
3122 with exact indoff_con yields {INDOFF_off4,
3123 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3124 with exact off_regXcon yields {OFF_indoff4,
3125 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3126 with exact absolute4 yields {ABS_off4, %1.bd, 0}
3127 with exact abs_con yields {ABS_off4, %1.bd, %1.od}
3128 with exact abs_regXcon yields {ABS_indoff4, %1.sc, %1.xreg, %1.bd, %1.od}
3129 with exact abs_index4 yields {ABSIND_off4, %1.sc, %1.xreg, %1.bd, 0}
3130 with exact absind_con yields {ABSIND_off4, %1.sc, %1.xreg, %1.bd, %1.od}
3131 with exact ext_regX yields {abs_index4, %1.sc, %1.xreg, %1.bd}
3132 #endif /* FANCY_MODES */
3133 #endif /* TBL68020 */
3138 yields {offsetted2, %1, 4} {indirect4, %1}
3139 with exact local_addr
3140 yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
3142 yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
3150 yields {offsetted4, %1, 4} {indirect4, %1}
3151 with exact local_addr
3152 yields {offsetted4, lb, %1.bd+4} {offsetted4, lb, %1.bd}
3154 yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
3158 pat loi $1==3*WORD_SIZE
3161 uses DD_REG4={const,$1}
3163 move_i {pre_dec_int, %1},{pre_dec_int, sp}
3164 move_i {pre_dec_int, %1},{pre_dec_int, sp}
3165 move_i {pre_dec_int, %1},{pre_dec_int, sp}
3167 pat loi $1==4*WORD_SIZE
3170 uses DD_REG4={const4,$1}
3172 move_i {pre_dec_int, %1},{pre_dec_int, sp}
3173 move_i {pre_dec_int, %1},{pre_dec_int, sp}
3174 move_i {pre_dec_int, %1},{pre_dec_int, sp}
3175 move_i {pre_dec_int, %1},{pre_dec_int, sp}
3178 pat loi $1>4*WORD_SIZE && $1/WORD_SIZE <= 65536
3181 uses DD_REG4 = {const, $1/WORD_SIZE -1}
3182 gen add_l {const4, $1}, %1
3184 move_i {pre_dec_int, %1}, {pre_dec_int, sp}
3185 dbf %a, {slabel, 1b}
3190 gen move_i {const,$1},{pre_dec_int, sp}
3191 jsr {absolute4, ".los"}
3193 pat los $1==WORD_SIZE
3196 gen jsr {absolute4, ".los"}
3201 gen jsr {absolute4, ".los4"}
3206 yields {absolute4, $1}
3208 yields {absolute4, $1+4}
3214 with A_REG yields {offsetted4, %1, $1}
3215 with exact local_addr yields {DLOCAL, %1.bd+$1}
3216 with regAcon yields {offsetted4, %1.reg, %1.bd+$1}
3218 with A_REG yields {offsetted4, %1, $1+4}
3219 {offsetted4, %1, $1}
3220 with exact local_addr yields {LOCAL, %1.bd+$1+4}
3222 with regAcon yields {offsetted4, %1.reg, %1.bd+$1+4}
3223 {offsetted4, %1.reg, %1.bd+$1}
3226 pat lpi yields {ext_addr, $1}
3228 /************************************************
3229 * Group 2: store instructions *
3230 ************************************************/
3232 pat stl inreg($1)==reg_any
3233 with exact memory1-consts
3234 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
3235 gen clr_i {LOCAL, $1}
3236 move_b %1, {dreg1, regvar($1,reg_any)}
3239 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
3240 gen move %1, {LOCAL, $1}
3242 with exact memory2-consts
3243 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
3244 gen clr_i {LOCAL, $1}
3245 move_w %1, {dreg2, regvar($1,reg_any)}
3247 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
3248 gen move %1, {LOCAL, $1}
3251 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
3252 gen move_i {post_inc_int, sp}, {LOCAL, $1}
3254 pat SLP inreg($1)==reg_pointer
3259 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
3260 gen move %1, {areg, regvar($1, reg_pointer)}
3262 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
3263 gen move_l %1, {areg, regvar($1, reg_pointer)}
3264 with address-ext_addr
3265 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
3266 gen lea %1, {areg, regvar($1, reg_pointer)}
3268 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
3269 gen move_l {post_inc4, sp}, {areg, regvar($1, reg_pointer)}
3272 with store_int-sconsts
3273 kills all_indir, LOCAL %bd==$1
3274 gen move %1, {LOCAL, $1}
3276 kills all_indir, LOCAL %bd==$1
3277 gen move_i {post_inc_int,sp}, {LOCAL, $1}
3280 with store_int-sconsts
3282 gen move %1, {absolute_int, $1}
3285 gen move_i {post_inc_int, sp}, {absolute_int, $1}
3287 pat sil inreg($1)==reg_pointer
3288 with store_int-sconsts
3290 gen move %1, {indirect_int, regvar($1, reg_pointer)}
3293 gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
3296 pat sil inreg($1)==reg_any
3297 with store_int-sconsts
3299 uses AA_REG = {DLOCAL, $1}
3300 gen move %1, {indirect_int, %a}
3303 uses AA_REG = {DLOCAL, $1}
3304 gen move_i {post_inc_int, sp}, {indirect_int, %a}
3309 with store_int-sconsts
3311 gen move %1, {ILOCAL, $1}
3314 gen move_i {post_inc_int, sp}, {ILOCAL, $1}
3316 with store_int-sconsts
3318 uses AA_REG = {DLOCAL, $1}
3319 gen move %1, {indirect_int, %a}
3322 uses AA_REG = {DLOCAL, $1}
3323 gen move_i {post_inc_int, sp}, {indirect_int, %a}
3327 with A_REG store_int-sconsts
3329 gen move %2, {offsetted_int, %1, $1}
3330 with exact any4 STACK
3333 gen move_i {post_inc_int, sp}, {offsetted_int, %a, $1}
3337 gen move_l {post_inc4, sp}, %a
3338 move_i {post_inc_int, sp}, {offsetted_int, %a, $1}
3339 with exact local_addr store_int
3341 gen move %2, {LOCAL, %1.bd+$1}
3342 with exact ext_addr store_int
3344 gen move %2, {absolute_int, %1.bd+$1}
3347 with regAcon store_int
3349 gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
3351 #else /* TBL68020 */
3352 with exact regAcon store_int
3354 gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
3355 with exact regAregXcon store_int
3357 gen move %2, {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
3359 with exact indirect4 store_int
3361 gen move %2, {OFF_off_int, %1.reg, 0, $1}
3362 with exact offsetted4 store_int
3364 gen move %2, {OFF_off_int, %1.reg, %1.bd, $1}
3365 with exact DLOCAL store_int
3367 gen move %2, {OFF_off_int, lb, %1.bd, $1}
3368 with exact off_con store_int
3370 gen move %2, {OFF_off_int, %1.reg, %1.bd, %1.od+$1}
3371 with exact index_off4 store_int
3373 gen move %2, {INDOFF_off_int, %1.reg, %1.xreg, %1.sc, %1.bd, $1}
3374 with exact indoff_con store_int
3376 gen move %2, {INDOFF_off_int, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
3377 with exact off_regXcon store_int
3379 gen move %2, {OFF_indoff_int, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
3380 with exact absolute4 store_int
3382 gen move %2, {ABS_off_int, %1.bd, $1}
3383 with exact abs_con store_int
3385 gen move %2, {ABS_off_int, %1.bd, %1.od+$1}
3386 with exact abs_regXcon store_int
3388 gen move %2, {ABS_indoff_int, %1.sc, %1.xreg, %1.bd, %1.od+$1}
3389 with exact abs_index4 store_int
3391 gen move %2, {ABSIND_off_int, %1.sc, %1.xreg, %1.bd, $1}
3392 with exact absind_con store_int
3394 gen move %2, {ABSIND_off_int, %1.sc, %1.xreg, %1.bd, %1.od+$1}
3395 with exact ext_regX store_int
3397 gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
3398 #endif /* FANCY_MODES */
3399 #endif /* TBL68020 */
3404 gen move %2, {indirect1, %1}
3405 with local_addr any1
3407 gen move %2, {offsetted1, lb, %1.bd}
3408 with exact ext_addr any1
3410 gen move %2, {absolute1, %1.bd}
3414 gen move %2, {offsetted1, %1.reg, %1.bd}
3415 with regAregXcon any1
3417 gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
3418 #else /* TBL68020 */
3419 with exact regAcon any1
3421 gen move %2, {offsetted1, %1.reg, %1.bd}
3422 with exact regAregXcon any1
3424 gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
3426 with exact indirect4 any1
3428 gen move %2, {OFF_off1, %1.reg, 0, 0}
3429 with exact offsetted4 any1
3431 gen move %2, {OFF_off1, %1.reg, %1.bd, 0}
3432 with exact LOCAL any1
3434 gen move %2, {OFF_off1, lb, %1.bd, 0}
3435 with exact off_con any1
3437 gen move %2, {OFF_off1, %1.reg, %1.bd, %1.od}
3438 with exact index_off4 any1
3440 gen move %2, {INDOFF_off1, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
3441 with exact indoff_con any1
3443 gen move %2, {INDOFF_off1, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3444 with exact off_regXcon any1
3446 gen move %2, {OFF_indoff1, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3447 with exact absolute4 any1
3449 gen move %2, {ABS_off1, %1.bd, 0}
3450 with exact abs_con any1
3452 gen move %2, {ABS_off1, %1.bd, %1.od}
3453 with exact abs_regXcon any1
3455 gen move %2, {ABS_indoff1, %1.sc, %1.xreg, %1.bd, %1.od}
3456 with exact abs_index4 any1
3458 gen move %2, {ABSIND_off1, %1.sc, %1.xreg, %1.bd, 0}
3459 with exact absind_con any1
3461 gen move %2, {ABSIND_off1, %1.sc, %1.xreg, %1.bd, %1.od}
3462 with exact ext_regX any1
3464 gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
3465 #endif /* FANCY_MODES */
3466 #endif /* TBL68020 */
3471 gen move %2, {indirect2, %1}
3472 with local_addr any2
3474 gen move %2, {offsetted2, lb, %1.bd}
3475 with exact ext_addr any2
3477 gen move %2, {absolute2, %1.bd}
3481 gen move %2, {offsetted2, %1.reg, %1.bd}
3482 with regAregXcon any2
3484 gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
3485 #else /* TBL68020 */
3486 with exact regAcon any2
3488 gen move %2, {offsetted2, %1.reg, %1.bd}
3489 with exact regAregXcon any2
3491 gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
3493 with exact DLOCAL any2
3495 gen move %2, {ILOCAL, %1.bd}
3498 with exact indirect4 any2
3500 gen move %2, {OFF_off2, %1.reg, 0, 0}
3501 with exact offsetted4 any2
3503 gen move %2, {OFF_off2, %1.reg, %1.bd, 0}
3504 with exact LOCAL any2
3506 gen move %2, {OFF_off2, lb, %1.bd, 0}
3507 with exact off_con any2
3509 gen move %2, {OFF_off2, %1.reg, %1.bd, %1.od}
3510 with exact index_off4 any2
3512 gen move %2, {INDOFF_off2, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
3513 with exact indoff_con any2
3515 gen move %2, {INDOFF_off2, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3516 with exact off_regXcon any2
3518 gen move %2, {OFF_indoff2, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3519 with exact absolute4 any2
3521 gen move %2, {ABS_off2, %1.bd, 0}
3522 with exact abs_con any2
3524 gen move %2, {ABS_off2, %1.bd, %1.od}
3525 with exact abs_regXcon any2
3527 gen move %2, {ABS_indoff2, %1.sc, %1.xreg, %1.bd, %1.od}
3528 with exact abs_index4 any2
3530 gen move %2, {ABSIND_off2, %1.sc, %1.xreg, %1.bd, 0}
3531 with exact absind_con any2
3533 gen move %2, {ABSIND_off2, %1.sc, %1.xreg, %1.bd, %1.od}
3534 with exact ext_regX any2
3536 gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
3537 #endif /* FANCY_MODES */
3538 #endif /* TBL68020 */
3541 with A_REG store4-sconsts4
3543 gen move %2, {indirect4, %1}
3544 with exact any4 STACK
3547 gen move_l {post_inc4, sp}, {indirect4, %a}
3551 gen move_l {post_inc4, sp}, %a
3552 move_l {post_inc4, sp}, {indirect4, %a}
3553 with exact local_addr store4
3555 gen move %2, {DLOCAL, %1.bd}
3556 with exact ext_addr store4
3558 gen move %2, {absolute4, %1.bd}
3560 with regAcon store4-sconsts4
3562 gen move %2, {offsetted4, %1.reg, %1.bd}
3563 with regAregXcon store4-sconsts4
3565 gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
3566 #else /* TBL68020 */
3567 with exact regAcon store4
3569 gen move %2, {offsetted4, %1.reg, %1.bd}
3570 with exact regAregXcon store4
3572 gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
3574 with exact LOCAL store4
3576 gen move %2, {ILOCAL, %1.bd}
3579 with exact indirect4 store4
3581 gen move %2, {OFF_off4, %1.reg, 0, 0}
3582 with exact offsetted4 store4
3584 gen move %2, {OFF_off4, %1.reg, %1.bd, 0}
3585 with exact off_con store4
3587 gen move %2, {OFF_off4, %1.reg, %1.bd, %1.od}
3588 with exact index_off4 store4
3590 gen move %2, {INDOFF_off4, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
3591 with exact indoff_con store4
3593 gen move %2, {INDOFF_off4, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3594 with exact off_regXcon store4
3596 gen move %2, {OFF_indoff4, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
3597 with exact absolute4 store4
3599 gen move %2, {ABS_off4, %1.bd, 0}
3600 with exact abs_con store4
3602 gen move %2, {ABS_off4, %1.bd, %1.od}
3603 with exact abs_regXcon store4
3605 gen move %2, {ABS_indoff4, %1.sc, %1.xreg, %1.bd, %1.od}
3606 with exact abs_index4 store4
3608 gen move %2, {ABSIND_off4, %1.sc, %1.xreg, %1.bd, 0}
3609 with exact absind_con store4
3611 gen move %2, {ABSIND_off4, %1.sc, %1.xreg, %1.bd, %1.od}
3612 with exact ext_regX store4
3614 gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
3615 #endif /* FANCY_MODES */
3616 #endif /* TBL68020 */
3620 with A_REG any4 any2
3622 gen move %2, {indirect4, %1}
3623 move %3, {offsetted2, %1, 4}
3624 with AA_REG any4 any2
3626 gen move %2, {post_inc4, %1}
3627 move %3, {post_inc2, %1}
3628 with exact A_REG STACK
3630 gen move_l {post_inc4, sp}, {indirect4, %1}
3631 move_w {post_inc2, sp}, {offsetted2, %1, 4}
3632 with exact AA_REG STACK
3634 gen move_l {post_inc4, sp}, {post_inc4, %1}
3635 move_w {post_inc2, sp}, {post_inc2, %1}
3642 with AA_REG any4-pre_post any4-pre_post
3644 gen move_l %2,{indirect4, %1}
3645 move_l %3,{offsetted4, %1, 4}
3646 with exact local_addr any4-pre_post any4-pre_post
3648 gen move_l %2,{offsetted4, lb, %1.bd}
3649 move_l %3,{offsetted4, lb, %1.bd+4}
3650 with exact ext_addr any4-pre_post any4-pre_post
3652 gen move_l %2,{absolute4, %1.bd}
3653 move_l %3,{absolute4, %1.bd+4}
3658 pat sti $1==3*WORD_SIZE
3661 gen move_i {post_inc_int, sp},{post_inc_int,%1}
3662 move_i {post_inc_int, sp},{post_inc_int,%1}
3663 move_i {post_inc_int, sp},{post_inc_int,%1}
3665 pat sti $1==4*WORD_SIZE
3668 gen move_i {post_inc_int, sp},{post_inc_int,%1}
3669 move_i {post_inc_int, sp},{post_inc_int,%1}
3670 move_i {post_inc_int, sp},{post_inc_int,%1}
3671 move_i {post_inc_int, sp},{post_inc_int,%1}
3674 pat sti $1>4*WORD_SIZE && $1/WORD_SIZE <= 65536
3677 uses DD_REG4 = {const, $1/WORD_SIZE -1}
3679 move_i {post_inc_int, sp}, {post_inc_int, %1}
3680 dbf %a, {slabel, 1b}
3685 gen move_i {const, $1}, {pre_dec_int, sp}
3686 jsr {absolute4, ".sts"}
3688 pat sts $1==WORD_SIZE
3691 gen jsr {absolute4, ".sts"}
3696 gen jsr {absolute4, ".sts4"}
3701 with store4-sconsts4
3702 kills all_indir, DLOCAL %bd==$1
3703 gen move %1, {DLOCAL, $1}
3705 kills all_indir, DLOCAL %bd==$1
3706 gen move_l {post_inc4,sp}, {DLOCAL, $1}
3709 with any4-sconsts any4-sconsts
3710 kills all_indir, LOCAL %bd==$1
3711 gen move %1, {LOCAL, $1}
3712 move %2, {LOCAL, $1+4}
3715 kills all_indir, LOCAL %bd==$1
3716 gen fmove_d %1, {LOCAL, $1}
3719 kills all_indir, LOCAL %bd==$1
3720 gen move_l {post_inc4, sp}, {LOCAL,$1}
3721 move_l {post_inc4, sp}, {LOCAL,$1+4}
3722 #endif /* WORD_SIZE==2 */
3728 gen move_l %1, {absolute4, $1}
3731 gen move_l {post_inc4, sp}, {absolute4, $1}
3733 with any4-sconsts any4-sconsts
3735 gen move %1, {absolute4, $1}
3736 move %2, {absolute4, $1+4}
3740 gen fmove_d %1, {absolute4, $1}
3744 gen move_l {post_inc4, sp}, {absolute4,$1}
3745 move_l {post_inc4, sp}, {absolute4,$1+4}
3750 with A_REG any4-sconsts4
3752 gen move_l %2, {offsetted4, %1, $1}
3753 with exact A_REG STACK
3755 gen move_l {post_inc4, sp}, {offsetted4, %1, $1}
3757 with A_REG any4-sconsts any4-sconsts
3759 gen move %2, {offsetted4, %1, $1}
3760 move %3, {offsetted4, %1, $1+4}
3761 with exact local_addr any4 any4
3763 gen move %2, {LOCAL, %1.bd+$1}
3764 move %3, {LOCAL, %1.bd+$1+4}
3765 with regAcon any4-sconsts any4-sconsts
3767 gen move %2, {offsetted4, %1.reg, %1.bd+$1}
3768 move %3, {offsetted4, %1.reg, %1.bd+$1+4}
3773 /************************************************
3774 * Group 3: integer arithmetic. *
3775 ************************************************/
3779 with any2-bconst DD_REG
3780 gen add_w %1, %2 yields %2
3781 with DD_REG any2-DD_REG-bconst
3782 gen add_w %2, %1 yields %1
3783 with exact any2 STACK
3784 uses reusing %1,DD_REG=%1
3785 gen add_w {post_inc2, sp}, %a
3790 with any4-bconst4 DD_REG4
3791 gen add_l %1, %2 yields %2
3792 with DD_REG4 any4-DD_REG4-bconst4
3793 gen add_l %2, %1 yields %1
3794 with exact any4 STACK
3795 uses reusing %1,DD_REG4=%1
3796 gen add_l {post_inc4, sp}, %a
3801 with any2-bconst DD_REG
3802 gen sub_w %1, %2 yields %2
3803 with DD_REG any2-DD_REG-bconst
3806 with exact any2 STACK
3807 uses reusing %1,DD_REG=%1
3808 gen sub_w {post_inc2, sp}, %a
3813 with any4-bconst4 DD_REG4
3814 gen sub_l %1, %2 yields %2
3815 with DD_REG4 any4-DD_REG4-bconst4
3818 with exact any4 STACK
3819 uses reusing %1,DD_REG4=%1
3820 gen sub_l {post_inc4, sp}, %a
3822 with any4-bconst4 AA_REG
3823 gen sub_l %1, %2 yields %2
3826 pat loc loc cii ldc mli $1==2 && $2==4 && highw($4)==0 && loww($4)>0 && $5==4
3828 uses reusing %1, DD_REG4
3830 muls_w {const, loww($4)}, %a.1
3834 with any2-pre_post any2-pre_post
3835 uses reusing %2,DD_REG = %2
3836 gen muls_w %1, %a yields %a
3842 gen muls_l %1, %2 yields %2
3843 #else /* TBL68020 */
3846 gen jsr {absolute4, ".mli"}
3852 with data2-sconsts DD_REG
3860 with data4-sconsts4 DD_REG4
3861 gen divs_l %1, %2 yields %2
3862 #else /* TBL68020 */
3865 gen jsr {absolute4, ".dvi"}
3867 #endif /* TBL68020 */
3871 with data2-sconsts DD_REG
3881 with data4-sconsts4 DD_REG4
3883 gen divsl_l %1, {DREG_pair, %a, %2}
3885 /* !!!! contents of %2 have changed: make this known to cg */
3887 #else /* TBL68020 */
3890 gen jsr {absolute4, ".dvi"}
3892 #endif /* TBL68020 */
3897 gen neg_w %1 yields %1
3902 gen neg_l %1 yields %1
3906 with shconreg DD_REG
3907 gen asl_w %1, %2 yields %2
3911 with shconreg DD_REG4
3912 gen asl_l %1, %2 yields %2
3916 with shconreg DD_REG
3917 gen asr_w %1, %2 yields %2
3921 with shconreg DD_REG4
3922 gen asr_l %1, %2 yields %2
3924 /************************************************
3925 * Group 4: unsigned arithmetic. *
3926 ************************************************/
3928 pat adu leaving adi $1
3930 pat sbu leaving sbi $1
3934 with any2-pre_post any2-pre_post
3935 uses reusing %2,DD_REG = %2
3936 gen mulu_w %1, %a yields %a
3941 with data4-sconsts4 DD_REG4
3942 gen mulu_l %1, %2 yields %2
3943 #else /* TBL68020 */
3946 gen jsr {absolute4, ".mlu"}
3948 #endif /* TBL68020 */
3952 with data2-sconsts data2
3953 uses DD_REG4 = {zero_const4,0}
3955 divu_w %1, %a.1 yields %a.1
3960 with data4-sconsts4 DD_REG4
3961 gen divu_l %1, %2 yields %2
3962 #else /* TBL68020 */
3965 gen jsr {absolute4, ".dvu"}
3967 #endif /* TBL68020 */
3971 with data2-sconsts data2
3972 uses DD_REG4 = {zero_const4, 0}
3982 with data4-sconsts4 DD_REG4
3984 gen divul_l %1, {DREG_pair, %a, %2}
3986 /* !!!! contents of %2 have changed: make this known to cg */
3988 #else /* TBL68020 */
3991 gen jsr {absolute4, ".dvu"}
3993 #endif /* TBL68020 */
3995 pat slu leaving sli $1
3999 with shconreg DD_REG
4000 gen lsr_w %1, %2 yields %2
4004 with shconreg DD_REG4
4005 gen lsr_l %1, %2 yields %2
4007 /************************************************
4008 * Group 5: floating point arithmetic *
4009 ************************************************/
4011 /* Floating point stuff
4012 * Arithmetic instructions
4018 gen fadd_s {post_inc4,sp},%1 yields %1 leaving stl $2
4021 gen fadd_d {post_inc4,sp},%1 yields %1 leaving sdl $2
4023 with FS_REG FS_REG STACK
4024 gen fsub %1,%2 yields %2 leaving stl $2
4026 with FD_REG FD_REG STACK
4027 gen fsub %1,%2 yields %2 leaving sdl $2
4030 gen fmul_s {post_inc4,sp},%1 yields %1 leaving stl $2
4033 gen fmul_d {post_inc4,sp},%1 yields %1 leaving sdl $2
4035 with FS_REG FS_REG STACK
4036 gen fdiv %1,%2 yields %2 leaving stl $2
4038 with FD_REG FD_REG STACK
4039 gen fdiv %1,%2 yields %2 leaving sdl $2
4042 gen fneg %1 yields %1 leaving stl $2
4045 gen fneg %1 yields %1 leaving sdl $2
4049 gen fadd_s {post_inc4,sp},%1 yields %1 leaving ste $2
4052 gen fadd_d {post_inc4,sp},%1 yields %1 leaving sde $2
4054 with FS_REG FS_REG STACK
4055 gen fsub %1,%2 yields %2 leaving ste $2
4057 with FD_REG FD_REG STACK
4058 gen fsub %1,%2 yields %2 leaving sde $2
4061 gen fmul_s {post_inc4,sp},%1 yields %1 leaving ste $2
4064 gen fmul_d {post_inc4,sp},%1 yields %1 leaving sde $2
4066 with FS_REG FS_REG STACK
4067 gen fdiv %1,%2 yields %2 leaving ste $2
4069 with FD_REG FD_REG STACK
4070 gen fdiv %1,%2 yields %2 leaving sde $2
4073 gen fneg %1 yields %1 leaving ste $2
4076 gen fneg %1 yields %1 leaving sde $2
4080 gen fadd_s {indirect4,sp},%1
4081 fmove_s %1,{indirect4,sp}
4084 gen fadd_d {indirect4,sp},%1
4085 fmove_d %1,{indirect4,sp}
4087 with FS_REG FS_REG STACK
4089 fmove_s %2,{pre_dec4,sp}
4091 with FD_REG FD_REG STACK
4093 fmove_d %2,{pre_dec4,sp}
4096 gen fmul_s {indirect4,sp},%1
4097 fmove_s %1,{indirect4,sp}
4100 gen fmul_d {indirect4,sp},%1
4101 fmove_d %1,{indirect4,sp}
4103 with FS_REG FS_REG STACK
4105 fmove_s %2,{pre_dec4,sp}
4107 with FD_REG FD_REG STACK
4109 fmove_d %2,{pre_dec4,sp}
4113 fmove_s %1,{pre_dec4,sp}
4117 fmove_d %1,{pre_dec4,sp}
4119 with FS_REG FS_REG STACK
4123 fmove_s %2,{pre_dec4,sp}
4124 fmove_s %1,{pre_dec4,sp}
4126 with FD_REG FD_REG STACK
4130 fmove_d %2,{pre_dec4,sp}
4131 fmove_d %1,{pre_dec4,sp}
4133 pat adf $1==4 leaving cal ".adf4" asp 4
4134 pat adf $1==8 leaving cal ".adf8" asp 8
4135 pat sbf $1==4 leaving cal ".sbf4" asp 4
4136 pat sbf $1==8 leaving cal ".sbf8" asp 8
4137 pat mlf $1==4 leaving cal ".mlf4" asp 4
4138 pat mlf $1==8 leaving cal ".mlf8" asp 8
4139 pat dvf $1==4 leaving cal ".dvf4" asp 4
4140 pat dvf $1==8 leaving cal ".dvf8" asp 8
4141 pat ngf $1==4 leaving cal ".ngf4"
4142 pat ngf $1==8 leaving cal ".ngf8"
4143 pat fif $1==4 leaving lor 1 cal ".fif4" asp 4
4144 pat fif $1==8 leaving lor 1 cal ".fif8" asp 4
4147 pat fef $1==4 leaving lor 1 adp 0-2 cal ".fef4" asp 2
4148 pat fef $1==8 leaving lor 1 adp 0-2 cal ".fef8" asp 2
4150 pat fef $1==4 leaving lor 1 adp 0-4 cal ".fef4"
4151 pat fef $1==8 leaving lor 1 adp 0-4 cal ".fef8"
4154 /************************************************
4155 * Group 6: pointer arithmetic *
4156 ************************************************/
4158 pat adp $1==0 /* skip; array instructions might 'leave' this */
4161 with A_REG yields {t_regAcon, %1, $1}
4162 with exact local_addr yields {local_addr, %1.bd+$1}
4163 with exact ext_addr yields {ext_addr, %1.bd+$1}
4164 with exact regAcon + t_regAcon
4165 yields {t_regAcon, %1.reg, %1.bd+$1}
4166 with exact regAregXcon + t_regAregXcon
4167 yields {t_regAregXcon,%1.reg, %1.xreg, %1.sc, %1.bd+$1}
4168 #if TBL68020 && FANCY_MODES
4169 with exact indirect4 yields {off_con, %1.reg, 0, $1}
4170 with exact LOCAL yields {off_con, lb, %1.bd, $1}
4171 with exact offsetted4 yields {off_con, %1.reg, %1.bd, $1}
4172 with exact off_con yields {off_con, %1.reg, %1.bd, %1.od+$1}
4173 with exact index_off4 yields {indoff_con, %1.reg, %1.xreg, %1.sc, %1.bd, $1}
4174 with exact indoff_con yields {indoff_con,
4175 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
4176 with exact off_regXcon yields {off_regXcon,
4177 %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
4178 with exact absolute4 yields {abs_con, %1.bd, $1}
4179 with exact abs_con yields {abs_con, %1.bd, %1.od+$1}
4180 with exact abs_regXcon yields {abs_regXcon, %1.sc, %1.xreg, %1.bd, %1.od+$1}
4181 with exact abs_index4 yields {absind_con, %1.sc, %1.xreg, %1.bd, $1}
4182 with exact absind_con yields {absind_con, %1.sc, %1.xreg, %1.bd, %1.od+$1}
4183 with exact ext_regX yields {ext_regX, %1.sc, %1.xreg, %1.bd+$1}
4188 gen add_l %2, %1 yields %1 leaving cmu 4
4190 gen add_l %1, %2 yields %2 leaving cmu 4
4193 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4194 yields %2 leaving cmu 4
4200 gen add_l %2, %1 yields %1 leaving bne $2
4202 gen add_l %1, %2 yields %2 leaving bne $2
4205 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4206 yields %2 leaving bne $2
4211 gen add_l %2, %1 yields %1 leaving beq $2
4213 gen add_l %1, %2 yields %2 leaving beq $2
4216 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4217 yields %2 leaving beq $2
4220 pat ads LEP bne $1==4
4222 gen add_l %2, %1 yields %1 leaving LEP $2 bne $3
4224 gen add_l %1, %2 yields %2 leaving LEP $2 bne $3
4227 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4228 yields %2 leaving loe $2 bne $3
4231 pat ads LEP beq $1==4
4233 gen add_l %2, %1 yields %1 leaving LEP $2 beq $3
4235 gen add_l %1, %2 yields %2 leaving LEP $2 beq $3
4238 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4239 yields %2 leaving loe $2 beq $3
4242 pat ads LEP cmp $1==4
4244 gen add_l %2, %1 yields %1 leaving LEP $2 cmu 4
4246 gen add_l %1, %2 yields %2 leaving LEP $2 cmu 4
4249 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4250 yields %2 leaving LEP $2 cmu 4
4253 pat ads lae bne $1==4
4255 gen add_l %2, %1 yields %1 leaving lae $2 bne $3
4257 gen add_l %1, %2 yields %2 leaving lae $2 bne $3
4260 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4261 yields %2 leaving lae $2 bne $3
4264 pat ads lae beq $1==4
4266 gen add_l %2, %1 yields %1 leaving lae $2 beq $3
4268 gen add_l %1, %2 yields %2 leaving lae $2 beq $3
4271 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4272 yields %2 leaving lae $2 beq $3
4274 #endif /* WORD_SIZE==2 */
4276 pat ads lae cmp $1==4
4278 gen add_l %2, %1 yields %1 leaving lae $2 cmu 4
4280 gen add_l %1, %2 yields %2 leaving lae $2 cmu 4
4283 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4284 yields %2 leaving lae $2 cmu 4
4288 pat ads lal bne $1==4
4290 gen add_l %2, %1 yields %1 leaving lal $2 bne $3
4292 gen add_l %1, %2 yields %2 leaving lal $2 bne $3
4295 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4296 yields %2 leaving lal $2 bne $3
4299 pat ads lal beq $1==4
4301 gen add_l %2, %1 yields %1 leaving lal $2 beq $3
4303 gen add_l %1, %2 yields %2 leaving lal $2 beq $3
4306 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4307 yields %2 leaving lal $2 beq $3
4310 pat ads lal cmp $1==4
4312 gen add_l %2, %1 yields %1 leaving lal $2 cmu 4
4314 gen add_l %1, %2 yields %2 leaving lal $2 cmu 4
4317 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4318 yields %2 leaving lal $2 cmu 4
4321 pat ads LLP bne $1==4
4323 gen add_l %2, %1 yields %1 leaving LLP $2 bne $3
4325 gen add_l %1, %2 yields %2 leaving LLP $2 bne $3
4328 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4329 yields %2 leaving lol $2 bne $3
4332 pat ads LLP beq $1==4
4334 gen add_l %2, %1 yields %1 leaving LLP $2 beq $3
4336 gen add_l %1, %2 yields %2 leaving LLP $2 beq $3
4339 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4340 yields %2 leaving lol $2 beq $3
4342 #endif /* WORD_SIZE==2 */
4344 pat ads LLP cmp $1==4
4346 gen add_l %2, %1 yields %1 leaving LLP $2 cmu 4
4348 gen add_l %1, %2 yields %2 leaving LLP $2 cmu 4
4351 gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
4352 yields %2 leaving lol $2 cmu 4
4357 leaving loc 2 loc 4 cii ads 4
4361 with D_REG4 A_REG yields {regAregXcon, %2, %1, 1, 0}
4362 with D_REG4 regAcon + t_regAcon
4363 yields {t_regAregXcon, %2.reg, %1, 1, %2.bd}
4364 with D_REG4 local_addr yields {t_regAregXcon, lb, %1, 1, %2.bd}
4366 gen add_l %1, %2 yields %2
4370 with D_REG4 yields {regX, 1, %1}
4372 with regX A_REG yields {regAregXcon, %2, %1.xreg, %1.sc, 0}
4373 with exact regX regAcon yields {regAregXcon, %2.reg, %1.xreg, %1.sc, %2.bd}
4374 with exact regX local_addr
4375 yields {regAregXcon, lb, %1.xreg, %1.sc, %2.bd}
4377 with exact regX indirect4
4378 yields {off_regXcon, %2.reg, %1.xreg,%1.sc,0,0}
4379 with exact regX offsetted4
4380 yields {off_regXcon, %2.reg, %1.xreg, %1.sc, %2.bd, 0}
4381 with exact regX DLOCAL yields {off_regXcon, lb, %1.xreg, %1.sc, %2.bd, 0}
4382 with exact regX off_con yields {off_regXcon, %2.reg, %1.xreg,%1.sc,%2.bd,%2.od}
4383 with exact regX ext_addr
4384 yields {ext_regX, %1.sc, %1.xreg, %2.bd}
4385 with exact regX absolute4
4386 yields {abs_regXcon, %1.sc, %1.xreg, %2.bd, 0}
4387 with exact regX abs_con yields {abs_regXcon, %1.sc, %1.xreg, %2.bd, %2.od}
4388 with exact indirect4 ext_addr
4389 yields {off_con, %1.reg, 0, %2.bd}
4390 with exact offsetted4 ext_addr
4391 yields {off_con, %1.reg, %1.bd, %2.bd}
4392 with exact LOCAL ext_addr
4393 yields {off_con, lb, %1.bd, %2.bd}
4394 with exact index_off4 ext_addr
4395 yields {indoff_con, %1.reg, %1.xreg, %1.sc,%1.bd,%2.bd}
4396 with exact absolute4 ext_addr
4397 yields {abs_con, %1.bd, %2.bd}
4398 with exact abs_index4 ext_addr
4399 yields {absind_con, %1.sc, %1.xreg, %1.bd, %2.bd}
4400 with exact indirect4 ext_regX
4401 yields {off_regXcon, %1.reg, %2.xreg, %2.sc, 0, %2.bd}
4402 with exact offsetted4 ext_regX
4403 yields {off_regXcon, %1.reg, %2.xreg,%2.sc,%1.bd,%2.bd}
4404 with exact LOCAL ext_regX
4405 yields {off_regXcon, lb, %2.xreg, %2.sc, %1.bd, %2.bd}
4406 with exact absolute4 ext_regX
4407 yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
4408 #endif /* FANCY_MODES */
4409 #endif /* TBL68020 */
4411 /* I WOULD ALSO LIKE THIS:
4413 * with const leaving adp %1.num
4414 * BUT THAT DOESN'T WORK.
4419 leaving sbs 4 loc 4 loc 2 cii
4422 pat sbs $1==4 leaving sbi 4
4424 /* regX type OK ??? */
4426 pat loc slu $2==4 leaving loc $1 sli 4
4428 pat loc sli ads $1==1 && $2==4 && $3==4
4429 with D_REG4 yields {regX, 2, %1}
4432 pat loc sli ads $1==2 && $2==4 && $3==4
4433 with D_REG4 yields {regX, 4, %1}
4436 pat loc sli ads $1==3 && $2==4 && $3==4
4437 with D_REG4 yields {regX, 8, %1}
4441 pat loc sli $1==1 && $2==WORD_SIZE
4443 gen add_i %1, %1 yields %1
4446 pat loc sli $1==1 && $2==4
4448 gen add_l %1, %1 yields %1
4451 #endif /* TBL68020 */
4454 /************************************************
4455 * Group 7: increment / decrement / zero *
4456 ************************************************/
4458 pat inc leaving loc 1 adi WORD_SIZE
4460 pat inl inreg($1)==reg_any
4461 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
4462 gen add_i {const, 1}, {LOCAL, $1}
4465 kills all_indir, LOCAL %bd==$1
4466 gen add_i {const, 1}, {LOCAL, $1}
4469 kills all_indir, LOCAL %bd==$1
4470 uses DD_REG = {LOCAL, $1}
4471 gen add_i {const, 1}, {LOCAL, $1}
4477 gen add_i {const, 1}, {absolute_int, $1}
4479 pat dec leaving loc 1 sbi WORD_SIZE
4481 pat del inreg($1)==reg_any
4482 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
4483 gen sub_i {const, 1}, {LOCAL, $1}
4486 kills all_indir, LOCAL %bd==$1
4487 gen sub_i {const, 1}, {LOCAL, $1}
4490 kills all_indir, LOCAL %bd==$1
4491 uses DD_REG = {LOCAL, $1}
4492 gen sub_i {const, 1}, {LOCAL, $1}
4498 gen sub_i {const, 1}, {absolute_int, $1}
4500 pat zrl inreg($1)==reg_any
4501 kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
4502 gen clr_i {LOCAL, $1}
4504 pat zrl inreg($1)==reg_pointer
4505 kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
4506 gen move {const4,0}, {areg, regvar($1, reg_pointer)}
4509 kills all_indir, LOCAL %bd==$1
4510 gen clr_i {LOCAL, $1}
4512 pat zrl lol $1==$2 && inreg($1) < 0
4513 kills all_indir, LOCAL %bd==$1
4514 gen clr_i {LOCAL, $1} yields {zero_const, 0}
4518 gen clr_i {absolute_int, $1}
4522 gen clr_i {absolute_int, $1} yields {zero_const, 0}
4524 pat zer $1==4 yields {zero_const4, 0}
4526 pat zer $1==6 yields {zero_const, 0} {zero_const, 0} {zero_const, 0}
4528 pat zer $1==8 yields {zero_const, 0} {zero_const, 0}
4529 pat zer $1==12 yields {zero_const, 0} {zero_const, 0} {zero_const, 0}
4532 pat zer $1/WORD_SIZE <= 65536
4534 uses DD_REG4 = {const, $1/WORD_SIZE -1}
4536 clr_i {pre_dec_int, sp}
4537 dbf %a, {slabel, 1b}
4541 uses DD_REG4 = {const, $1/WORD_SIZE}
4543 clr_i {pre_dec_int, sp}
4544 sub_l {const4,1}, %a
4547 /************************************************
4548 * Group 8: convert instructions *
4549 ************************************************/
4556 gen jsr {absolute4, ".cii"}
4559 /* No sign-extension, though this is probably not what you may want.
4560 * This will teach compiler writers not to convert between unsigneds and
4561 * integers of a different size.
4563 pat loc loc ciu $1==2 && $2==4
4565 yields {zero_const4, 0}
4567 uses DD_REG4 = {zero_const4, 0}
4571 pat loc loc ciu $1==4 && $2==2
4573 yields {zero_const, 0}
4575 uses reusing %1, DD_REG4 = %1
4578 pat loc loc cui $1==2 && $2==4
4580 uses DD_REG4={zero_const4,0}
4581 gen move %1,%a.1 yields %a
4583 pat loc loc cui $1==4 && $2==2
4587 pat loc loc cuu $1==2 && $2==4
4589 uses reusing %1,DD_REG4
4591 and_l {const4,65535}, %a yields %a
4593 uses DD_REG4={zero_const4,0}
4594 gen move %1,%a.1 yields %a
4596 pat loc loc cuu $1==4 && $2==2
4604 gen jsr {absolute4, ".cuu"}
4611 pat loc loc cif $1==4 && $2==4
4615 fmove_s %a,{pre_dec4,sp}
4616 pat loc loc cif $1==4 && $2==8
4620 fmove_d %a,{pre_dec4,sp}
4621 pat loc loc cuf $1==4 && $2==4
4627 fsub_l {const,0-2147483648},%a
4628 fsub_l {const,0-2147483648},%a
4630 fmove_s %a,{pre_dec4,sp}
4631 pat loc loc cuf $1==4 && $2==8
4637 fsub_l {const,0-2147483648},%a
4638 fsub_l {const,0-2147483648},%a
4640 fmove_d %a,{pre_dec4,sp}
4641 pat loc loc cfi $1==4 && $2==4
4645 fmove_l %1,%a yields %a
4646 pat loc loc cfi $1==8 && $2==4
4650 fmove_l %1,%a yields %a
4651 pat loc loc cfu $1==4 && $2==4
4656 fmove_l %1,%a yields %a
4657 pat loc loc cfu $1==8 && $2==4
4662 fmove_l %1,%a yields %a
4663 pat loc loc cff $1==4 && $2==8
4665 gen fmove_d %1,{pre_dec4,sp}
4666 pat loc loc cff $1==8 && $2==4
4668 gen fmove_s %1,{pre_dec4,sp}
4671 * Floating point stuff
4675 /* The patterns need some room on the stack first */
4676 pat loc loc cif $1==2 && $2==4 leaving loc $1 cal ".cif4"
4678 pat loc loc cif $1==2 && $2==8
4681 gen clr_l {pre_dec4, sp}
4682 move_w %1,{pre_dec2, sp} leaving loc $1 cal ".cif8"
4684 pat loc loc cif $1==4 && $2==4 leaving loc $1 cal ".cif4" asp 2
4686 pat loc loc cif $1==4 && $2==8
4689 gen clr_w {pre_dec2, sp}
4690 move_l %1,{pre_dec4, sp} leaving loc $1 cal ".cif8"
4692 pat loc loc cuf $1==2 && $2==4 leaving loc $1 cal ".cuf4"
4694 pat loc loc cuf $1==2 && $2==8
4697 gen clr_l {pre_dec4, sp}
4698 move_w %1,{pre_dec2, sp} leaving loc $1 cal ".cuf8"
4700 pat loc loc cuf $1==4 && $2==4 leaving loc $1 cal ".cuf4" asp 2
4702 pat loc loc cuf $1==4 && $2==8
4705 gen clr_w {pre_dec2, sp}
4706 move_l %1,{pre_dec4, sp} leaving loc $1 cal ".cuf8"
4708 pat loc loc cfi $1==4 && ($2==2 || $2==4)
4709 leaving loc $1 loc $2 cal ".cfi" asp 8-$2
4711 pat loc loc cfi $1==8 && ($2==2 || $2==4)
4712 leaving loc $1 loc $2 cal ".cfi" asp 12-$2
4714 pat loc loc cfu $1==4 && ($2==2 || $2==4)
4715 leaving loc $1 loc $2 cal ".cfu" asp 8-$2
4716 pat loc loc cfu $1==8 && ($2==2 || $2==4)
4717 leaving loc $1 loc $2 cal ".cfu" asp 12-$2
4719 pat loc loc cif $1==4 && $2==4 leaving loc 4 cal ".cif4" asp 4
4720 pat loc loc cif $1==4 && $2==8 leaving loc 4 cal ".cif8"
4721 pat loc loc cuf $1==4 && $2==4 leaving loc 4 cal ".cuf4" asp 4
4722 pat loc loc cuf $1==4 && $2==8 leaving loc 4 cal ".cuf8"
4723 pat loc loc cfi leaving loc $1 loc $2 cal ".cfi" asp $1+4
4724 pat loc loc cfu leaving loc $1 loc $2 cal ".cfu" asp $1+4
4726 pat loc loc cff $1==8 && $2==4 leaving cal ".cff4" asp 4
4727 pat loc loc cff $1==4 && $2==8
4728 leaving zer 4 exg 4 cal ".cff8"
4729 #endif /* TBL68881 */
4731 /************************************************
4732 * Group 9: logical instructions *
4733 ************************************************/
4738 with datalt4+consts4-sconsts4 DD_REG4
4739 gen xxx* %1, %2 yields %2
4740 with DD_REG4 datalt4+consts4-sconsts4
4741 gen xxx* %2, %1 yields %1
4742 with exact any4 STACK
4743 uses reusing %1,DD_REG4=%1
4744 gen xxx* {post_inc4, sp}, %a yields %a
4748 with datalt_int+consts-sconsts DD_REG
4749 gen xxx* %1, %2 yields %2
4750 with DD_REG datalt_int+consts-sconsts
4751 gen xxx* %2, %1 yields %1
4752 with exact any_int STACK
4753 uses reusing %1,DD_REG=%1
4754 gen xxx* {post_inc_int, sp}, %a yields %a
4756 proc logdef example and
4758 uses DD_REG4 = {const, $1/WORD_SIZE -1},
4762 lea {regAcon, sp, $1}, %b
4764 move_i {post_inc_int, sp}, %c
4765 xxx* %c, {post_inc_int, %b}
4766 dbf %a, {slabel, 1b}
4774 lea {regAregXcon, sp, %1, 1, 0},%a
4775 asr_l {small_const, 2}, %1
4777 move_i {post_inc_int, sp}, %b
4778 xxx* %b, {post_inc_int, %a}
4779 sub_l {const4,1}, %1
4789 lea {regAregXcon, sp, %c, 1, 0},%a
4790 asr_l {small_const, 1}, %c
4791 sub_l {const4,1}, %c
4793 move_i {post_inc_int, sp}, %b
4794 xxx* %b, {post_inc_int, %a}
4795 dbf %c, {slabel, 1b}
4798 proc logbdef example and
4804 move_l {const4,$1/WORD_SIZE}, %c
4805 lea {regAregXcon, sp, %c, 1, 0},%a
4807 move_i {post_inc_int, sp}, %b
4808 xxx* %b, {post_inc_int, %a}
4809 sub_l {const4,1}, %c
4812 pat and $1==WORD_SIZE call logw(AND_I)
4814 pat and $1==2*WORD_SIZE call log2w("and.l")
4816 pat and $1>4 && $1/WORD_SIZE<=65536 call logdef(AND_I)
4817 pat and defined($1) call logbdef(AND_I)
4818 pat and !defined($1) call logndef(AND_I)
4820 pat ior $1==WORD_SIZE call logw(OR_I)
4822 pat ior $1==2*WORD_SIZE call log2w("or.l")
4824 pat ior $1>2 && $1/WORD_SIZE<=65536 call logdef(OR_I)
4825 pat ior defined($1) call logbdef(OR_I)
4826 pat ior !defined($1) call logndef(OR_I)
4830 with DD_REG conreg2-bconst
4831 gen eor_w %2, %1 yields %1
4835 with DD_REG4 conreg4-bconst4
4836 gen eor_l %2, %1 yields %1
4838 pat xor $1>4 && $1/WORD_SIZE<=65536 call logdef(EOR_I)
4839 pat xor defined($1) call logbdef(EOR_I)
4840 pat xor !defined($1) call logndef(EOR_I)
4845 gen not_w %1 yields %1
4850 gen not_l %1 yields %1
4853 with DD_REG4 DD_REG4
4855 not_l %2 yields %2 %1
4857 pat com $1>8 && $1/WORD_SIZE<=65536
4860 DD_REG4 = {const, $1/WORD_SIZE -1}
4863 not_i {post_inc_int, %a}
4864 dbf %b, {slabel, 1b}
4869 DD_REG4 = {const, $1/WORD_SIZE}
4872 not_i {post_inc_int, %a}
4873 sub_l {const4, 1}, %b
4877 pat com !defined($1)
4881 asr_l {small_const, 2}, %1
4883 not_i {post_inc_int, %a}
4884 sub_l {const4, 1}, %1
4887 pat com !defined($1)
4893 asr_l {small_const, 1}, %b
4894 sub_l {const4, 1}, %b
4896 not_i {post_inc_int, %a}
4897 dbf %b, {slabel, 1b}
4902 with shconreg DD_REG
4903 gen rol_w %1, %2 yields %2
4907 with shconreg DD_REG4
4908 gen rol_l %1, %2 yields %2
4912 with shconreg DD_REG
4913 gen ror_w %1, %2 yields %2
4917 with shconreg DD_REG4
4918 gen ror_l %1, %2 yields %2
4923 /************************************************
4925 ************************************************/
4929 with conreg2 DD_REG4
4932 and_l {const4, 1}, %2
4936 pat inn $1==WORD_SIZE
4940 and_i {const, 1}, %2
4943 /* The interface for the .inn differ for m68k2 and m68k4. */
4944 /* ??? Work out a cleaner interface, that is similar for all tables */
4949 gen move {const, $1}, d0
4950 jsr {absolute4, ".inn"}
4954 pat inn !defined($1)
4958 jsr {absolute4, ".inn"}
4966 move {const, $1}, d1
4967 jsr {absolute4, ".inn"}
4971 pat inn !defined($1)
4972 with any_int any_int STACK
4976 jsr {absolute4, ".inn"}
4979 #endif /* WORD_SIZE==2 */
4981 pat loc inn $2==WORD_SIZE && small($1)
4983 gen asr_i {small_const, $1}, %1
4984 and_i {const, 1}, %1
4990 uses DD_REG = {zero_const, 0}
4991 gen bset %1, %a yields %a
4996 uses DD_REG4 = {zero_const4, 0}
4997 gen bset %1, %a yields %a
5004 gen move {const, $1}, d0
5005 jsr {absolute4, ".set"}
5007 pat set !defined($1)
5011 jsr {absolute4, ".set"}
5017 move {const, $1}, d1
5018 jsr {absolute4, ".set"}
5020 pat set !defined($1)
5021 with any_int any_int STACK
5025 jsr {absolute4, ".set"}
5026 #endif /* WORD_SIZE==2 */
5031 /************************************************
5032 * Group 11: arrays *
5033 ************************************************/
5037 pat lar defined($1) && $1 == WORD_SIZE
5040 gen jsr {absolute4, ".lar"}
5042 pat sar defined($1) && $1 == WORD_SIZE
5045 gen jsr {absolute4, ".sar"}
5047 pat aar defined($1) && $1 == WORD_SIZE
5050 gen jsr {absolute4, ".aar"}
5055 gen move {const, $1}, d0
5056 jsr {absolute4, ".lar"}
5058 pat lar !defined($1)
5062 jsr {absolute4, ".lar"}
5067 gen move {const, $1}, d0
5068 jsr {absolute4, ".sar"}
5070 pat sar !defined($1)
5074 jsr {absolute4, ".sar"}
5079 gen move {const, $1}, d0
5080 jsr {absolute4, ".aar"}
5083 pat aar !defined($1)
5087 jsr {absolute4, ".aar"}
5091 pat lae lar $2==4 && nicesize(rom($1,3))
5092 leaving lae $1 aar 4 loi rom($1, 3)
5093 pat lae sar $2==4 && nicesize(rom($1,3))
5094 leaving lae $1 aar 4 sti rom($1, 3)
5096 pat lae aar $2==4 && rom($1,3)==1
5097 leaving ads 4 adp 0-rom($1,1)
5100 pat lae aar $2==4 && nicesize(rom($1,3))
5101 with D_REG yields {regX, rom($1,3), %1}
5102 leaving ads 4 adp rom($1,3)*(0-rom($1,1))
5103 #else /* TBL68020 */
5104 pat lae aar $2==4 && rom($1,3)==2
5106 gen asl_l {small_const, 1}, %1
5108 leaving ads 4 adp (0 - rom($1,1))<<1
5110 pat lae aar $2==4 && rom($1,3)==4
5112 gen asl_l {small_const, 2}, %1
5114 leaving ads 4 adp (0 - rom($1,1))<<2
5116 pat lae aar $2==4 && rom($1,3)==8
5118 gen asl_l {small_const, 3}, %1
5120 leaving ads 4 adp (0 - rom($1,1))<<3
5121 #endif /* TBL68020 */
5122 #endif /* ARR_OPT */
5123 #endif /* WORD_SIZE!=2 */
5125 /* I WOULD ALSO LIKE THESE:
5126 * pat lae aar $2==4 && defined(rom($1,3))
5127 * with const leaving adp rom($1,3)*(%1.num-rom($1,1))
5128 * pat lae lar $2==4 && defined(rom($1,3))
5129 * with const leaving adp rom($1,3)*(%1.num-rom($1,1))
5131 * pat lae sar $2==4 && defined(rom($1,3))
5132 * with const leaving adp rom($1,3)*(%1.num-rom($1,1))
5134 * BUT THEY DON'T WORK.
5139 /************************************************
5140 * Group 12: compare instructions *
5141 ************************************************/
5145 pat cmi defined($1) && $1==2
5147 uses DD_REG = {zero_const, 0}
5151 add_w {small_const, 1},%a
5154 sub_w {small_const, 1},%a
5158 pat cmi defined($1) && $1==4
5160 gen jsr {absolute4, ".cmi"} yields d1
5162 /* pat cmi $1==4 leaving sbi 4
5169 gen move {const, $1}, d0
5170 jsr {absolute4, ".cmi"}
5173 pat cmi !defined($1)
5177 jsr {absolute4, ".cmi"}
5181 /* pat cmu $1==4 leaving sbi 4
5188 gen move {const, $1},d0
5189 jsr {absolute4, ".cmu"}
5191 pat cmu !defined($1)
5194 jsr {absolute4, ".cmu"}
5199 gen move {const, $1}, d0
5200 jsr {absolute4, ".cmu"}
5203 pat cmu !defined($1)
5207 jsr {absolute4, ".cmu"}
5209 #endif /* WORD_SIZE==2 */
5212 pat cms $1==2 leaving cmi 2
5213 pat cms $1==4 leaving cmi 4
5215 pat cms $1==4 leaving cmi 4
5221 gen move {const, $1}, d0
5222 jsr {absolute4, ".cms"}
5225 pat cms !defined($1)
5229 jsr {absolute4, ".cms"}
5232 pat cmp leaving cmu 4
5237 uses reusing %1,DD_REG
5243 move_i {small_const,1},%a
5249 with test_set1 + test_set2
5251 uses reusing %1,DD_REG
5257 move_i {small_const,1},%a
5261 /* for some branches, we need to get rid of the overflow bit first.
5262 The easiest way to do this is to just test ....
5266 uses reusing %1,DD_REG
5273 move_i {small_const,1},%a
5279 with test_set1 + test_set2
5281 uses reusing %1,DD_REG
5287 move_i {small_const,1},%a
5291 pat tlt call txx("bmi", "bcs")
5292 pat tle call txx_ouch("ble", "bls")
5293 pat teq call txx("beq", "beq")
5294 pat tne call txx("bne", "bne")
5295 pat tge call txx("bpl", "bcc")
5296 pat tgt call txx_ouch("bgt", "bhi")
5300 uses reusing %1,DD_REG
5304 yields {extend1, %a}
5309 with test_set1 + test_set2
5311 uses reusing %1,DD_REG
5315 yields {extend1, %a}
5317 pat tlt call txx("smi", "scs")
5318 pat tle call txx("sle", "sls")
5319 pat teq call txx("seq", "seq")
5320 pat tne call txx("sne", "sne")
5321 pat tge call txx("spl", "scc")
5322 pat tgt call txx("sgt", "shi")
5332 uses D_REG={const,0}
5343 uses D_REG={const,0}
5353 pat cmf $1==4 leaving cal ".cmf4" asp 8 lfr WORD_SIZE
5354 pat cmf $1==8 leaving cal ".cmf8" asp 16 lfr WORD_SIZE
5360 pat zrf leaving zer $1
5362 /************************************************
5363 * Group 13: branch instructions *
5364 ************************************************/
5367 pat lab topeltsize($1)==4 && !fallthrough($1)
5369 gen labeldef $1 yields dl0
5371 pat lab topeltsize($1)==4 && fallthrough($1)
5376 labeldef $1 yields dl0
5379 pat lab topeltsize($1)==WORD_SIZE && !fallthrough($1)
5381 gen labeldef $1 yields d0
5383 pat lab topeltsize($1)==WORD_SIZE && fallthrough($1)
5388 labeldef $1 yields d0
5396 pat bra topeltsize($1)==4
5402 pat bra topeltsize($1)==WORD_SIZE
5409 gen bra {llabel, $1}
5411 proc brxx example beq
5412 with exact extend1 extend1
5417 with exact extend2 extend2
5422 with exact sconsts any_int
5427 with exact any_int sconsts
5432 with any_int-sconsts genreg STACK
5435 with genreg any_int-sconsts STACK
5438 with exact immediate_int-sconsts imm_cmp_int
5442 with exact imm_cmp_int immediate_int-sconsts
5446 with exact immediate_int-sconsts STACK
5447 gen cmp_i %1, {post_inc_int, sp}
5449 with exact any_int STACK
5450 uses reusing %1,DD_REG=%1
5451 gen cmp_i {post_inc_int, sp}, %a
5455 gen move_i {post_inc_int, sp},%a
5456 cmp_i {post_inc_int, sp},%a
5459 with exact post_inc4 post_inc4
5463 with exact post_inc2 post_inc2
5466 with exact post_inc1 post_inc1
5470 pat blt call brxx("blt","bgt")
5471 pat ble call brxx("ble","bge")
5472 pat beq call brxx("beq","beq")
5473 pat bne call brxx("bne","bne")
5474 pat bge call brxx("bge","ble")
5475 pat bgt call brxx("bgt","blt")
5477 proc zxx example zeq
5478 with test_set_int STACK
5482 with test_set1 STACK
5484 with test_set1 + test_set2 STACK
5489 gen tst_i {post_inc_int, sp}
5492 /* for some branches, we need to get rid of the overflow bit first.
5493 The easiest way to do this is to just test ....
5495 proc zxx_ouch example zeq
5496 with test_set_int STACK
5501 with test_set1 STACK
5503 with test_set1 + test_set2 STACK
5508 gen tst_i {post_inc_int, sp}
5511 pat zlt call zxx("bmi", "bcs")
5512 pat zle call zxx_ouch("ble", "bls")
5513 pat zeq call zxx("beq", "beq")
5514 pat zne call zxx("bne", "bne")
5515 pat zge call zxx("bpl", "bcc")
5516 pat zgt call zxx_ouch("bgt", "bhi")
5518 /************************************************
5519 * Group 14: procedure calls instructions *
5520 ************************************************/
5526 gen jsr {absolute4, %1.bd}
5529 gen jsr {indirect4, %1}
5532 uses AA_REG = {post_inc4, sp}
5533 gen jsr {indirect4, %a}
5541 gen jsr {absolute4, $1}
5544 pat lfr $1==2 yields d0
5545 pat lfr $1==4 yields dl0
5546 pat lfr $1==8 yields dl1 dl0
5548 pat lfr $1==4 yields d0
5549 pat lfr $1==8 yields d1 d0
5564 gen move_w {post_inc2, sp}, d0
5573 gen move_l {post_inc4, sp}, dl0
5581 with exact any4 STACK
5583 move_l {post_inc4, sp}, dl1
5586 gen move_l {post_inc4, sp}, dl0
5587 move_l {post_inc4, sp}, dl1
5591 /************************************************
5592 * Group 15: miscellaneous instructions *
5593 ************************************************/
5599 gen add_l {const4, $1}, sp
5604 with any-pre_post any-pre_post
5608 gen add_l {const4, $1}, sp
5612 with any4-pre_post any-pre_post
5613 with any-pre_post any4-pre_post
5614 with any-pre_post any-pre_post any-pre_post
5616 gen add_l {const4, $1}, sp
5620 with any4-pre_post any4-pre_post
5622 gen add_l {const4, $1}, sp
5626 gen lea {regAcon, sp, $1}, sp
5628 /* ??? DD_REG$ ??? */
5632 uses reusing %1,DD_REG4
5646 gen move_w {indirect2, %2}, {indirect2, %1}
5652 gen move_l {indirect4, %2}, {indirect4, %1}
5658 gen move_l {indirect4, %2}, {indirect4, %1}
5659 move_w {offsetted2, %2, 4}, {offsetted2, %1, 4}
5665 gen move_l {indirect4, %2}, {indirect4, %1}
5666 move_l {offsetted4, %2, 4}, {offsetted4, %1, 4}
5668 pat blm $1>2*WORD_SIZE && $1/WORD_SIZE <= 65536
5671 uses DD_REG4={const, $1/WORD_SIZE -1}
5673 move_i {post_inc_int, %2}, {post_inc_int, %1}
5674 dbf %a, {slabel, 1b}
5679 uses DD_REG4={const,$1/WORD_SIZE}
5681 move_i {post_inc_int, %2}, {post_inc_int, %1}
5682 sub_l {const4, 1}, %a
5687 with DD_REG AA_REG AA_REG
5689 gen asr_w {small_const, 1}, %1
5692 move_w {post_inc2, %3}, {post_inc2, %2}
5693 sub_w {const, 1}, %1
5699 with DD_REG4 AA_REG AA_REG
5703 asr_l {small_const, 1}, %1
5705 asr_l {small_const, 2}, %1
5709 move_i {post_inc_int, %3}, {post_inc_int, %2}
5710 sub_l {const4, 1}, %1
5717 with any4 D_REG+LOCAL+const+ILOCAL+absolute2 STACK
5719 with any4 D_REG+LOCAL+const+absolute2 STACK
5723 jmp {absolute4, ".csa2"}
5727 #if TBL68020 && WORD_SIZE==4
5728 with any4 D_REG4+DLOCAL+const4+ILOCAL+absolute4 STACK
5730 with any4 D_REG4+DLOCAL+const4+absolute4 STACK
5734 jmp {absolute4, ".csa4"}
5739 with any4 D_REG+LOCAL+const+ILOCAL+absolute2 STACK
5741 with any4 D_REG+LOCAL+const+absolute2 STACK
5745 jmp {absolute4, ".csb2"}
5749 #if TBL68020 && WORD_SIZE==4
5750 with any4 D_REG4+DLOCAL+const4+ILOCAL+absolute4 STACK
5752 with any4 D_REG4+DLOCAL+const4+absolute4 STACK
5756 jmp {absolute4, ".csb4"}
5758 pat dch leaving loi 4
5762 with dups2 yields %1 %1
5767 with dups2 dups2 yields %2 %1 %2 %1
5769 with dups4 yields %1 %1
5772 with dups4 dups4 yields %2 %1 %2 %1
5774 pat dup $1>2*WORD_SIZE && $1/WORD_SIZE<=65536
5776 uses DD_REG4 = {const, $1/WORD_SIZE -1}
5778 move_i {offsetted_int, sp, $1 -WORD_SIZE}, {pre_dec_int, sp}
5779 dbf %a, {slabel, 1b}
5783 uses DD_REG4 = {const, $1/WORD_SIZE}
5785 move_i {offsetted_int, sp, $1 -WORD_SIZE}, {pre_dec_int, sp}
5786 sub_l {const4, 1}, %a
5792 uses DD_REG4 = {zero_const4, 0}, AA_REG
5795 lea {regAregXcon, sp, %a, 1, 0}, %b
5796 asr_l {small_const, 1}, %a
5799 move_w {pre_dec2, %b}, {pre_dec2, sp}
5800 sub_l {const4, 1}, %a
5809 lea {regAregXcon, sp, %1, 1, 0}, %a
5811 asr_l {small_const, 1}, %1
5813 asr_l {small_const, 2}, %1
5817 move_i {pre_dec_int, %a}, {pre_dec_int, sp}
5818 sub_l {const4, 1}, %1
5824 with any2 any2 yields %1 %2
5828 with any4 any4 yields %1 %2
5833 gen move {const, $1}, d0
5834 jsr {absolute4, ".exg"}
5836 pat exg !defined($1)
5840 jsr {absolute4, ".exg"}
5843 gen move_l {ext_addr, $1}, {absolute4, ".filn"}
5847 uses AA_REG = {ext_addr, $1}
5848 gen move_l {offsetted4, %a, 8}, lb
5849 move_l {offsetted4, %a, 4}, sp
5850 #if TBL68020 && FANCY_MODES
5851 jmp {OFF_off4, %a, 0, 0}
5853 move_l {indirect4, %a}, %a
5857 pat lim yields {absolute_int, ".trpim"}
5861 gen move_i {const, $1}, {absolute_int, ".lino"}
5865 gen add_i {const, 1}, {absolute_int, ".lino"}
5867 pat lor $1==0 yields lb
5871 uses AA_REG = sp yields %a
5873 pat lor $1==2 yields {absolute4, ".reghp"}
5875 pat lpb leaving adp 8
5880 gen jsr {absolute4, ".mon"}
5886 gen jsr {absolute4, ".nop"}
5893 gen cmp2_w {absolute2, %1.bd}, %2
5895 move_w {small_const, 1}, {pre_dec2, sp} /* push constant 1 == ERANGE */
5896 jsr {absolute4, ".trp"}
5898 with address-ext_addr D_REG
5901 move_w {small_const, 1}, {pre_dec2, sp} /* push constant 1 == ERANGE */
5902 jsr {absolute4, ".trp"}
5905 gen cmp2_w {indirect2, %1}, %2
5907 move_w {small_const, 1}, {pre_dec2, sp} /* push constant 1 == ERANGE */
5908 jsr {absolute4, ".trp"}
5913 gen jsr {absolute4, ".rck"}
5915 #endif /* WORD_SIZE==2 */
5917 #if WORD_SIZE==4 || TBL68020
5920 with ext_addr D_REG4
5921 gen cmp2_l {absolute4, %1.bd}, %2
5923 pea {absolute4, 1} /* push constant 1 == ERANGE */
5924 jsr {absolute4, ".trp"}
5926 with address-ext_addr D_REG4
5929 pea {absolute4, 1} /* push constant 1 == ERANGE */
5930 jsr {absolute4, ".trp"}
5933 gen cmp2_l {indirect4, %1}, %2
5935 pea {absolute4, 1} /* push constant 1 == ERANGE */
5936 jsr {absolute4, ".trp"}
5938 #else /* TBL68020 */
5941 gen jsr {absolute4, ".rck"}
5942 #endif /* TBL68020 */
5943 #endif /* WORD_SIZE==4 || TBL68020 */
5945 pat rtt leaving ret 0
5951 gen move_l {absolute4, ".trppc"}, %a
5952 move_l %1, {absolute4, ".trppc"}
5958 gen move_i %1, {absolute_int, ".trpim"}
5972 gen jsr {absolute4, ".strhp"}
5977 gen jsr {absolute4, ".trp"}
5981 /************************************************
5982 * more rules for long EM-patterns *
5983 ************************************************/
5987 uses DD_REG = {absolute_int, $1}
5988 gen add_i {const,1}, {absolute_int, $1}
5994 uses DD_REG = {absolute_int, $1}
5995 gen sub_i {const,1}, {absolute_int, $1}
6000 proc llol1shstl example lol loc sli stl /* only left */
6001 kills all_indir, DLOCAL %bd==$1
6002 gen shw* {offsetted2, lb, $1+2}
6003 roxl {offsetted2, lb, $1}
6005 proc lloe1shste example loe loc sli ste /* only left */
6007 gen shw* {absolute2, $1+2}
6008 roxl {absolute2, $1}
6010 proc llil1shsil example lil loc sli sil /* only left */
6012 #if TBL68020 && FANCY_MODES
6013 gen shw* {OFF_off2, lb, $1, 2}
6014 roxl {OFF_off2, lb, $1, 0}
6016 uses AA_REG = {DLOCAL, $1}
6017 gen shw* {offsetted2, %a, 2}
6018 roxl {indirect2, %a}
6021 proc rlol1shstl example lol loc sri stl /* only right */
6022 kills all_indir, DLOCAL %bd==$1
6023 gen shw* {offsetted2, lb, $1}
6024 roxr {offsetted2, lb, $1+2}
6026 proc rloe1shste example loe loc sri ste /* only right */
6028 gen shw* {absolute2, $1}
6029 roxr {absolute2, $1+2}
6031 proc rlil1shsil example lil loc sri sil /* only right */
6033 #if TBL68020 && FANCY_MODES
6034 gen shw* {OFF_off2, lb, $1, 0}
6035 roxr {OFF_off2, lb, $1, 2}
6037 uses AA_REG = {DLOCAL, $1}
6038 gen shw* {indirect2, %a}
6039 roxr {offsetted2, %a, 2}
6042 pat lol loc sli stl $1==$4 && $2==1 && $3==4 call llol1shstl("asl #1,")
6043 pat loe loc sli ste $1==$4 && $2==1 && $3==4 call lloe1shste("asl #1,")
6044 pat lil loc sli sil $1==$4 && $2==1 && $3==4 call llil1shsil("asl #1,")
6045 pat lol loc sri stl $1==$4 && $2==1 && $3==4 call rlol1shstl("asr #1,")
6046 pat loe loc sri ste $1==$4 && $2==1 && $3==4 call rloe1shste("asr #1,")
6047 pat lil loc sri sil $1==$4 && $2==1 && $3==4 call rlil1shsil("asr #1,")
6048 pat lol loc slu stl $1==$4 && $2==1 && $3==4 call llol1shstl("asl #1,")
6049 pat loe loc slu ste $1==$4 && $2==1 && $3==4 call lloe1shste("asl #1,")
6050 pat lil loc slu sil $1==$4 && $2==1 && $3==4 call llil1shsil("asl #1,")
6051 pat lol loc sru stl $1==$4 && $2==1 && $3==4 call rlol1shstl("lsr #1,")
6052 pat loe loc sru ste $1==$4 && $2==1 && $3==4 call rloe1shste("lsr #1,")
6053 pat lil loc sru sil $1==$4 && $2==1 && $3==4 call rlil1shsil("lsr #1,")
6057 with test_set_int DD_REG
6063 with test_set1 DD_REG
6065 with test_set1 + test_set2 DD_REG
6073 with test_set_int DD_REG
6076 bset {zero_const, 0}, %2
6079 with test_set1 DD_REG
6081 with test_set1 + test_set2 DD_REG
6085 bset {zero_const, 0}, %2
6089 with test_set_int DD_REG
6096 with test_set1 DD_REG
6098 with test_set1 + test_set2 DD_REG
6106 with test_set_int DD_REG
6110 bset {zero_const, 0}, %2
6113 with test_set1 DD_REG
6115 with test_set1 + test_set2 DD_REG
6119 bset {zero_const, 0}, %2
6122 pat tlt and $2==WORD_SIZE call txxand("bmi", "bcs")
6123 pat tle and $2==WORD_SIZE call txxand_ouch("ble", "bls")
6124 pat teq and $2==WORD_SIZE call txxand("beq", "beq")
6125 pat tne and $2==WORD_SIZE call txxand("bne", "bne")
6126 pat tge and $2==WORD_SIZE call txxand("bpl", "bcc")
6127 pat tgt and $2==WORD_SIZE call txxand_ouch("bgt", "bhi")
6129 pat tlt ior $2==WORD_SIZE call txxior("bpl", "bcc")
6130 pat tle ior $2==WORD_SIZE call txxior_ouch("bgt", "bhi")
6131 pat teq ior $2==WORD_SIZE call txxior("bne", "bne")
6132 pat tne ior $2==WORD_SIZE call txxior("beq", "beq")
6133 pat tge ior $2==WORD_SIZE call txxior("bmi", "bcs")
6134 pat tgt ior $2==WORD_SIZE call txxior_ouch("ble", "bls")
6137 with exact extend1 extend1 DD_REG
6142 with exact extend2 extend2 DD_REG
6147 with exact sconsts any_int DD_REG
6153 with exact any_int sconsts DD_REG
6159 with any_int-sconsts genreg DD_REG
6164 with genreg any_int-sconsts DD_REG
6169 with exact immediate_int-sconsts imm_cmp_int DD_REG
6174 with exact imm_cmp_int immediate_int-sconsts DD_REG
6181 with exact extend1 extend1 DD_REG
6184 bset {zero_const, 0}, %3
6186 with exact extend2 extend2 DD_REG
6189 bset {zero_const, 0}, %3
6191 with exact sconsts any_int DD_REG
6195 bset {zero_const, 0}, %3
6197 with exact any_int sconsts DD_REG
6201 bset {zero_const, 0}, %3
6203 with any_int-sconsts genreg DD_REG
6206 bset {zero_const, 0}, %3
6208 with genreg any_int-sconsts DD_REG
6211 bset {zero_const, 0}, %3
6213 with exact immediate_int-sconsts imm_cmp_int DD_REG
6216 bset {zero_const, 0}, %3
6218 with exact imm_cmp_int immediate_int-sconsts DD_REG
6221 bset {zero_const, 0}, %3
6225 with exact sconsts any_int
6230 yields {extend1, %a}
6231 with exact any_int sconsts
6236 yields {extend1, %a}
6237 with any_int-sconsts genreg
6238 uses reusing %1,reusing %2,DD_REG
6242 yields {extend1, %a}
6243 with genreg any_int-sconsts
6244 uses reusing %1,reusing %2,DD_REG
6248 yields {extend1, %a}
6249 with exact extend1 extend1
6250 uses reusing %1,reusing %2,DD_REG
6254 yields {extend1, %a}
6255 with exact extend2 extend2
6256 uses reusing %1,reusing %2,DD_REG
6260 yields {extend1, %a}
6261 with exact immediate_int-sconsts imm_cmp_int
6262 uses reusing %2,DD_REG
6266 yields {extend1, %a}
6267 with exact imm_cmp_int immediate_int-sconsts
6268 uses reusing %1,DD_REG
6272 yields {extend1, %a}
6273 with exact immediate_int-sconsts STACK
6275 gen cmp_i %1, {post_inc_int, sp}
6278 yields {extend1, %a}
6279 with exact any_int STACK
6280 uses reusing %1,DD_REG=%1
6281 gen cmp_i {post_inc_int, sp}, %a
6284 yields {extend1, %a}
6287 gen move_i {post_inc_int, sp},%a
6288 cmp_i {post_inc_int, sp},%a
6291 yields {extend1, %a}
6293 pat cmi tlt and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("blt","bgt")
6294 pat cmi tle and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("ble","bge")
6295 pat cmi teq and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("beq","beq")
6296 pat cmi tne and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bne","bne")
6297 pat cmi tge and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bge","ble")
6298 pat cmi tgt and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bgt","blt")
6300 pat cmu tlt and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bcs","bhi")
6301 pat cmu tle and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bls","bcc")
6302 pat cmu teq and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("beq","beq")
6303 pat cmu tne and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bne","bne")
6304 pat cmu tge and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bcc","bls")
6305 pat cmu tgt and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bhi","bcs")
6307 pat cmi tlt ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bge","ble")
6308 pat cmi tle ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bgt","blt")
6309 pat cmi teq ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bne","bne")
6310 pat cmi tne ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("beq","beq")
6311 pat cmi tge ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("blt","bgt")
6312 pat cmi tgt ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("ble","bge")
6314 pat cmu tlt ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bcc","bls")
6315 pat cmu tle ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bhi","bcs")
6316 pat cmu teq ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bne","bne")
6317 pat cmu tne ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("beq","beq")
6318 pat cmu tge ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bcs","bhi")
6319 pat cmu tgt ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bls","bcc")
6321 pat cmi tlt $1==WORD_SIZE call cmxtxx("slt","sgt")
6322 pat cmi tle $1==WORD_SIZE call cmxtxx("sle","sge")
6323 pat cmi teq $1==WORD_SIZE call cmxtxx("seq","seq")
6324 pat cmi tne $1==WORD_SIZE call cmxtxx("sne","sne")
6325 pat cmi tge $1==WORD_SIZE call cmxtxx("sge","sle")
6326 pat cmi tgt $1==WORD_SIZE call cmxtxx("sgt","slt")
6328 pat cmu tlt $1==WORD_SIZE call cmxtxx("scs","shi")
6329 pat cmu tle $1==WORD_SIZE call cmxtxx("sls","scc")
6330 pat cmu teq $1==WORD_SIZE call cmxtxx("seq","seq")
6331 pat cmu tne $1==WORD_SIZE call cmxtxx("sne","sne")
6332 pat cmu tge $1==WORD_SIZE call cmxtxx("scc","sls")
6333 pat cmu tgt $1==WORD_SIZE call cmxtxx("shi","scs")
6336 proc cmuzxx example cmu zlt
6337 with exact sconsts any_int
6342 with exact any_int sconsts
6347 with any_int-sconsts genreg STACK
6350 with genreg any_int-sconsts STACK
6353 with exact immediate_int-sconsts imm_cmp_int
6357 with exact imm_cmp_int immediate_int-sconsts
6361 with exact immediate_int-sconsts STACK
6362 gen cmp_i %1, {post_inc_int, sp}
6364 with exact any_int STACK
6365 uses reusing %1, DD_REG=%1
6366 gen cmp_i {post_inc_int, sp}, %a
6370 gen move_i {post_inc_int, sp},%a
6371 cmp_i {post_inc_int, sp},%a
6373 with data2-sconsts dreg2 STACK
6376 with dreg2 data2-conreg2-sconsts STACK
6379 with data1 dreg1 STACK
6382 with dreg1 data1-conreg1 STACK
6386 pat cmu zlt $1==WORD_SIZE call cmuzxx("bcs","bhi")
6387 pat cmu zle $1==WORD_SIZE call cmuzxx("bls","bcc")
6388 pat cmu zeq $1==WORD_SIZE call cmuzxx("beq","beq")
6389 pat cmu zne $1==WORD_SIZE call cmuzxx("bne","bne")
6390 pat cmu zge $1==WORD_SIZE call cmuzxx("bcc","bls")
6391 pat cmu zgt $1==WORD_SIZE call cmuzxx("bhi","bcs")
6395 proc cmf4zxx example cmf zlt
6400 pat cmf zlt $1==4 call cmf4zxx("fblt")
6401 pat cmf zle $1==4 call cmf4zxx("fble")
6402 pat cmf zne $1==4 call cmf4zxx("fbne")
6403 pat cmf zeq $1==4 call cmf4zxx("fbeq")
6404 pat cmf zge $1==4 call cmf4zxx("fbge")
6405 pat cmf zgt $1==4 call cmf4zxx("fbgt")
6407 proc cmf8zxx example cmf zlt
6412 pat cmf zlt $1==8 call cmf8zxx("fblt")
6413 pat cmf zle $1==8 call cmf8zxx("fble")
6414 pat cmf zne $1==8 call cmf8zxx("fbne")
6415 pat cmf zeq $1==8 call cmf8zxx("fbeq")
6416 pat cmf zge $1==8 call cmf8zxx("fbge")
6417 pat cmf zgt $1==8 call cmf8zxx("fbgt")
6421 proc loc1locciibxx example loc loc cii bne
6422 with any1 extend1 STACK
6425 with any1 any_int STACK
6426 uses reusing %1, DD_REG = %1
6427 #if TBL68020 && WORD_SIZE==4
6438 pat loc loc cii blt $1==1 && $2==EM_WSIZE call loc1locciibxx("blt","bgt")
6439 pat loc loc cii ble $1==1 && $2==EM_WSIZE call loc1locciibxx("ble","bge")
6440 pat loc loc cii bne $1==1 && $2==EM_WSIZE call loc1locciibxx("bne","bne")
6441 pat loc loc cii beq $1==1 && $2==EM_WSIZE call loc1locciibxx("beq","beq")
6442 pat loc loc cii bge $1==1 && $2==EM_WSIZE call loc1locciibxx("bge","ble")
6443 pat loc loc cii bgt $1==1 && $2==EM_WSIZE call loc1locciibxx("bgt","blt")
6446 proc loc2locciibxx example loc loc cii bne
6447 with any2 extend2 STACK
6450 with any2 any4 STACK
6451 uses reusing %1, DD_REG = %1
6456 pat loc loc cii blt $1==2 && $2==EM_WSIZE call loc2locciibxx("blt","bgt")
6457 pat loc loc cii blt $1==2 && $2==EM_WSIZE call loc2locciibxx("blt","bgt")
6458 pat loc loc cii ble $1==2 && $2==EM_WSIZE call loc2locciibxx("ble","bge")
6459 pat loc loc cii bne $1==2 && $2==EM_WSIZE call loc2locciibxx("bne","bne")
6460 pat loc loc cii beq $1==2 && $2==EM_WSIZE call loc2locciibxx("beq","beq")
6461 pat loc loc cii bge $1==2 && $2==EM_WSIZE call loc2locciibxx("bge","ble")
6462 pat loc loc cii bgt $1==2 && $2==EM_WSIZE call loc2locciibxx("bgt","blt")
6465 proc bxx1_in example loc loc cii loc bne
6467 gen cmp_b {const, low8($4)}, %1
6471 proc bxx2_in example loc loc cii loc bne
6473 gen cmp_w {const, loww($4)}, %1
6477 proc bxx1_small example loc bne
6478 with imm_cmp1-D_REG STACK
6479 gen cmp_b {const, $1}, %1
6481 with imm_cmp2-D_REG STACK
6482 gen cmp_w {const, $1}, %1
6485 uses DD_REG = {small_const, $1} /* uses moveq */
6490 proc bxx2_small example loc bne
6491 with imm_cmp2-D_REG STACK
6492 gen cmp_w {const, $1}, %1
6495 gen cmp_l {const, $1}, %1
6499 proc zxx1_in example loc loc cii zne
6500 with test_set1 STACK
6504 gen test {dreg1, %1}
6508 proc zxx2_in example loc loc cii zne
6509 with test_set2 STACK
6513 gen test {dreg2, %1}
6517 pat loc loc cii zlt $1==1 && $2==WORD_SIZE call zxx1_in("blt")
6518 pat loc loc cii zle $1==1 && $2==WORD_SIZE call zxx1_in("ble")
6519 pat loc loc cii zne $1==1 && $2==WORD_SIZE call zxx1_in("bne")
6520 pat loc loc cii zeq $1==1 && $2==WORD_SIZE call zxx1_in("beq")
6521 pat loc loc cii zge $1==1 && $2==WORD_SIZE call zxx1_in("bge")
6522 pat loc loc cii zgt $1==1 && $2==WORD_SIZE call zxx1_in("bgt")
6525 pat loc loc cii zlt $1==2 && $2==4 call zxx2_in("blt")
6526 pat loc loc cii zle $1==2 && $2==4 call zxx2_in("ble")
6527 pat loc loc cii zne $1==2 && $2==4 call zxx2_in("bne")
6528 pat loc loc cii zeq $1==2 && $2==4 call zxx2_in("beq")
6529 pat loc loc cii zge $1==2 && $2==4 call zxx2_in("bge")
6530 pat loc loc cii zgt $1==2 && $2==4 call zxx2_in("bgt")
6533 pat loc loc cii loc blt $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("blt")
6534 pat loc loc cii loc ble $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("ble")
6535 pat loc loc cii loc beq $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("beq")
6536 pat loc loc cii loc bne $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("bne")
6537 pat loc loc cii loc bge $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("bge")
6538 pat loc loc cii loc bgt $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("bgt")
6541 pat loc loc cii loc blt $1==2 && $2==4 && in_2($4) call bxx2_in("blt")
6542 pat loc loc cii loc ble $1==2 && $2==4 && in_2($4) call bxx2_in("ble")
6543 pat loc loc cii loc beq $1==2 && $2==4 && in_2($4) call bxx2_in("beq")
6544 pat loc loc cii loc bne $1==2 && $2==4 && in_2($4) call bxx2_in("bne")
6545 pat loc loc cii loc bge $1==2 && $2==4 && in_2($4) call bxx2_in("bge")
6546 pat loc loc cii loc bgt $1==2 && $2==4 && in_2($4) call bxx2_in("bgt")
6549 /* the second instruction for bxx1_small is the other way around! */
6550 pat loc blt $1>=0 && $1<128 call bxx1_small("bcs", "bgt")
6551 pat loc ble $1>=0 && $1<128 call bxx1_small("bls", "bge")
6552 pat loc beq $1>=0 && $1<128 call bxx1_small("beq", "beq")
6553 pat loc bne $1>=0 && $1<128 call bxx1_small("bne", "bne")
6554 pat loc bge $1>=0 && $1<128 call bxx1_small("bcc", "ble")
6555 pat loc bgt $1>=0 && $1<128 call bxx1_small("bhi", "blt")
6558 pat loc blt $1>=128 && $1<32768 call bxx2_small("bcs", "blt")
6559 pat loc ble $1>=128 && $1<32768 call bxx2_small("bls", "ble")
6560 pat loc beq $1>=128 && $1<32768 call bxx2_small("beq", "beq")
6561 pat loc bne $1>=128 && $1<32768 call bxx2_small("bne", "bne")
6562 pat loc bge $1>=128 && $1<32768 call bxx2_small("bcc", "bge")
6563 pat loc bgt $1>=128 && $1<32768 call bxx2_small("bhi", "bgt")
6567 pat loc loc cii lal sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
6568 leaving lal $4 sti $5
6569 pat loc loc cii lol sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
6570 leaving lol $4 sti $5
6571 pat loc loc cii lil sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
6572 leaving lil $4 sti $5
6573 pat loc loc cii LLP lof sti $1 <= WORD_SIZE && $1>=$6 && $2==WORD_SIZE
6574 leaving LLP $4 lof $5 sti $6
6575 pat loc loc cii lae sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
6576 leaving lae $4 sti $5
6577 pat loc loc cii loe sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
6578 leaving loe $4 sti $5
6580 pat loc loc cii stl $1==1 && $2==WORD_SIZE && inreg($4)==reg_any
6582 kills regvar($4, reg_any), use_index %xreg==regvar($4, reg_any)
6583 gen move_b %1, {dreg1, regvar($4,reg_any)}
6589 #else /* TBL68020 */
6592 #endif /* TBL68020 */
6595 pat loc loc cii $1==2 && $2==4
6598 uses reusing %1, DD_REG4
6599 gen move %1,%a.1 yields {extend2, %a}
6601 uses reusing %1,DD_REG4
6602 gen move %1.reg,%a.1 yields {extend1_4, %a}
6604 uses reusing %1,DD_REG4
6605 gen move %1, %a.1 yields {extend2, %a}
6607 with DD_REG yields {extend2, %1}
6609 uses reusing %1,DD_REG=%1
6610 yields {extend2, %a}
6613 pat loc loc cii $1==1 && $2==WORD_SIZE
6614 with DD_REG yields {extend1, %1}
6616 uses reusing %1,DD_REG = %1
6617 yields {extend1, %a}
6620 pat loc loc cii $1==1 && $2==4
6622 uses reusing %1, DD_REG4
6624 yields {extend1_4, %a}
6626 uses reusing %1,DD_REG4
6627 gen move %1,%a.1 yields {extend1_4, %a}
6630 pat loc loc ciu $1==$2 /* skip this */
6631 pat loc loc cui $1==$2 /* skip this */
6634 /* The following rules should be handled by the peephole optimizer, I think */
6637 pat ldc dvu highw($1)==0 && loww($1)==2 && $2==4 leaving loc 1 sru 4
6638 pat ldc dvu highw($1)==0 && loww($1)==4 && $2==4 leaving loc 2 sru 4
6639 pat ldc dvu highw($1)==0 && loww($1)==8 && $2==4 leaving loc 3 sru 4
6640 pat ldc dvu highw($1)==0 && loww($1)==16 && $2==4 leaving loc 4 sru 4
6641 pat ldc dvu highw($1)==0 && loww($1)==32 && $2==4 leaving loc 5 sru 4
6642 pat ldc dvu highw($1)==0 && loww($1)==64 && $2==4 leaving loc 6 sru 4
6643 pat ldc dvu highw($1)==0 && loww($1)==128 && $2==4 leaving loc 7 sru 4
6644 pat ldc dvu highw($1)==0 && loww($1)==256 && $2==4 leaving loc 8 sru 4
6647 pat loc dvu $1==2 && $2==WORD_SIZE leaving loc 1 sru WORD_SIZE
6648 pat loc dvu $1==4 && $2==WORD_SIZE leaving loc 2 sru WORD_SIZE
6649 pat loc dvu $1==8 && $2==WORD_SIZE leaving loc 3 sru WORD_SIZE
6650 pat loc dvu $1==16 && $2==WORD_SIZE leaving loc 4 sru WORD_SIZE
6651 pat loc dvu $1==32 && $2==WORD_SIZE leaving loc 5 sru WORD_SIZE
6652 pat loc dvu $1==64 && $2==WORD_SIZE leaving loc 6 sru WORD_SIZE
6653 pat loc dvu $1==128 && $2==WORD_SIZE leaving loc 7 sru WORD_SIZE
6654 pat loc dvu $1==256 && $2==WORD_SIZE leaving loc 8 sru WORD_SIZE
6657 pat ldc dvi highw($1)==0 && loww($1)==2 && $2==4
6661 add_l {const4,loww($1)-1},%1
6662 1: yields %1 leaving loc 1 sri 4
6664 pat ldc dvi highw($1)==0 && loww($1)==4 && $2==4
6668 add_l {const4,loww($1)-1},%1
6669 1: yields %1 leaving loc 2 sri 4
6671 pat ldc dvi highw($1)==0 && loww($1)==8 && $2==4
6675 add_l {const4,loww($1)-1},%1
6676 1: yields %1 leaving loc 3 sri 4
6678 pat ldc dvi highw($1)==0 && loww($1)==16 && $2==4
6682 add_l {const4,loww($1)-1},%1
6683 1: yields %1 leaving loc 4 sri 4
6685 pat ldc dvi highw($1)==0 && loww($1)==32 && $2==4
6689 add_l {const4,loww($1)-1},%1
6690 1: yields %1 leaving loc 5 sri 4
6692 pat ldc dvi highw($1)==0 && loww($1)==64 && $2==4
6696 add_l {const4,loww($1)-1},%1
6697 1: yields %1 leaving loc 6 sri 4
6699 pat ldc dvi highw($1)==0 && loww($1)==128 && $2==4
6703 add_l {const4,loww($1)-1},%1
6704 1: yields %1 leaving loc 7 sri 4
6706 pat ldc dvi highw($1)==0 && loww($1)==256 && $2==4
6710 add_l {const4,loww($1)-1},%1
6711 1: yields %1 leaving loc 8 sri 4
6712 #endif /* WORD_SIZE==2 */
6714 pat loc dvi $1==2 && $2==WORD_SIZE
6718 add_i {const,$1-1},%1
6719 1: yields %1 leaving loc 1 sri WORD_SIZE
6721 pat loc dvi $1==4 && $2==WORD_SIZE
6725 add_i {const,$1-1},%1
6726 1: yields %1 leaving loc 2 sri WORD_SIZE
6728 pat loc dvi $1==8 && $2==WORD_SIZE
6732 add_i {const,$1-1},%1
6733 1: yields %1 leaving loc 3 sri WORD_SIZE
6735 pat loc dvi $1==16 && $2==WORD_SIZE
6739 add_i {const,$1-1},%1
6740 1: yields %1 leaving loc 4 sri WORD_SIZE
6742 pat loc dvi $1==32 && $2==WORD_SIZE
6746 add_i {const,$1-1},%1
6747 1: yields %1 leaving loc 5 sri WORD_SIZE
6749 pat loc dvi $1==64 && $2==WORD_SIZE
6753 add_i {const,$1-1},%1
6754 1: yields %1 leaving loc 6 sri WORD_SIZE
6756 pat loc dvi $1==128 && $2==WORD_SIZE
6760 add_i {const,$1-1},%1
6761 1: yields %1 leaving loc 7 sri WORD_SIZE
6763 pat loc dvi $1==256 && $2==WORD_SIZE
6767 add_i {const,$1-1},%1
6768 1: yields %1 leaving loc 8 sri WORD_SIZE
6770 /* The rest is all 2-bytes stuff */
6772 pat loc loc cii $1==4 && $2==2
6775 with any2-pre_post any2-pre_post
6779 with exact sconsts4 any4
6784 yields {extend1, %a.1}
6785 with exact any4 sconsts4
6790 yields {extend1, %a.1}
6791 with any4-sconsts4 genreg4
6792 uses reusing %1,reusing %2,DD_REG4
6796 yields {extend1, %a.1}
6797 with genreg4 any4-sconsts4
6798 uses reusing %1,reusing %2,DD_REG4
6802 yields {extend1, %a.1}
6803 with exact extend1_4 extend1_4
6804 uses reusing %1,reusing %2,DD_REG4
6808 yields {extend1, %a.1}
6809 with exact extend2 extend2
6810 uses reusing %1,reusing %2,DD_REG4
6814 yields {extend1, %a.1}
6815 with exact immediate4-sconsts4 imm_cmp4
6816 uses reusing %2,DD_REG4
6820 yields {extend1, %a.1}
6821 with exact imm_cmp4 immediate4-sconsts4
6822 uses reusing %1,DD_REG4
6826 yields {extend1, %a.1}
6827 with exact immediate4-sconsts4 STACK
6829 gen cmp_l %1, {post_inc4, sp}
6832 yields {extend1, %a.1}
6833 with exact any4 STACK
6834 uses reusing %1,DD_REG4=%1
6835 gen cmp_l {post_inc4, sp}, %a
6838 yields {extend1, %a.1}
6841 gen move_l {post_inc4, sp},%a
6842 cmp_l {post_inc4, sp},%a
6845 yields {extend1, %a.1}
6847 pat cmi tlt $1==4 call cmqtxx("slt","sgt")
6848 pat cmi tle $1==4 call cmqtxx("sle","sge")
6849 pat cmi teq $1==4 call cmqtxx("seq","seq")
6850 pat cmi tne $1==4 call cmqtxx("sne","sne")
6851 pat cmi tge $1==4 call cmqtxx("sge","sle")
6852 pat cmi tgt $1==4 call cmqtxx("sgt","slt")
6854 pat cmu tlt $1==4 call cmqtxx("scs","shi")
6855 pat cmu tle $1==4 call cmqtxx("sls","scc")
6856 pat cmu teq $1==4 call cmqtxx("seq","seq")
6857 pat cmu tne $1==4 call cmqtxx("sne","sne")
6858 pat cmu tge $1==4 call cmqtxx("scc","sls")
6859 pat cmu tgt $1==4 call cmqtxx("shi","scs")
6862 proc cmqzxx example cmu zlt
6863 with zero_const4 test_set4 STACK
6867 with exact sconsts4-zero_const4 any4
6872 with exact any4 sconsts4
6877 with any4-sconsts4-zero_const4 genreg4 STACK
6880 with genreg4 any4-sconsts4-zero_const4 STACK
6883 with exact immediate4-sconsts4-zero_const4 imm_cmp4
6887 with exact imm_cmp4 immediate4-sconsts4-zero_const4
6891 with exact immediate4-sconsts4-zero_const4 STACK
6892 gen cmp_l %1, {post_inc4, sp}
6894 with exact any4 STACK
6895 uses reusing %1, DD_REG4=%1
6896 gen cmp_l {post_inc4, sp}, %a
6900 gen move_l {post_inc4, sp},%a
6901 cmp_l {post_inc4, sp},%a
6903 with data2-sconsts dreg2 STACK
6906 with dreg2 data2-conreg2-sconsts STACK
6909 with data1 dreg1 STACK
6912 with dreg1 data1-conreg1 STACK
6916 pat cmi zlt $1==4 call cmqzxx("blt","bgt")
6917 pat cmi zle $1==4 call cmqzxx("ble","bge")
6918 pat cmi zeq $1==4 call cmqzxx("beq","beq")
6919 pat cmi zne $1==4 call cmqzxx("bne","bne")
6920 pat cmi zge $1==4 call cmqzxx("bge","ble")
6921 pat cmi zgt $1==4 call cmqzxx("bgt","blt")
6923 pat cms zeq $1==4 call cmqzxx("beq","beq")
6924 pat cms zne $1==4 call cmqzxx("bne","bne")
6926 pat cmu zlt $1==4 call cmqzxx("bcs","bhi")
6927 pat cmu zle $1==4 call cmqzxx("bls","bcc")
6928 pat cmu zeq $1==4 call cmqzxx("beq","beq")
6929 pat cmu zne $1==4 call cmqzxx("bne","bne")
6930 pat cmu zge $1==4 call cmqzxx("bcc","bls")
6931 pat cmu zgt $1==4 call cmqzxx("bhi","bcs")
6933 pat ldc cms zeq loww($1)==0 && highw($1)==0 && $2==4
6934 with test_set4 STACK
6938 pat ldc cms zne loww($1)==0 && highw($1)==0 && $2==4
6939 with test_set4 STACK