mach/i80/as/mach4.c

   1 #define RCSID4 "$Id: mach4.c,v 3.3 1994/06/24 12:57:48 ceriel Exp $"
   2
   3 /*
   4  * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
   5  * See the copyright notice in the ACK home directory, in the file "Copyright".
   6  *
   7  */
   8
   9 /*
  10  * Intel 8080 parsing rules
  11  */
  12 operation
  13         :       NOOPOP
  14                         {       emit1($1);}
  15         |
  16                 D8OP expr
  17                         {       emit1($1);
  18 #ifdef RELOCATION
  19                                 newrelo($2.typ, RELO1);
  20 #endif
  21                                 emit1($2.val);
  22                         }
  23         |
  24                 D16OP expr
  25                         {       emit1($1);
  26 #ifdef RELOCATION
  27                                 newrelo($2.typ, RELO2);
  28 #endif
  29                                 emit2($2.val);
  30                         }
  31         |
  32                 R16OP r16
  33                         {       emit1($1 | ($2 << 3));}
  34         |
  35                 MOV r8 ',' r8
  36                         {       if ($2 == M && $4 == M)
  37                                         serror("register error");
  38                                 emit1($1 | ($2 << 3) | $4);
  39                         }
  40         |
  41                 MVI r8 ',' expr
  42                         {       emit1($1 | ($2 << 3));
  43 #ifdef RELOCATION
  44                                 newrelo($4.typ, RELO1);
  45 #endif
  46                                 emit1($4.val);
  47                         }
  48         |
  49                 LXI r16 ',' expr
  50                         {       emit1($1 | ($2 << 3));
  51 #ifdef RELOCATION
  52                                 newrelo($4.typ, RELO2);
  53 #endif
  54                                 emit2($4.val);
  55                         }
  56         |
  57                 SRCOP r8
  58                         {       emit1($1 | $2);}
  59         |
  60                 DSTOP r8
  61                         {       emit1($1 | ($2 << 3));}
  62         |
  63                 RST absexp
  64                         {       fit(fit3($2));
  65                                 emit1($1 | (low3($2) << 3));
  66                         }
  67         |
  68                 STLDAX r16
  69                         {
  70                                 if ($2 != B && $2 != D)
  71                                         serror("register error");
  72                                 emit1($1 | (($2 & 02) << 3));
  73                         }
  74         ;
  75 r16     :       REG
  76                         {       if ($1 & ~06)
  77                                         serror("register error");
  78                                 $$ = $1 & 06;
  79                         }
  80         ;
  81 r8      :       REG
  82                         {       if (($1 & ~07) != 0)
  83                                         serror("register error");
  84                                 $$ = $1 & 07;
  85                         }
  86         ;