mach/6805/as/mach3.c

   1 /*
   2  * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
   3  * See the copyright notice in the ACK home directory, in the file "Copyright".
   4  */
   5 #define RCSID3 "$Id: mach3.c,v 0.3 1994/06/24 12:55:50 ceriel Exp $"
   6
   7 /*
   8  * Motorola 6805 keywords
   9  */
  10 /*
  11  * The X register
  12  */
  13 0,      X,              0,              "x",
  14 /*
  15  * Bit test and branch
  16  */
  17 0,      BBRANCH,        0x00,           "brset",
  18 0,      BBRANCH,        0x01,           "brclr",
  19 /*
  20  * Bit manipulation
  21  */
  22 0,      BIT,            0x10,           "bset",
  23 0,      BIT,            0x11,           "bclr",
  24 /*
  25  * Branches
  26  */
  27 0,      BRANCH,         0x20,           "bra",
  28 0,      BRANCH,         0x21,           "brn",
  29 0,      BRANCH,         0x22,           "bhi",
  30 0,      BRANCH,         0x23,           "bls",
  31 0,      BRANCH,         0x24,           "bcc",
  32 0,      BRANCH,         0x25,           "bcs",
  33 0,      BRANCH,         0x26,           "bne",
  34 0,      BRANCH,         0x27,           "beq",
  35 0,      BRANCH,         0x28,           "bhcc",
  36 0,      BRANCH,         0x29,           "bhcs",
  37 0,      BRANCH,         0x2a,           "bpl",
  38 0,      BRANCH,         0x2b,           "bmi",
  39 0,      BRANCH,         0x2c,           "bmc",
  40 0,      BRANCH,         0x2d,           "bms",
  41 0,      BRANCH,         0x2e,           "bil",
  42 0,      BRANCH,         0x2f,           "bih",
  43 /*
  44  * Read modify write on anything but registers
  45  */
  46 0,      RMR,            0x30,           "neg",
  47 0,      RMR,            0x33,           "com",
  48 0,      RMR,            0x34,           "lsr",
  49 0,      RMR,            0x36,           "ror",
  50 0,      RMR,            0x36,           "asr",
  51 0,      RMR,            0x38,           "lsl",
  52 0,      RMR,            0x39,           "rol",
  53 0,      RMR,            0x3a,           "dec",
  54 0,      RMR,            0x3c,           "inc",
  55 0,      RMR,            0x3d,           "tst",
  56 0,      RMR,            0x3f,           "clr",
  57 /*
  58  * Implied stuff
  59  */
  60 0,      NOARG,          0x80,           "rti",
  61 0,      NOARG,          0x81,           "rts",
  62 0,      NOARG,          0x83,           "swi",
  63 0,      NOARG,          0x97,           "tax",
  64 0,      NOARG,          0x98,           "clc",
  65 0,      NOARG,          0x99,           "sec",
  66 0,      NOARG,          0x9a,           "cli",
  67 0,      NOARG,          0x9b,           "sei",
  68 0,      NOARG,          0x9c,           "rsp",
  69 0,      NOARG,          0x9d,           "nop",
  70 0,      NOARG,          0x9f,           "txa",
  71 /*
  72  * Register memory.
  73  * Warning. Some imediate opcodes excluded in parser actions.
  74  */
  75 0,      RM,             0xa0,           "sub",
  76 0,      RM,             0xa1,           "cmp",
  77 0,      RM,             0xa2,           "sbc",
  78 0,      RM,             0xa3,           "cpx",
  79 0,      RM,             0xa4,           "and",
  80 0,      RM,             0xa5,           "bit",
  81 0,      RM,             0xa6,           "lda",
  82 0,      RM,             0xa7,           "sta",
  83 0,      RM,             0xa8,           "eor",
  84 0,      RM,             0xa9,           "adc",
  85 0,      RM,             0xaa,           "ora",
  86 0,      RM,             0xab,           "add",
  87 0,      RM,             0xac,           "jmp",
  88 0,      BRANCH,         0xad,           "bsr",
  89 0,      RM,             0xad,           "jsr",
  90 0,      RM,             0xae,           "ldx",
  91 0,      RM,             0xaf,           "stx",
  92 /*
  93  * Branch synonyms
  94  */
  95 0,      BRANCH,         0x24,           "bhs",  /* bcc */
  96 0,      BRANCH,         0x25,           "blo",  /* bcs */
  97 /*
  98  * Brain damaged concatenated opcodes for RMR on registers
  99  */
 100 0,      NOARG,          0x40,           "nega",
 101 0,      NOARG,          0x43,           "coma",
 102 0,      NOARG,          0x44,           "lsra",
 103 0,      NOARG,          0x46,           "rora",
 104 0,      NOARG,          0x47,           "asra",
 105 0,      NOARG,          0x48,           "lsla",
 106 0,      NOARG,          0x49,           "rola",
 107 0,      NOARG,          0x4a,           "deca",
 108 0,      NOARG,          0x4c,           "inca",
 109 0,      NOARG,          0x4d,           "tsta",
 110 0,      NOARG,          0x4f,           "clra",
 111 0,      NOARG,          0x50,           "negx",
 112 0,      NOARG,          0x53,           "comx",
 113 0,      NOARG,          0x54,           "lsrx",
 114 0,      NOARG,          0x56,           "rorx",
 115 0,      NOARG,          0x57,           "asrx",
 116 0,      NOARG,          0x58,           "lslx",
 117 0,      NOARG,          0x59,           "rolx",
 118 0,      NOARG,          0x5a,           "decx",
 119 0,      NOARG,          0x5c,           "incx",
 120 0,      NOARG,          0x5d,           "tstx",
 121 0,      NOARG,          0x5f,           "clrx",
 122 /*
 123  * CMOS support
 124  */
 125 0,      CMOS,           0,              ".cmos",
 126 0,      CMOS,           0x8e,           "stop",
 127 0,      CMOS,           0x8f,           "wait",