Initial Commit - share my KiCad library on GitHub

[my_kicad_library.git] / My_Components.pretty / Cap_Cer_762.kicad_mod

diff --git a/My_Components.pretty/Cap_Cer_762.kicad_mod b/My_Components.pretty/Cap_Cer_762.kicad_mod
new file mode 100644 (file)
index 0000000..370b04c
--- /dev/null
+++ b/My_Components.pretty/Cap_Cer_762.kicad_mod
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+(module Cap_Cer_762 (layer F.Cu) (tedit 55B336B3)\r
+  (descr "Ceramic Capacitor, 7.62mm lead spacing")\r
+  (tags CAPACITOR)\r
+  (autoplace_cost180 10)\r
+  (fp_text reference REF* (at 0 -2.54) (layer F.SilkS)\r
+    (effects (font (size 1.016 1.016) (thickness 0.2032)))\r
+  )\r
+  (fp_text value VAL* (at 0 2.54) (layer F.SilkS)\r
+    (effects (font (size 1.016 0.9144) (thickness 0.2032) italic))\r
+  )\r
+  (fp_line (start 1.6 -1.25) (end -1.6 -1.25) (layer F.SilkS) (width 0.254))\r
+  (fp_line (start 1.9 0.95) (end 1.9 -0.95) (layer F.SilkS) (width 0.254))\r
+  (fp_line (start -1.6 1.25) (end 1.6 1.25) (layer F.SilkS) (width 0.254))\r
+  (fp_line (start -1.9 -0.95) (end -1.9 0.95) (layer F.SilkS) (width 0.254))\r
+  (fp_arc (start 1.6 0.95) (end 1.9 0.95) (angle 90) (layer F.SilkS) (width 0.254))\r
+  (fp_arc (start 1.6 -0.95) (end 1.6 -1.25) (angle 90) (layer F.SilkS) (width 0.254))\r
+  (fp_arc (start -1.6 0.95) (end -1.6 1.25) (angle 90) (layer F.SilkS) (width 0.254))\r
+  (fp_line (start 1.9 0) (end 3.8 0) (layer F.SilkS) (width 0.254))\r
+  (fp_line (start -3.8 0) (end -1.9 0) (layer F.SilkS) (width 0.254))\r
+  (fp_arc (start -1.6 -0.95) (end -1.9 -0.95) (angle 90) (layer F.SilkS) (width 0.254))\r
+  (pad 1 thru_hole circle (at -3.81 0) (size 1.397 1.397) (drill 0.8128) (layers *.Cu *.Mask F.SilkS))\r
+  (pad 2 thru_hole circle (at 3.81 0) (size 1.397 1.397) (drill 0.8128) (layers *.Cu *.Mask F.SilkS))\r
+  (model discret/resistor.wrl\r
+    (at (xyz 0 0 0))\r
+    (scale (xyz 0.3 0.3 0.3))\r
+    (rotate (xyz 0 0 0))\r
+  )\r
+)\r