From fd4f548d6ef19e4a47ef04f30b7c7e25901a2740 Mon Sep 17 00:00:00 2001
From: ceriel <none@none>
Date: Thu, 20 Aug 1987 15:30:01 +0000
Subject: [PATCH] fixed addition, better patterns for SDL, SDE

---
 mach/i86/cg/table | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/mach/i86/cg/table b/mach/i86/cg/table
index 83483dac8..6869e6618 100644
--- a/mach/i86/cg/table
+++ b/mach/i86/cg/table
@@ -530,8 +530,10 @@ sts $1==2	| X_CXREG X_BXREG |
 			remove(ALL)
 			"call .sti"
 			erase(%[1]) erase(%[2]) 		|	| |
-sdl		|	  |			  |	| stl $1 stl $1+2 |
-sde		|	  |			  |  | ste $1 ste $1+"+2" |
+sdl		| regorconst regorconst  |  | %[2] %[1]  | stl $1 stl $1+2 |
+...		| nocoercions: STACK |	| | stl $1 stl $1+2 |
+sde		| regorconst regorconst  |  | %[2] %[1]  | ste $1 ste $1+"+2" |
+...		| nocoercions: STACK |	| | ste $1 ste $1+"+2" |
 sdf		| addreg regorconst regorconst |
 			remove(referals)
 			move(%[2],{ind_regoff2,%[1],tostring($1)})
@@ -1155,7 +1157,7 @@ lol loc sli stl $1==$4 && $2==2 && $3==2 && inreg($1)==2 | |
 lol loc sli stl $1==$4 && $3==2 && inreg($1)==2 | |
 			remove(regvar($1))
 			allocate(CXREG = {ANYCON, $2})
-			"sar %(regvar($1)%),cl"
+			"sal %(regvar($1)%),cl"
 			setcc(regvar($1))		| | |
 lol loc sri stl $1==$4 && $2==1 && $3==2 && inreg($1)==2 | |
 			remove(regvar($1))
-- 
2.34.1