From 972d39139d679a77c1869be728d6e054afed96b8 Mon Sep 17 00:00:00 2001 From: ceriel Date: Mon, 19 Feb 1990 16:38:35 +0000 Subject: [PATCH] Added some patterns for shifts with constant shift count --- mach/i86/ncg/table | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/mach/i86/ncg/table b/mach/i86/ncg/table index b5d19db8d..cec0bfe1d 100644 --- a/mach/i86/ncg/table +++ b/mach/i86/ncg/table @@ -986,6 +986,22 @@ with REG REG gen sal %1,{ANYCON,1} rcl %2,{ANYCON,1} yields %2 %1 +pat loc sli $1==2 && $2==4 +with REG REG + gen sal %1,{ANYCON,1} + rcl %2,{ANYCON,1} + sal %1,{ANYCON,1} + rcl %2,{ANYCON,1} yields %2 %1 + +pat loc sli $1==3 && $2==4 +with REG REG + gen sal %1,{ANYCON,1} + rcl %2,{ANYCON,1} + sal %1,{ANYCON,1} + rcl %2,{ANYCON,1} + sal %1,{ANYCON,1} + rcl %2,{ANYCON,1} yields %2 %1 + pat loc sli $1==16 && $2==4 with rmorconst rmorconst yields %1 {ANYCON,0} @@ -1019,6 +1035,22 @@ with REG REG gen sar %2,{ANYCON,1} rcr %1,{ANYCON,1} yields %2 %1 +pat loc sri $1==2 && $2==4 +with REG REG + gen sar %2,{ANYCON,1} + rcr %1,{ANYCON,1} + sar %2,{ANYCON,1} + rcr %1,{ANYCON,1} yields %2 %1 + +pat loc sri $1==3 && $2==4 +with REG REG + gen sar %2,{ANYCON,1} + rcr %1,{ANYCON,1} + sar %2,{ANYCON,1} + rcr %1,{ANYCON,1} + sar %2,{ANYCON,1} + rcr %1,{ANYCON,1} yields %2 %1 + pat sri $1==2 with SHIFT_CREG REG gen sar %2,cl yields %2 -- 2.34.1