From 7ac08838b328fcd40a35033d7e85c527d9a5e5b0 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Fri, 9 Oct 2015 16:13:44 +0100 Subject: [PATCH] zeta_v2: platform_ide --- Kernel/platform-zeta-v2/config.h | 35 ------------------------ Kernel/platform-zeta-v2/platform_ide.h | 38 ++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 35 deletions(-) create mode 100644 Kernel/platform-zeta-v2/platform_ide.h diff --git a/Kernel/platform-zeta-v2/config.h b/Kernel/platform-zeta-v2/config.h index cfded83c..fe90175e 100644 --- a/Kernel/platform-zeta-v2/config.h +++ b/Kernel/platform-zeta-v2/config.h @@ -52,41 +52,6 @@ /* PPIDE support */ #define CONFIG_PPIDE /* #define CONFIG_PPIDE to enable IDE on 8255A */ -#ifdef CONFIG_PPIDE -#define PPIDE_BASE 0x60 /* Base address of 8255A */ -#define IDE_REG_INDIRECT /* IDE registers are not directly connected to the CPU bus */ - -/* IDE control signal to 8255 port C mapping */ -#define PPIDE_A0_LINE 0x01 // Direct from 8255 to IDE interface -#define PPIDE_A1_LINE 0x02 // Direct from 8255 to IDE interface -#define PPIDE_A2_LINE 0x04 // Direct from 8255 to IDE interface -#define PPIDE_CS0_LINE 0x08 // Inverter between 8255 and IDE interface -#define PPIDE_CS1_LINE 0x10 // Inverter between 8255 and IDE interface -#define PPIDE_WR_LINE 0x20 // Inverter between 8255 and IDE interface -#define PPIDE_WR_BIT 5 // (1 << PPIDE_WR_BIT) = PPIDE_WR_LINE -#define PPIDE_RD_LINE 0x40 // Inverter between 8255 and IDE interface -#define PPIDE_RD_BIT 6 // (1 << PPIDE_RD_BIT) = PPIDE_RD_LINE -#define PPIDE_RST_LINE 0x80 // Inverter between 8255 and IDE interface - -/* 8255 configuration */ -#define PPIDE_PPI_BUS_READ 0x92 -#define PPIDE_PPI_BUS_WRITE 0x80 - -/* IDE register addresses */ -#define ide_reg_data (PPIDE_CS0_LINE) -#define ide_reg_error (PPIDE_CS0_LINE | PPIDE_A0_LINE) -#define ide_reg_features (PPIDE_CS0_LINE | PPIDE_A0_LINE) -#define ide_reg_sec_count (PPIDE_CS0_LINE | PPIDE_A1_LINE) -#define ide_reg_lba_0 (PPIDE_CS0_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE) -#define ide_reg_lba_1 (PPIDE_CS0_LINE | PPIDE_A2_LINE) -#define ide_reg_lba_2 (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A0_LINE) -#define ide_reg_lba_3 (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE) -#define ide_reg_devhead (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE) -#define ide_reg_command (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE) -#define ide_reg_status (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE) -#define ide_reg_altstatus (PPIDE_CS1_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE) -#define ide_reg_control (PPIDE_CS1_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE) -#endif /* CONFIG_PPIDE */ /* Optional ParPortProp board connected to PPI */ //#define CONFIG_PPP /* #define CONFIG_PPP to enable as tty3 */ diff --git a/Kernel/platform-zeta-v2/platform_ide.h b/Kernel/platform-zeta-v2/platform_ide.h new file mode 100644 index 00000000..95d67e15 --- /dev/null +++ b/Kernel/platform-zeta-v2/platform_ide.h @@ -0,0 +1,38 @@ +#ifdef CONFIG_PPIDE +#define PPIDE_BASE 0x60 /* Base address of 8255A */ +#define IDE_REG_INDIRECT /* IDE registers are not directly connected to the CPU bus */ + +/* IDE control signal to 8255 port C mapping */ +#define PPIDE_A0_LINE 0x01 // Direct from 8255 to IDE interface +#define PPIDE_A1_LINE 0x02 // Direct from 8255 to IDE interface +#define PPIDE_A2_LINE 0x04 // Direct from 8255 to IDE interface +#define PPIDE_CS0_LINE 0x08 // Inverter between 8255 and IDE interface +#define PPIDE_CS1_LINE 0x10 // Inverter between 8255 and IDE interface +#define PPIDE_WR_LINE 0x20 // Inverter between 8255 and IDE interface +#define PPIDE_WR_BIT 5 // (1 << PPIDE_WR_BIT) = PPIDE_WR_LINE +#define PPIDE_RD_LINE 0x40 // Inverter between 8255 and IDE interface +#define PPIDE_RD_BIT 6 // (1 << PPIDE_RD_BIT) = PPIDE_RD_LINE +#define PPIDE_RST_LINE 0x80 // Inverter between 8255 and IDE interface + +/* 8255 configuration */ +#define PPIDE_PPI_BUS_READ 0x92 +#define PPIDE_PPI_BUS_WRITE 0x80 + +/* IDE register addresses */ +#define ide_reg_data (PPIDE_CS0_LINE) +#define ide_reg_error (PPIDE_CS0_LINE | PPIDE_A0_LINE) +#define ide_reg_features (PPIDE_CS0_LINE | PPIDE_A0_LINE) +#define ide_reg_sec_count (PPIDE_CS0_LINE | PPIDE_A1_LINE) +#define ide_reg_lba_0 (PPIDE_CS0_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE) +#define ide_reg_lba_1 (PPIDE_CS0_LINE | PPIDE_A2_LINE) +#define ide_reg_lba_2 (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A0_LINE) +#define ide_reg_lba_3 (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE) +#define ide_reg_devhead (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE) +#define ide_reg_command (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE) +#define ide_reg_status (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE) +#define ide_reg_altstatus (PPIDE_CS1_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE) +#define ide_reg_control (PPIDE_CS1_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE) +#endif /* CONFIG_PPIDE */ + +#define ide_select(x) +#define ide_deselect() -- 2.34.1