From 75f8e3fdc17146de073971acff60c7c6d2c5e908 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Sun, 24 Feb 2019 21:43:02 +0000 Subject: [PATCH] yaz180: ppide changes In theory this gets us a kernel that will work on a Yaz180. --- Kernel/platform-yaz180/platform_ide.h | 18 +++++++-------- Kernel/platform-yaz180/ppide.c | 33 +++++++++++++++++---------- 2 files changed, 30 insertions(+), 21 deletions(-) diff --git a/Kernel/platform-yaz180/platform_ide.h b/Kernel/platform-yaz180/platform_ide.h index 95d67e15..7bce05ad 100644 --- a/Kernel/platform-yaz180/platform_ide.h +++ b/Kernel/platform-yaz180/platform_ide.h @@ -1,17 +1,17 @@ #ifdef CONFIG_PPIDE -#define PPIDE_BASE 0x60 /* Base address of 8255A */ +#define PPIDE_BASE 0x4000 /* Base address of 8255A */ #define IDE_REG_INDIRECT /* IDE registers are not directly connected to the CPU bus */ /* IDE control signal to 8255 port C mapping */ -#define PPIDE_A0_LINE 0x01 // Direct from 8255 to IDE interface -#define PPIDE_A1_LINE 0x02 // Direct from 8255 to IDE interface -#define PPIDE_A2_LINE 0x04 // Direct from 8255 to IDE interface +#define PPIDE_A0_LINE 0x10 // Direct from 8255 to IDE interface +#define PPIDE_A1_LINE 0x04 // Direct from 8255 to IDE interface +#define PPIDE_A2_LINE 0x40 // Direct from 8255 to IDE interface #define PPIDE_CS0_LINE 0x08 // Inverter between 8255 and IDE interface -#define PPIDE_CS1_LINE 0x10 // Inverter between 8255 and IDE interface -#define PPIDE_WR_LINE 0x20 // Inverter between 8255 and IDE interface -#define PPIDE_WR_BIT 5 // (1 << PPIDE_WR_BIT) = PPIDE_WR_LINE -#define PPIDE_RD_LINE 0x40 // Inverter between 8255 and IDE interface -#define PPIDE_RD_BIT 6 // (1 << PPIDE_RD_BIT) = PPIDE_RD_LINE +#define PPIDE_CS1_LINE 0x20 // Inverter between 8255 and IDE interface +#define PPIDE_WR_LINE 0x01 // Inverter between 8255 and IDE interface +#define PPIDE_WR_BIT 0 // (1 << PPIDE_WR_BIT) = PPIDE_WR_LINE +#define PPIDE_RD_LINE 0x02 // Inverter between 8255 and IDE interface +#define PPIDE_RD_BIT 1 // (1 << PPIDE_RD_BIT) = PPIDE_RD_LINE #define PPIDE_RST_LINE 0x80 // Inverter between 8255 and IDE interface /* 8255 configuration */ diff --git a/Kernel/platform-yaz180/ppide.c b/Kernel/platform-yaz180/ppide.c index f6d0ee10..b2e29227 100644 --- a/Kernel/platform-yaz180/ppide.c +++ b/Kernel/platform-yaz180/ppide.c @@ -12,10 +12,10 @@ #ifdef CONFIG_PPIDE -__sfr __at (PPIDE_BASE + 0x00) ppi_port_a; /* IDE bus LSB */ -__sfr __at (PPIDE_BASE + 0x01) ppi_port_b; /* IDE bus MSB */ -__sfr __at (PPIDE_BASE + 0x02) ppi_port_c; /* IDE bus control signals */ -__sfr __at (PPIDE_BASE + 0x03) ppi_control; /* 8255 command register */ +__sfr __banked __at (PPIDE_BASE + 0x00) ppi_port_a; /* IDE bus LSB */ +__sfr __banked __at (PPIDE_BASE + 0x01) ppi_port_b; /* IDE bus MSB */ +__sfr __banked __at (PPIDE_BASE + 0x02) ppi_port_c; /* IDE bus control signals */ +__sfr __banked __at (PPIDE_BASE + 0x03) ppi_control; /* 8255 command register */ void ppide_init(void) { @@ -57,26 +57,30 @@ void devide_read_data(void) __naked { __asm ld a, #ide_reg_data - ld c, #PPIDE_BASE+2 ; select control lines + ld bc, #PPIDE_BASE+2 ; select control lines out (c), a ; select IDE data register ld hl, (_blk_op+BLKPARAM_ADDR_OFFSET) ; blkparam.addr ld d, #ide_reg_data ; register address ld e, #ide_reg_data | PPIDE_RD_LINE ; register address with /RD asserted - ld b, #0 ; setup count ld a, (_blk_op+BLKPARAM_IS_USER_OFFSET) ; blkparam.is_user or a ; test is_user push af ; save flags - ld a, #PPIDE_BASE+0 ; I will be needing this later call nz, map_process_always ; map user memory first if required + xor a goread: ; now we do the transfer + push af + ld bc,#PPIDE_BASE ; 16bit port numbers (ick) out (c), e ; assert /RD ld c, a ; PPIDE_BASE ini ; read byte from LSB + inc b inc c ; up to MSB - ini ; read byte from MSB + ini + inc b ; read byte from MSB inc c ; control lines out (c), d ; de-assert /RD - inc b ; (delay) counteract second ini instruction + pop af + dec a jr nz, goread ; (delay) next word ; read completed pop af ; recover is_user test result @@ -88,8 +92,8 @@ goread: ; now we do the transfer void devide_write_data(void) __naked { __asm - ld c, #PPIDE_BASE+2 ; select control lines ld a, #ide_reg_data + ld bc, #PPIDE_BASE+2 ; select control lines out (c), a ; select data register ld a, #PPIDE_PPI_BUS_WRITE inc c ; up to 8255A command register @@ -102,17 +106,22 @@ void devide_write_data(void) __naked ld a, (_blk_op+BLKPARAM_IS_USER_OFFSET) ; blkparam.is_user or a ; test is_user push af ; save flags - ld a, #PPIDE_BASE+0 ; I will be needing this later call nz, map_process_always ; map user memory first if required + xor a gowrite: ; now we do the transfer + push af + ld bc, #PPIDE_BASE+0 ; 16bit port numbers (ick) out (c), d ; de-assert /WR ld c, a ; PPIDE_BASE outi ; write byte to LSB inc c ; up to MSB + inc b outi ; write byte to MSB inc c ; up to control lines + inc b out (c), e ; assert /WR - inc b ; (delay) offset to counteract second outi instruction + pop af + dec a jr nz, gowrite ; (delay) next word ; write completed out (c), d ; de-assert /WR -- 2.34.1