From 57dfc84ee76d4b174987b83f66f8ea1b21007c46 Mon Sep 17 00:00:00 2001 From: ceriel Date: Fri, 12 Jan 1990 16:55:50 +0000 Subject: [PATCH] ACK VAX assembler, first version --- mach/vax4/as/.distr | 7 + mach/vax4/as/mach0.c | 23 +++ mach/vax4/as/mach1.c | 51 ++++++ mach/vax4/as/mach2.c | 38 ++++ mach/vax4/as/mach3.c | 427 +++++++++++++++++++++++++++++++++++++++++++ mach/vax4/as/mach4.c | 380 ++++++++++++++++++++++++++++++++++++++ mach/vax4/as/mach5.c | 286 +++++++++++++++++++++++++++++ 7 files changed, 1212 insertions(+) create mode 100644 mach/vax4/as/.distr create mode 100644 mach/vax4/as/mach0.c create mode 100644 mach/vax4/as/mach1.c create mode 100644 mach/vax4/as/mach2.c create mode 100644 mach/vax4/as/mach3.c create mode 100644 mach/vax4/as/mach4.c create mode 100644 mach/vax4/as/mach5.c diff --git a/mach/vax4/as/.distr b/mach/vax4/as/.distr new file mode 100644 index 000000000..3a5e6b717 --- /dev/null +++ b/mach/vax4/as/.distr @@ -0,0 +1,7 @@ +Makefile +mach0.c +mach1.c +mach2.c +mach3.c +mach4.c +mach5.c diff --git a/mach/vax4/as/mach0.c b/mach/vax4/as/mach0.c new file mode 100644 index 000000000..89545f8b3 --- /dev/null +++ b/mach/vax4/as/mach0.c @@ -0,0 +1,23 @@ +/* + * (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands. + * See the copyright notice in the ACK home directory, in the file "Copyright". + */ +#define RCSID0 "$Header$" + +/* + * VAX-11 machine dependent options + */ + +#define THREE_PASS +#define LISTING +#define RELOCATION + +#undef valu_t +#define valu_t long +#undef addr_t +#define addr_t long + +#undef ALIGNWORD +#define ALIGNWORD 4 +#undef ALIGNSECT +#define ALIGNSECT 4 diff --git a/mach/vax4/as/mach1.c b/mach/vax4/as/mach1.c new file mode 100644 index 000000000..2cc716425 --- /dev/null +++ b/mach/vax4/as/mach1.c @@ -0,0 +1,51 @@ +/* + * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands. + * See the copyright notice in the ACK home directory, in the file "Copyright". + */ +#define RCSID1 "$Header$" + +/* + * VAX-11 Machine dependent C declarations + */ + +/* Addressing modes */ + +#define REG_MODE 5 +#define REGDEF_MODE 6 +#define AI_MODE 8 +#define AI_DEF_MODE 9 +#define AD_MODE 7 +#define DISPLB_MODE 10 +#define DISPLW_MODE 12 +#define DISPLL_MODE 14 +#define DISPLB_DEF_MODE 11 +#define DISPLW_DEF_MODE 13 +#define DISPLL_DEF_MODE 15 +#define INDEX_MODE 4 + +#define DISPL 16 /* not an addressing mode; used for branch + displacement addressing + */ +#define IMM 17 /* immediate mode (only for internal use) */ +#define ABS 18 /* absolute mode (only for internal use) */ +#define ABS_DEF 19 /* absolute deferred mode (only for internal use) */ + +#define PC 15 /* special case */ + +#define fit8(z) (lowb(z) == (z)) +#define fit16(z) (loww(z) == (z)) +#define literal(z) (((z) & ~0x3f) == 0) + +struct operand { + expr_t exp; + int mode; /* addressing mode */ + int reg; /* register used in addressing mode */ + int relo; /* index in relocation table for exp */ + int size; /* size as imposed by instruction */ + int index_reg; /* for indexed mode contains index reg, + -1 if not index mode + */ +}; + +extern struct operand opnd[6]; +extern int op_ind; diff --git a/mach/vax4/as/mach2.c b/mach/vax4/as/mach2.c new file mode 100644 index 000000000..58d53e103 --- /dev/null +++ b/mach/vax4/as/mach2.c @@ -0,0 +1,38 @@ +/* + * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands. + * See the copyright notice in the ACK home directory, in the file "Copyright". + */ +#define RCSID2 "$Header$" + +/* +* VAX-11 machine dependent yacc declarations +*/ + +%token REG +%token CASE_b_b_b, CASE_l_l_l, CASE_w_w_w +%token OP0 +%token OP1_A, OP1_Bb, OP1_Bl, OP1_Bw, OP1_Bx, OP1_b, OP1_l, OP1_u, + OP1_w, OP1_Be +%token OP2_A_A, OP2_A_l, OP2_b_b, OP2_b_l, OP2_b_u, OP2_b_w, OP2_l_A, + OP2_l_Bb, OP2_l_b, OP2_l_l, OP2_l_u, OP2_l_w, OP2_u_b, OP2_u_l, + OP2_u_u, OP2_u_w, OP2_w_b, OP2_w_l, OP2_w_u, OP2_w_w, OP2_l_Be +%token OP3_b_b_b, OP3_b_l_l, OP3_b_u_u, OP3_b_w_A, OP3_l_V_Bb, + OP3_l_l_Bb, OP3_l_l_l, OP3_l_w_A, OP3_u_u_u, OP3_u_w_A, + OP3_w_A_A, OP3_w_A_l, OP3_w_w_w, OP3_l_V_Be +%token OP4_A_l_w_A, OP4_b_b_b_Bw, OP4_l_b_V_l, OP4_l_l_b_V, + OP4_l_l_l_Bw, OP4_l_l_l_u, OP4_l_u_l_l, OP4_u_u_u_Bw, + OP4_w_A_A_A, OP4_w_A_A_b, OP4_w_A_w_A, OP4_w_w_w_Bw +%token OP5_u_b_u_l_u, OP5_u_w_u_l_u, OP5_w_A_A_w_A, OP5_w_A_b_w_A +%token OP6_b_w_A_b_w_A, OP6_l_l_l_l_l_l, OP6_w_A_b_A_w_A, + OP6_w_A_w_A_w_A +%token +%type OP1_O, OP1_B +%type OP2_O_O, OP2_A_O, OP2_O_B, OP2_O_A +%type OP3_O_O_O, OP3_O_O_B, OP3_O_O_A, OP3_O_A_A, OP3_O_A_O +%type OP4_O_O_O_O, OP4_O_O_O_B, OP4_O_A_O_A, OP4_O_A_A_O, + OP4_O_A_A_A, OP4_A_O_O_A +%type OP5_O_A_A_O_A, OP5_O_A_O_O_A, OP5_O_O_O_O_O +%type OP6_O_O_O_O_O_O, OP6_O_A_O_A_O_A, OP6_O_O_A_O_O_A +%type CASE_O_O_O + +%type oper diff --git a/mach/vax4/as/mach3.c b/mach/vax4/as/mach3.c new file mode 100644 index 000000000..a5942f7c0 --- /dev/null +++ b/mach/vax4/as/mach3.c @@ -0,0 +1,427 @@ +/* $Header$ */ +/* + * (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands. + * See the copyright notice in the ACK home directory, in the file "Copyright". + */ +/* + * VAX-11 keywords + */ + +0, REG, 0, "r0", +0, REG, 1, "r1", +0, REG, 2, "r2", +0, REG, 3, "r3", +0, REG, 4, "r4", +0, REG, 5, "r5", +0, REG, 6, "r6", +0, REG, 7, "r7", +0, REG, 8, "r8", +0, REG, 9, "r9", +0, REG, 10, "r10", +0, REG, 11, "r11", +0, REG, 12, "r12", +0, REG, 12, "ap", +0, REG, 13, "r13", +0, REG, 13, "fp", +0, REG, 14, "r14", +0, REG, 14, "sp", +0, REG, 15, "r15", +0, REG, 15, "pc", + +/* For immediate mode, we need the size as specified by the instruction. + Ordinary operands are therefore encoded as _w, _b, and _l to indicate + size. + For now, immediate floating point and immediate values of size > 4 are not + implemented. _u is used for this. +*/ + +/* integer arithmetic and logical instructions */ + +0, OP2_w_w, 0x58, "adawi", +0, OP2_b_b, 0x80, "addb2", +0, OP3_b_b_b, 0x81, "addb3", +0, OP2_w_w, 0xa0, "addw2", +0, OP3_w_w_w, 0xa1, "addw3", +0, OP2_l_l, 0xc0, "addl2", +0, OP3_l_l_l, 0xc1, "addl3", +0, OP2_l_l, 0xd8, "adwc", +0, OP3_b_l_l, 0x78, "ashl", +0, OP3_b_u_u, 0x79, "ashq", +0, OP2_b_b, 0x8a, "bicb2", +0, OP3_b_b_b, 0x8b, "bicb3", +0, OP2_w_w, 0xaa, "bicw2", +0, OP3_w_w_w, 0xab, "bicw3", +0, OP2_l_l, 0xca, "bicl2", +0, OP3_l_l_l, 0xcb, "bicl3", +0, OP2_b_b, 0x88, "bisb2", +0, OP3_b_b_b, 0x89, "bisb3", +0, OP2_w_w, 0xa8, "bisw2", +0, OP3_w_w_w, 0xa9, "bisw3", +0, OP2_l_l, 0xc8, "bisl2", +0, OP3_l_l_l, 0xc9, "bisl3", +0, OP2_b_b, 0x93, "bitb", +0, OP2_w_w, 0xb3, "bitw", +0, OP2_l_l, 0xd3, "bitl", +0, OP1_b, 0x94, "clrb", +0, OP1_w, 0xb4, "clrw", +0, OP1_l, 0xd4, "clrl", +0, OP1_u, 0x7c, "clrq", +0, OP1_u, 0x7cfd, "clro", +0, OP2_b_b, 0x91, "cmpb", +0, OP2_w_w, 0xb1, "cmpw", +0, OP2_l_l, 0xd1, "cmpl", +0, OP2_b_w, 0x99, "cvtbw", +0, OP2_b_l, 0x98, "cvtbl", +0, OP2_w_b, 0x33, "cvtwb", +0, OP2_w_l, 0x32, "cvtwl", +0, OP2_l_b, 0xf6, "cvtlb", +0, OP2_l_w, 0xf7, "cvtlw", +0, OP1_b, 0x97, "decb", +0, OP1_w, 0xb7, "decw", +0, OP1_l, 0xd7, "decl", +0, OP2_b_b, 0x86, "divb2", +0, OP3_b_b_b, 0x87, "divb3", +0, OP2_w_w, 0xa6, "divw2", +0, OP3_w_w_w, 0xa7, "divw3", +0, OP2_l_l, 0xc6, "divl2", +0, OP3_l_l_l, 0xc7, "divl3", +0, OP4_l_u_l_l, 0x7b, "ediv", +0, OP4_l_l_l_u, 0x7a, "emul", +0, OP1_b, 0x96, "incb", +0, OP1_w, 0xb6, "incw", +0, OP1_l, 0xd6, "incl", +0, OP2_b_b, 0x92, "mcomb", +0, OP2_w_w, 0xb2, "mcomw", +0, OP2_l_l, 0xd2, "mcoml", +0, OP2_b_b, 0x8e, "mnegb", +0, OP2_w_w, 0xae, "mnegw", +0, OP2_l_l, 0xce, "mnegl", +0, OP2_b_b, 0x90, "movb", +0, OP2_w_w, 0xb0, "movw", +0, OP2_l_l, 0xd0, "movl", +0, OP2_u_u, 0x7d, "movq", +0, OP2_u_u, 0x7dfd, "movo", +0, OP2_b_w, 0x9b, "movzbw", +0, OP2_b_l, 0x9a, "movzbl", +0, OP2_w_l, 0x3c, "movzwl", +0, OP2_b_b, 0x84, "mulb2", +0, OP3_b_b_b, 0x85, "mulb3", +0, OP2_w_w, 0xa4, "mulw2", +0, OP3_w_w_w, 0xa5, "mulw3", +0, OP2_l_l, 0xc4, "mull2", +0, OP3_l_l_l, 0xc5, "mull3", +0, OP1_l, 0xdd, "pushl", +0, OP3_b_l_l, 0x9c, "rotl", +0, OP2_l_l, 0xd9, "sbwc", +0, OP2_b_b, 0x82, "subb2", +0, OP3_b_b_b, 0x83, "subb3", +0, OP2_w_w, 0xa2, "subw2", +0, OP3_w_w_w, 0xa3, "subw3", +0, OP2_l_l, 0xc2, "subl2", +0, OP3_l_l_l, 0xc3, "subl3", +0, OP1_b, 0x95, "tstb", +0, OP1_w, 0xb5, "tstw", +0, OP1_l, 0xd5, "tstl", +0, OP2_b_b, 0x8c, "xorb2", +0, OP3_b_b_b, 0x8d, "xorb3", +0, OP2_w_w, 0xac, "xorw2", +0, OP3_w_w_w, 0xad, "xorw3", +0, OP2_l_l, 0xcc, "xorl2", +0, OP3_l_l_l, 0xcd, "xorl3", + +/* Address instructions */ + +0, OP2_A_l, 0x9e, "movab", +0, OP2_A_l, 0x3e, "movaw", +0, OP2_A_l, 0xde, "moval", +0, OP2_A_l, 0xde, "movaf", +0, OP2_A_l, 0x7e, "movaq", +0, OP2_A_l, 0x7e, "movad", +0, OP2_A_l, 0x7e, "movag", +0, OP2_A_l, 0x7efd, "movah", +0, OP2_A_l, 0x7efd, "movao", +0, OP1_A, 0x9f, "pushab", +0, OP1_A, 0x3f, "pushaw", +0, OP1_A, 0xdf, "pushal", +0, OP1_A, 0xdf, "pushaf", +0, OP1_A, 0x7f, "pushaq", +0, OP1_A, 0x7f, "pushad", +0, OP1_A, 0x7f, "pushag", +0, OP1_A, 0x7ffd, "pushah", +0, OP1_A, 0x7ffd, "pushao", + +/* Variable length bit-field instructions */ + +0, OP4_l_b_V_l, 0xec, "cmpv", +0, OP4_l_b_V_l, 0xed, "cmpzv", +0, OP4_l_b_V_l, 0xee, "extv", +0, OP4_l_b_V_l, 0xef, "extzv", +0, OP4_l_b_V_l, 0xeb, "ffc", +0, OP4_l_b_V_l, 0xea, "ffs", +0, OP4_l_l_b_V, 0xf0, "insv", + +/* Control instructions */ + +0, OP4_b_b_b_Bw, 0x9d, "acbb", +0, OP4_w_w_w_Bw, 0x3d, "acbw", +0, OP4_l_l_l_Bw, 0xf1, "acbl", +0, OP4_u_u_u_Bw, 0x4f, "acbf", +0, OP4_u_u_u_Bw, 0x6f, "acbd", +0, OP4_u_u_u_Bw, 0x4ffd, "acbg", +0, OP4_u_u_u_Bw, 0x6ffd, "acbh", +0, OP3_l_l_Bb, 0xf3, "aobleq", +0, OP3_l_l_Bb, 0xf2, "aoblss", +0, OP1_Bb, 0x14, "bgtr", +0, OP1_Bb, 0x15, "bleq", +0, OP1_Bb, 0x12, "bneq", +0, OP1_Bb, 0x12, "bnequ", +0, OP1_Bb, 0x13, "beql", +0, OP1_Bb, 0x13, "beqlu", +0, OP1_Bb, 0x18, "bgeq", +0, OP1_Bb, 0x19, "blss", +0, OP1_Bb, 0x1a, "bgtru", +0, OP1_Bb, 0x1b, "blequ", +0, OP1_Bb, 0x1c, "bvc", +0, OP1_Bb, 0x1d, "bvs", +0, OP1_Bb, 0x1e, "bgequ", +0, OP1_Bb, 0x1e, "bcc", +0, OP1_Bb, 0x1f, "blssu", +0, OP1_Bb, 0x1f, "bcs", +0, OP3_l_V_Bb, 0xe0, "bbs", +0, OP3_l_V_Bb, 0xe1, "bbc", +0, OP3_l_V_Bb, 0xe2, "bbss", +0, OP3_l_V_Bb, 0xe3, "bbcs", +0, OP3_l_V_Bb, 0xe4, "bbsc", +0, OP3_l_V_Bb, 0xe5, "bbcc", +0, OP3_l_V_Bb, 0xe6, "bbssi", +0, OP3_l_V_Bb, 0xe7, "bbcci", +0, OP2_l_Bb, 0xe8, "blbs", +0, OP2_l_Bb, 0xe9, "blbc", +0, OP1_Be, 0x14, "jgtr", +0, OP1_Be, 0x15, "jleq", +0, OP1_Be, 0x12, "jneq", +0, OP1_Be, 0x12, "jnequ", +0, OP1_Be, 0x13, "jeql", +0, OP1_Be, 0x13, "jeqlu", +0, OP1_Be, 0x18, "jgeq", +0, OP1_Be, 0x19, "jlss", +0, OP1_Be, 0x1a, "jgtru", +0, OP1_Be, 0x1b, "jlequ", +0, OP1_Be, 0x1c, "jvc", +0, OP1_Be, 0x1d, "jvs", +0, OP1_Be, 0x1e, "jgequ", +0, OP1_Be, 0x1e, "jcc", +0, OP1_Be, 0x1f, "jlssu", +0, OP1_Be, 0x1f, "jcs", +0, OP2_l_Be, 0xe8, "jlbs", +0, OP2_l_Be, 0xe9, "jlbc", +0, OP3_l_V_Be, 0xe0, "jbs", +0, OP3_l_V_Be, 0xe1, "jbc", +0, OP3_l_V_Be, 0xe2, "jbss", +0, OP3_l_V_Be, 0xe3, "jbcs", +0, OP3_l_V_Be, 0xe4, "jbsc", +0, OP3_l_V_Be, 0xe5, "jbcc", +0, OP3_l_V_Be, 0xe6, "jbssi", +0, OP3_l_V_Be, 0xe7, "jbcci", +0, OP1_Bx, 0x11, "br", +0, OP1_Bb, 0x11, "brb", +0, OP1_Bw, 0x31, "brw", +0, OP1_Be, 0x11, "jbr", +0, OP1_Bx, 0x10, "bsb", +0, CASE_b_b_b, 0x8f, "caseb", +0, CASE_w_w_w, 0xaf, "casew", +0, CASE_l_l_l, 0xcf, "casel", +0, OP1_A, 0x17, "jmp", +0, OP1_A, 0x16, "jsb", +0, OP0, 0x05, "rsb", +0, OP2_l_Bb, 0xf4, "sobgeq", +0, OP2_l_Bb, 0xf5, "sobgtr", + +/* Procedure call instructions */ + +0, OP2_A_A, 0xfa, "callg", +0, OP2_l_A, 0xfb, "calls", +0, OP0, 0x04, "ret", + +/* Miscellaneous instructions */ + +0, OP1_w, 0xb9, "bicpsw", +0, OP1_w, 0xb8, "bispsw", +0, OP0, 0x03, "bpt", +0, OP0, 0x00, "halt", +0, OP6_l_l_l_l_l_l,0x0a, "index", +0, OP1_l, 0xdc, "movpsl", +0, OP0, 0x01, "nop", +0, OP1_w, 0xba, "popr", +0, OP1_w, 0xbb, "pushr", +0, OP0, 0xfc, "xfc", + +/* Queue instructions */ + +0, OP2_A_A, 0x5c, "insqhi", +0, OP2_A_A, 0x5d, "insqti", +0, OP2_A_A, 0x0e, "insque", +0, OP2_A_l, 0x5e, "remqhi", +0, OP2_A_l, 0x5f, "remqti", +0, OP2_A_l, 0x0f, "remque", + +/* Floating point instructions */ + +0, OP2_u_u, 0x40, "addf2", +0, OP3_u_u_u, 0x41, "addf3", +0, OP2_u_u, 0x60, "addd2", +0, OP3_u_u_u, 0x61, "addd3", +0, OP2_u_u, 0x40fd, "addg2", +0, OP3_u_u_u, 0x41fd, "addg3", +0, OP2_u_u, 0x60fd, "addh2", +0, OP3_u_u_u, 0x61fd, "addh3", +0, OP1_u, 0xd4, "clrf", +0, OP1_u, 0x7c, "clrd", +0, OP1_u, 0x7c, "clrg", +0, OP1_u, 0x7cfd, "clrh", +0, OP2_u_u, 0x51, "cmpf", +0, OP2_u_u, 0x71, "cmpd", +0, OP2_u_u, 0x51fd, "cmpg", +0, OP2_u_u, 0x71fd, "cmph", +0, OP2_b_u, 0x4c, "cvtbf", +0, OP2_b_u, 0x6c, "cvtbd", +0, OP2_b_u, 0x4cfd, "cvtbg", +0, OP2_b_u, 0x6cfd, "cvtbh", +0, OP2_w_u, 0x4d, "cvtwf", +0, OP2_w_u, 0x6d, "cvtwd", +0, OP2_w_u, 0x4dfd, "cvtwg", +0, OP2_w_u, 0x6dfd, "cvtwh", +0, OP2_l_u, 0x4e, "cvtlf", +0, OP2_l_u, 0x6e, "cvtld", +0, OP2_l_u, 0x4efd, "cvtlg", +0, OP2_l_u, 0x6efd, "cvtlh", +0, OP2_u_b, 0x48, "cvtfb", +0, OP2_u_b, 0x68, "cvtdb", +0, OP2_u_b, 0x48fd, "cvtgb", +0, OP2_u_b, 0x68fd, "cvthb", +0, OP2_u_w, 0x49, "cvtfw", +0, OP2_u_w, 0x69, "cvtdw", +0, OP2_u_w, 0x49fd, "cvtgw", +0, OP2_u_w, 0x69fd, "cvthw", +0, OP2_u_l, 0x4a, "cvtfl", +0, OP2_u_l, 0x6a, "cvtdl", +0, OP2_u_l, 0x4afd, "cvtgl", +0, OP2_u_l, 0x6afd, "cvthl", +0, OP2_u_l, 0x4b, "cvtrfl", +0, OP2_u_l, 0x6b, "cvtrdl", +0, OP2_u_l, 0x4bfd, "cvtrgl", +0, OP2_u_l, 0x6bfd, "cvtrhl", +0, OP2_u_u, 0x56, "cvtfd", +0, OP2_u_u, 0x99fd, "cvtfg", +0, OP2_u_u, 0x98fd, "cvtfh", +0, OP2_u_u, 0x76, "cvtdf", +0, OP2_u_u, 0x32fd, "cvtdh", +0, OP2_u_u, 0x33fd, "cvtgf", +0, OP2_u_u, 0x56fd, "cvtgh", +0, OP2_u_u, 0xf6fd, "cvthf", +0, OP2_u_u, 0xf7fd, "cvthd", +0, OP2_u_u, 0x76fd, "cvthg", +0, OP2_u_u, 0x46, "divf2", +0, OP3_u_u_u, 0x47, "divf3", +0, OP2_u_u, 0x66, "divd2", +0, OP3_u_u_u, 0x67, "divd3", +0, OP2_u_u, 0x46fd, "divg2", +0, OP3_u_u_u, 0x47fd, "divg3", +0, OP2_u_u, 0x66fd, "divh2", +0, OP3_u_u_u, 0x67fd, "divh3", +0, OP5_u_b_u_l_u, 0x54, "emodf", +0, OP5_u_b_u_l_u, 0x74, "emodd", +0, OP5_u_w_u_l_u, 0x54fd, "emodg", +0, OP5_u_w_u_l_u, 0x74fd, "emodh", +0, OP2_u_u, 0x52, "mnegf", +0, OP2_u_u, 0x72, "mnegd", +0, OP2_u_u, 0x52fd, "mnegg", +0, OP2_u_u, 0x72fd, "mnegh", +0, OP2_u_u, 0x50, "movf", +0, OP2_u_u, 0x70, "movd", +0, OP2_u_u, 0x50fd, "movg", +0, OP2_u_u, 0x70fd, "movh", +0, OP2_u_u, 0x44, "mulf2", +0, OP3_u_u_u, 0x45, "mulf3", +0, OP2_u_u, 0x64, "muld2", +0, OP3_u_u_u, 0x65, "muld3", +0, OP2_u_u, 0x44fd, "mulg2", +0, OP3_u_u_u, 0x45fd, "mulg3", +0, OP2_u_u, 0x64fd, "mulh2", +0, OP3_u_u_u, 0x65fd, "mulh3", +0, OP3_u_w_A, 0x55, "polyf", +0, OP3_u_w_A, 0x75, "polyd", +0, OP3_u_w_A, 0x55fd, "polyg", +0, OP3_u_w_A, 0x75fd, "polyh", +0, OP2_u_u, 0x42, "subf2", +0, OP3_u_u_u, 0x43, "subf3", +0, OP2_u_u, 0x62, "subd2", +0, OP3_u_u_u, 0x63, "subd3", +0, OP2_u_u, 0x42fd, "subg2", +0, OP3_u_u_u, 0x43fd, "subg3", +0, OP2_u_u, 0x62fd, "subh2", +0, OP3_u_u_u, 0x63fd, "subh3", +0, OP1_u, 0x53, "tstf", +0, OP1_u, 0x73, "tstd", +0, OP1_u, 0x53fd, "tstg", +0, OP1_u, 0x73fd, "tsth", + +/* Character string instructions */ + +0, OP3_w_A_A, 0x29, "cmpc3", +0, OP5_w_A_b_w_A, 0x2d, "cmpc5", +0, OP3_b_w_A, 0x3a, "locc", +0, OP4_w_A_w_A, 0x39, "matchc", +0, OP3_w_A_A, 0x28, "movc3", +0, OP5_w_A_b_w_A, 0x2c, "movc5", +0, OP6_w_A_b_A_w_A,0x2e, "movtc", +0, OP6_w_A_b_A_w_A,0x2f, "movtuc", +0, OP4_w_A_A_b, 0x2a, "scanc", +0, OP3_b_w_A, 0x3b, "skpc", +0, OP4_w_A_A_b, 0x2b, "spanc", + +/* Cyclic redundancy check instructions */ + +0, OP4_A_l_w_A, 0x0b, "crc", + +/* Decimal string instructions */ + +0, OP4_w_A_w_A, 0x20, "addp4", +0, OP6_w_A_w_A_w_A,0x21, "addp6", +0, OP6_b_w_A_b_w_A,0xf8, "ashp", +0, OP3_w_A_A, 0x35, "cmpp3", +0, OP4_w_A_w_A, 0x37, "cmpp4", +0, OP3_l_w_A, 0xf9, "cvtlp", +0, OP3_w_A_l, 0x36, "cvtpl", +0, OP4_w_A_w_A, 0x08, "cvtps", +0, OP5_w_A_A_w_A, 0x24, "cvtpt", +0, OP4_w_A_w_A, 0x09, "cvtsp", +0, OP5_w_A_A_w_A, 0x26, "cvttp", +0, OP6_w_A_w_A_w_A,0x27, "divp", +0, OP3_w_A_A, 0x34, "movp", +0, OP6_w_A_w_A_w_A,0x25, "mulp", +0, OP4_w_A_w_A, 0x22, "subp4", +0, OP6_w_A_w_A_w_A,0x23, "subp6", + +/* Edit instruction */ + +0, OP4_w_A_A_A, 0x38, "editpc", + +/* Other VAX-11 instructions */ + +0, OP1_Bw, 0xfeff, "bugw", /* ??? */ +0, OP1_Bl, 0xfdff, "bugl", /* ??? */ + +0, OP3_b_w_A, 0x0c, "prober", +0, OP3_b_w_A, 0x0d, "probew", + +0, OP0, 0x02, "rei", +0, OP1_w, 0xbc, "chmk", +0, OP1_w, 0xbd, "chme", +0, OP1_w, 0xbe, "chms", +0, OP1_w, 0xbf, "chmu", + +0, OP0, 0x06, "ldpctx", +0, OP0, 0x07, "svpctx", +0, OP2_l_l, 0xda, "mtpr", +0, OP2_l_l, 0xdb, "mfpr", diff --git a/mach/vax4/as/mach4.c b/mach/vax4/as/mach4.c new file mode 100644 index 000000000..c81fb47c5 --- /dev/null +++ b/mach/vax4/as/mach4.c @@ -0,0 +1,380 @@ +/* + * (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands. + * See the copyright notice in the ACK home directory, in the file "Copyright". + */ +#define RCSID4 "$Header$" + +/* +* VAX-11 machine dependent yacc syntax rules +*/ + +/* _b, _w, and _l are ordinary READ/MODIFY/WRITE operands, the letter indicates + the size, + A means effective ADDRESS (must be memory), + B means branch displacement, + V means effective address or register; + Here, no difference is made between Modify and Write. +*/ + +operation + : + { op_ind = 0; } + oper + { if ((unsigned) $2 < 0x100) { + emit1((int)$2); + } + else { + emit1((int)$2&0xff); + emit1((int)$2>>8); + } + operands(op_ind); + } + | OP1_Bx expr { branch($1, $2); } + | OP1_Be expr { op_ind = 0; ext_branch($1, $2); } + | OP2_l_Be { op_ind = 0; opnd[0].size = 4; } + opnd ',' expr + { ext_branch($1, $5); } + | OP3_l_V_Be { op_ind = 0; opnd[0].size = 4; + opnd[1].size = -1; + } + opnd ',' opnd ',' expr + { ext_branch($1, $7); } + ; + +OP1_O + : OP1_b { opnd[0].size = 1; $$ = $1; } + | OP1_w { opnd[0].size = 2; $$ = $1; } + | OP1_l { opnd[0].size = 4; $$ = $1; } + | OP1_u + ; + +OP1_B + : OP1_Bb { opnd[0].size = 1; $$ = $1; } + | OP1_Bw { opnd[0].size = 2; $$ = $1; } + | OP1_Bl { opnd[0].size = 4; $$ = $1; } + ; + +OP2_O_O + : OP2_b_b { opnd[0].size = 1; opnd[1].size = 1; $$ = $1; } + | OP2_b_l { opnd[0].size = 1; opnd[1].size = 4; $$ = $1; } + | OP2_b_u { opnd[0].size = 1; opnd[1].size = 0; $$ = $1; } + | OP2_b_w { opnd[0].size = 1; opnd[1].size = 2; $$ = $1; } + | OP2_l_b { opnd[0].size = 4; opnd[1].size = 1; $$ = $1; } + | OP2_l_l { opnd[0].size = 4; opnd[1].size = 4; $$ = $1; } + | OP2_l_u { opnd[0].size = 4; opnd[1].size = 0; $$ = $1; } + | OP2_l_w { opnd[0].size = 4; opnd[1].size = 2; $$ = $1; } + | OP2_u_b { opnd[0].size = 0; opnd[1].size = 1; $$ = $1; } + | OP2_u_l { opnd[0].size = 0; opnd[1].size = 4; $$ = $1; } + | OP2_u_u { opnd[0].size = 0; opnd[1].size = 0; $$ = $1; } + | OP2_u_w { opnd[0].size = 0; opnd[1].size = 2; $$ = $1; } + | OP2_w_b { opnd[0].size = 2; opnd[1].size = 1; $$ = $1; } + | OP2_w_l { opnd[0].size = 2; opnd[1].size = 4; $$ = $1; } + | OP2_w_u { opnd[0].size = 2; opnd[1].size = 0; $$ = $1; } + | OP2_w_w { opnd[0].size = 2; opnd[1].size = 2; $$ = $1; } + ; + +OP2_A_O + : OP2_A_l { opnd[1].size = 4; $$ = $1; } + ; + +OP2_O_B + : OP2_l_Bb { opnd[0].size = 4; opnd[1].size = 1; $$ = $1; } + ; + +OP2_O_A + : OP2_l_A { opnd[0].size = 4; $$ = $1; } + ; + +OP3_O_O_O + : OP3_b_b_b { opnd[0].size = 1; opnd[1].size = 1; + opnd[2].size = 1; $$ = $1; + } + | OP3_b_l_l { opnd[0].size = 1; opnd[1].size = 4; + opnd[2].size = 4; $$ = $1; + } + | OP3_b_u_u { opnd[0].size = 1; opnd[1].size = 0; + opnd[2].size = 0; $$ = $1; + } + | OP3_l_l_l { opnd[0].size = 4; opnd[1].size = 4; + opnd[2].size = 4; $$ = $1; + } + | OP3_u_u_u { opnd[0].size = 0; opnd[1].size = 0; + opnd[2].size = 0; $$ = $1; + } + | OP3_w_w_w { opnd[0].size = 2; opnd[1].size = 2; + opnd[2].size = 2; $$ = $1; + } + ; + +OP3_O_O_B + : OP3_l_l_Bb { opnd[0].size = 4; opnd[1].size = 4; + opnd[2].size = 1; $$ = $1; + } + | OP3_l_V_Bb { opnd[0].size = 4; opnd[1].size = -1; + opnd[2].size = 1; $$ = $1; + } + ; + +OP3_O_O_A + : OP3_b_w_A { opnd[0].size = 1; opnd[1].size = 2; $$ = $1; } + | OP3_l_w_A { opnd[0].size = 4; opnd[1].size = 2; $$ = $1; } + | OP3_u_w_A { opnd[0].size = 0; opnd[1].size = 2; $$ = $1; } + ; + +OP3_O_A_A + : OP3_w_A_A { opnd[0].size = 2; $$ = $1; } + ; + +OP3_O_A_O + : OP3_w_A_l { opnd[0].size = 2; opnd[2].size = 4; $$ = $1; } + ; + +OP4_O_O_O_O + : OP4_l_b_V_l { opnd[0].size = 4; opnd[1].size = 1; + opnd[2].size = -1; opnd[3].size = 4; + $$ = $1; + } + | OP4_l_l_b_V { opnd[0].size = 4; opnd[1].size = 4; + opnd[2].size = 1; opnd[3].size = -1; + $$ = $1; + } + | OP4_l_l_l_u { opnd[0].size = 4; opnd[1].size = 4; + opnd[2].size = 4; opnd[3].size = 0; + $$ = $1; + } + | OP4_l_u_l_l { opnd[0].size = 4; opnd[1].size = 0; + opnd[2].size = 4; opnd[3].size = 4; + $$ = $1; + } + ; + +OP4_O_O_O_B + : OP4_b_b_b_Bw { opnd[0].size = 1; opnd[1].size = 1; + opnd[2].size = 1; opnd[3].size = 2; + $$ = $1; + } + | OP4_l_l_l_Bw { opnd[0].size = 4; opnd[1].size = 4; + opnd[2].size = 4; opnd[3].size = 2; + $$ = $1; + } + | OP4_u_u_u_Bw { opnd[0].size = 0; opnd[1].size = 0; + opnd[2].size = 0; opnd[3].size = 2; + $$ = $1; + } + | OP4_w_w_w_Bw { opnd[0].size = 2; opnd[1].size = 2; + opnd[2].size = 2; opnd[3].size = 2; + $$ = $1; + } + ; + +OP4_O_A_O_A + : OP4_w_A_w_A { opnd[0].size = 2; opnd[2].size = 2; $$ = $1; } + ; + +OP4_O_A_A_O + : OP4_w_A_A_b { opnd[0].size = 2; opnd[3].size = 1; $$ = $1; } + ; + +OP4_O_A_A_A + : OP4_w_A_A_A { opnd[0].size = 2; $$ = $1; } + ; + +OP4_A_O_O_A + : OP4_A_l_w_A { opnd[1].size = 4; opnd[2].size = 2; $$ = $1; } + ; + +OP5_O_A_A_O_A + : OP5_w_A_A_w_A { opnd[0].size = 2; opnd[3].size = 2; $$ = $1; } + ; + +OP5_O_A_O_O_A + : OP5_w_A_b_w_A { opnd[0].size = 2; opnd[3].size = 2; + opnd[2].size = 1; $$ = $1; + } + ; + +OP5_O_O_O_O_O + : OP5_u_b_u_l_u { opnd[0].size = 0; opnd[1].size = 1; + opnd[2].size = 0; opnd[3].size = 4; + opnd[4].size = 0; $$ = $1; + } + | OP5_u_w_u_l_u { opnd[0].size = 0; opnd[1].size = 2; + opnd[2].size = 0; opnd[3].size = 4; + opnd[4].size = 0; $$ = $1; + } + ; + +OP6_O_O_O_O_O_O + : OP6_l_l_l_l_l_l { opnd[0].size = 4; opnd[1].size = 4; + opnd[2].size = 4; opnd[3].size = 4; + opnd[4].size = 4; opnd[5].size = 4; + $$ = $1; + } + ; + +OP6_O_A_O_A_O_A + : OP6_w_A_b_A_w_A { opnd[0].size = 2; opnd[2].size = 1; + opnd[4].size = 2; $$ = $1; + } + | OP6_w_A_w_A_w_A { opnd[0].size = 2; opnd[2].size = 2; + opnd[4].size = 2; $$ = $1; + } + ; + +OP6_O_O_A_O_O_A + : OP6_b_w_A_b_w_A { opnd[0].size = 1; opnd[1].size = 2; + opnd[3].size = 1; opnd[4].size = 2; + $$ = $1; + } + ; + +CASE_O_O_O + : CASE_b_b_b { opnd[0].size = 1; opnd[1].size = 1; + opnd[2].size = 1; $$ = $1; + } + | CASE_w_w_w { opnd[0].size = 2; opnd[1].size = 2; + opnd[2].size = 2; $$ = $1; + } + | CASE_l_l_l { opnd[0].size = 4; opnd[1].size = 4; + opnd[2].size = 4; $$ = $1; + } + ; + +oper + : OP0 + | OP1_O opnd { $$ = $1; } + | OP1_A ea { $$ = $1; } + | OP1_B expr { $$ = $1; + opnd[0].exp = $2; + RELOMOVE(opnd[0].relo, relonami); + opnd[0].mode = DISPL; + op_ind = 1; + } + | OP2_O_O opnd ',' opnd + { $$ = $1; } + | OP2_A_O ea ',' opnd + { $$ = $1; } + | OP2_O_B opnd ',' expr + { $$ = $1; + opnd[op_ind].exp = $4; + RELOMOVE(opnd[op_ind].relo, relonami); + opnd[op_ind].mode = DISPL; + op_ind++; + } + | OP2_A_A ea ',' ea + { $$ = $1; } + | OP2_O_A opnd ',' ea + { $$ = $1; } + | OP3_O_O_O opnd ',' opnd ',' opnd + { $$ = $1; } + | OP3_O_O_B opnd ',' opnd ',' expr + { $$ = $1; + opnd[op_ind].exp = $6; + RELOMOVE(opnd[op_ind].relo, relonami); + opnd[op_ind].mode = DISPL; + op_ind++; + } + | OP3_O_O_A opnd ',' opnd ',' ea + { $$ = $1; } + | OP3_O_A_A opnd ',' ea ',' ea + { $$ = $1; } + | OP3_O_A_O opnd ',' ea ',' opnd + { $$ = $1; } + | OP4_O_O_O_O opnd ',' opnd ',' opnd ',' opnd + { $$ = $1; } + | OP4_O_O_O_B opnd ',' opnd ',' opnd ',' expr + { $$ = $1; + opnd[op_ind].exp = $8; + RELOMOVE(opnd[op_ind].relo, relonami); + opnd[op_ind].mode = DISPL; + op_ind++; + } + | OP4_O_A_O_A opnd ',' ea ',' opnd ',' ea + { $$ = $1; } + | OP4_O_A_A_O opnd ',' ea ',' ea ',' opnd + { $$ = $1; } + | OP4_A_O_O_A ea ',' opnd ',' opnd ',' ea + { $$ = $1; } + | OP4_O_A_A_A opnd ',' ea ',' ea ',' ea + { $$ = $1; } + | OP5_O_A_A_O_A opnd ',' ea ',' ea ',' opnd ',' ea + { $$ = $1; } + | OP5_O_A_O_O_A opnd ',' ea ',' opnd ',' opnd ',' ea + { $$ = $1; } + | OP5_O_O_O_O_O opnd ',' opnd ',' opnd ',' opnd ',' opnd + { $$ = $1; } + | OP6_O_O_O_O_O_O opnd ',' opnd ',' opnd ',' opnd ',' opnd ',' opnd + { $$ = $1; } + | OP6_O_A_O_A_O_A opnd ',' ea ',' opnd ',' ea ',' opnd ',' ea + { $$ = $1; } + | OP6_O_O_A_O_O_A opnd ',' opnd ',' ea ',' opnd ',' opnd ',' ea + { $$ = $1; } + | CASE_O_O_O opnd ',' opnd ',' opnd + { $$ = $1; } + ; + +opnd + : ea + | immediate + | REG { opnd[op_ind].mode = REG_MODE; + opnd[op_ind].reg = $1; + opnd[op_ind].index_reg = -1; + op_ind++; + } + ; + +ea + : eax { opnd[op_ind].index_reg = -1; + op_ind++; + } + | eax '[' REG ']' { opnd[op_ind].index_reg = $3; + op_ind++; + } + | immediate '[' REG ']' + { opnd[op_ind-1].index_reg = $3; + } + ; +eax + : expr { opnd[op_ind].exp = $1; + opnd[op_ind].mode = ABS; + RELOMOVE(opnd[op_ind].relo, relonami); + } + | '*' expr { opnd[op_ind].exp = $2; + opnd[op_ind].mode = ABS_DEF; + RELOMOVE(opnd[op_ind].relo, relonami); + } + | '(' REG ')' { opnd[op_ind].mode = REGDEF_MODE; + opnd[op_ind].reg = $2; + } + | '(' REG ')' '+' { opnd[op_ind].mode = AI_MODE; + opnd[op_ind].reg = $2; + } + | '*' '(' REG ')' '+' + { opnd[op_ind].mode = AI_DEF_MODE; + opnd[op_ind].reg = $3; + } + | '-' '(' REG ')' { opnd[op_ind].mode = AD_MODE; + opnd[op_ind].reg = $3; + } + | expr '(' REG ')' + { opnd[op_ind].exp = $1; + opnd[op_ind].mode = DISPLL_MODE; + opnd[op_ind].reg = $3; + RELOMOVE(opnd[op_ind].relo, relonami); + } + | '*' expr '(' REG ')' + { opnd[op_ind].exp = $2; + opnd[op_ind].mode = DISPLL_DEF_MODE; + opnd[op_ind].reg = $4; + RELOMOVE(opnd[op_ind].relo, relonami); + } + ; + +immediate + : '$' expr { opnd[op_ind].mode = IMM; + opnd[op_ind].exp = $2; + opnd[op_ind].index_reg = -1; + RELOMOVE(opnd[op_ind].relo, relonami); + op_ind++; + } + ; diff --git a/mach/vax4/as/mach5.c b/mach/vax4/as/mach5.c new file mode 100644 index 000000000..bc191306f --- /dev/null +++ b/mach/vax4/as/mach5.c @@ -0,0 +1,286 @@ +/* + * (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands. + * See the copyright notice in the ACK home directory, in the file "Copyright". + */ +#define RCSID5 "$Header$" + +/* + * VAX-11 Machine dependent C declarations + */ + +static +oprnd(p) + register struct operand *p; +{ + /* Process one operand */ + + int sm; + + if (p->index_reg >= 0 && p->mode != DISPL) { + /* indexed mode; emit */ + emit1((INDEX_MODE << 4) | p->index_reg); + } + + switch(p->mode) { + case REG_MODE: + emit1((REG_MODE << 4) | p->reg); + break; + case REGDEF_MODE: + emit1((REGDEF_MODE << 4) | p->reg); + break; + case AI_MODE: + emit1((AI_MODE << 4) | p->reg); + break; + case AI_DEF_MODE: + emit1((AI_DEF_MODE << 4) | p->reg); + break; + case AD_MODE: + emit1((AD_MODE << 4) | p->reg); + break; + case DISPLL_MODE: + case DISPLL_DEF_MODE: + if (small(p->exp.typ == S_ABS && fitw(p->exp.val), 2)) { + if (small(fitb(p->exp.val), 1)) { + /* DISPLB_MODE or DISPLB_DEF_MODE */ + emit1(((p->mode-4)<<4) | p->reg); + emit1((int)(p->exp.val)); + } + else { + /* DISPLW_MODE or DISPLW_DEF_MODE */ + emit1(((p->mode-2)<<4) | p->reg); + emit2((int)(p->exp.val)); + } + } + else { + small(0, 1); /* dummy call */ + emit1((p->mode<<4) | p->reg); +#ifdef RELOCATION + RELOMOVE(relonami, p->relo); + newrelo(p->exp.typ, RELO4); +#endif + emit4((long) p->exp.val); + } + break; + case DISPL: + /* a displacement */ + p->exp.val -= (DOTVAL + p->size); + if ((pass == PASS_2) && + (p->exp.val > 0) && + ((p->exp.typ & S_DOT) == 0) + ) { + p->exp.val -= DOTGAIN; + } + if (p->size == 1) sm = fitb(p->exp.val); + else if (p->size == 2) sm = fitw(p->exp.val); + else sm = 1; + if (pass >= PASS_2 && + ((p->exp.typ & ~S_DOT) != DOTTYP || !sm)) { + serror("label too far"); + } + if (p->size == 1) emit1((int)(p->exp.val)); + else if (p->size == 2) emit2((int)(p->exp.val)); + else emit4(p->exp.val); + break; + case IMM: + if (p->size < 0) { + serror("immediate mode not allowed here"); + p->size = 4; + } + else if (p->size == 0) { + serror("this immediate mode is not implemented"); + p->size = 4; + } + if (small(p->exp.typ == S_ABS && literal(p->exp.val), p->size)){ + emit1((int)(p->exp.val)); + } + else { + emit1((AI_MODE << 4) | PC); + RELOMOVE(relonami, p->relo); + switch(p->size) { + case 1: +#ifdef RELOCATION + newrelo(p->exp.typ, RELO1); +#endif + emit1((int)(p->exp.val)); + break; + case 2: +#ifdef RELOCATION + newrelo(p->exp.typ, RELO2); +#endif + emit2((int)(p->exp.val)); + break; + case 4: +#ifdef RELOCATION + newrelo(p->exp.typ, RELO4); +#endif + emit4(p->exp.val); + break; + default: + assert(0); + } + } + break; + case ABS: + case ABS_DEF: + if (p->mode == ABS) p->mode = DISPLL_MODE; + else p->mode = DISPLL_DEF_MODE; + p->reg = PC; + p->exp.val -= (DOTVAL + 2); + if ((pass == PASS_2) + && + (p->exp.val > 0) + && + ((p->exp.typ & S_DOT) == 0) + ) { + p->exp.val -= DOTGAIN; + } + sm = fitw(p->exp.val - 1); + if ((p->exp.typ & ~S_DOT) != DOTTYP) sm = 0; + if (small(sm, 2)) { + if (small(fitb(p->exp.val), 1)) { + /* DISPLB_MODE or DISPLB_DEF_MODE */ + emit1(((p->mode-4)<<4) | p->reg); + emit1((int)(p->exp.val)); + } + else { + /* DISPLW_MODE or DISPLW_DEF_MODE */ + emit1(((p->mode-2)<<4) | p->reg); + emit2((int)(p->exp.val - 1)); + } + } + else { + small(0, 1); /* dummy call */ + emit1((p->mode<<4) | p->reg); +#ifdef RELOCATION + RELOMOVE(relonami, p->relo); + newrelo(p->exp.typ, RELO4|RELPC); +#endif + emit4((long) p->exp.val - 3); + } + break; + default: + assert(0); + } +} + +static int +size_ops() +{ + /* Give an upper bound on the size of the operands + */ + register struct operand *p = &opnd[0]; + register int i; + register int sz = 0; + + for (i = 0; i < op_ind; i++) { + if (p->index_reg >= 0 && p->mode != DISPL) { + sz++; + } + switch(p->mode) { + case REG_MODE: + case REGDEF_MODE: + case AI_MODE: + case AI_DEF_MODE: + case AD_MODE: + sz++; + break; + case DISPLL_MODE: + case DISPLL_DEF_MODE: + case ABS: + case ABS_DEF: + case IMM: + sz += 5; + break; + case DISPL: + sz += p->size; + break; + default: + assert(0); + } + p++; + } + return sz; +} + +branch(opc, exp) + expr_t exp; +{ + exp.val -= (DOTVAL + 2); + if ((pass == PASS_2) && + (exp.val > 0) && + ((exp.typ & S_DOT) == 0) + ) { + exp.val -= DOTGAIN; + } + if (pass >= PASS_2 && + ((exp.typ & ~S_DOT) != DOTTYP || ! fitw(exp.val))) { + serror("label too far"); + } + if (small(fitb(exp.val) && ((exp.typ & ~S_DOT) == DOTTYP), 1)) { + emit1(opc); + emit1((int) exp.val); + } + else { + emit1(opc|0x20); + emit2((int) exp.val); + } +} + +ext_branch(opc, exp) + expr_t exp; +{ + int sm; + int gain = opc == 0x11 ? 1 : 3; + valu_t val, d2 = DOTVAL + 2; + + exp.val -= d2; + if ((pass == PASS_2) && + (exp.val > 0) && + ((exp.typ & S_DOT) == 0) + ) { + exp.val -= DOTGAIN; + } + if (exp.val < 0) val = exp.val - size_ops(); + else val = exp.val; + sm = fitw(val); + if ((exp.typ & ~S_DOT) != DOTTYP) sm = 0; + if (small(sm, 3)) { + if (small(fitb(val), gain)) { + emit1(opc); + operands(op_ind); + emit1((int) (exp.val - (DOTVAL + 1 - d2))); + } + else { + if (opc != 0x11) { + emit1(opc^1); + operands(op_ind); + emit1(3); + } + emit1(0x31); + emit2((int) (exp.val - (DOTVAL + 2 - d2))); + } + } + else { + small(0, gain); /* dummy call */ + if (opc != 0x11) { + emit1(opc ^ 1); + operands(op_ind); + emit1(6); + } + emit1(0x17); /* jmp */ + emit1((DISPLL_MODE << 4) | PC); +#ifdef RELOCATION + newrelo(exp.typ, RELO4|RELPC); +#endif + emit4(exp.val - (DOTVAL + 4 - d2)); + } +} + +operands(cnt) +{ + register int i; + + for (i = 0; i < cnt; i++) { + oprnd(&opnd[i]); + } +} -- 2.34.1