From 55c3adbf80820b8dcef680a9d1bbd3df1f302309 Mon Sep 17 00:00:00 2001 From: David Given Date: Sat, 19 Mar 2016 14:52:55 +0100 Subject: [PATCH] Upgrade the ARM assembler to be a bit more modern and to support relocations. --HG-- branch : default-branch --- h/out.h | 1 + mach/arm/as/mach0.c | 13 +-- mach/arm/as/mach3.c | 240 +++++++++++++++++++++++--------------------- mach/arm/as/mach4.c | 2 +- mach/arm/as/mach5.c | 36 ++++--- man/arm_as.6 | 25 +++++ 6 files changed, 180 insertions(+), 137 deletions(-) create mode 100644 man/arm_as.6 diff --git a/h/out.h b/h/out.h index 16c22be51..3bc9d30c7 100644 --- a/h/out.h +++ b/h/out.h @@ -69,6 +69,7 @@ struct outname { #define RELOPPC 4 /* PowerPC 26-bit address */ #define RELOH2 5 /* write top 2 bytes of 4 byte word */ #define RELOVC4 6 /* VideoCore IV address in 32-bit instruction */ +#define RELOARM 7 /* ARM address in 32-bit instruction */ #define RELPC 0x2000 /* pc relative */ #define RELBR 0x4000 /* High order byte lowest address. */ diff --git a/mach/arm/as/mach0.c b/mach/arm/as/mach0.c index 855541a15..ffce76480 100644 --- a/mach/arm/as/mach0.c +++ b/mach/arm/as/mach0.c @@ -1,21 +1,22 @@ /* $Header; mach0.c, v1.2 06-Mar-89 AJM */ -#define LISTING -#define ASLD +#include + #define THREE_PASS -#define DEBUG 0 +#define LISTING /* enable listing facilities */ +#define RELOCATION /* generate relocation info */ /* #define WORDS_REVERSED #define BYTES_REVERSED */ #undef valu_t -#define valu_t long +#define valu_t int32_t #undef ADDR_T -#define ADDR_T long +#define ADDR_T uint32_t #undef word_t -#define word_t long +#define word_t uint32_t #undef ALIGNWORD #define ALIGNWORD 4 diff --git a/mach/arm/as/mach3.c b/mach/arm/as/mach3.c index a35feb540..efdd8335f 100644 --- a/mach/arm/as/mach3.c +++ b/mach/arm/as/mach3.c @@ -1,121 +1,127 @@ /* $Id: mach3.c, v2.0 23-Feb-89 AJM */ -0, COND, 0x00000000, ".EQ", -0, COND, 0x10000000, ".NE", -0, COND, 0x20000000, ".CS", -0, COND, 0x20000000, ".HS", -0, COND, 0x30000000, ".CC", -0, COND, 0x30000000, ".LO", -0, COND, 0x40000000, ".MI", -0, COND, 0x50000000, ".PL", -0, COND, 0x60000000, ".VS", -0, COND, 0x70000000, ".VC", -0, COND, 0x80000000, ".HI", -0, COND, 0x90000000, ".LS", -0, COND, 0xA0000000, ".GE", -0, COND, 0xB0000000, ".LT", -0, COND, 0xC0000000, ".GT", -0, COND, 0xD0000000, ".LE", -0, COND, 0xE0000000, ".AL", -0, COND, 0xF0000000, ".NV", - -0, LINK, 0x01000000, ".L", - -0, BRANCH, 0x0A000000, "BEQ", -0, BRANCH, 0x1A000000, "BNE", -0, BRANCH, 0x2A000000, "BCS", -0, BRANCH, 0x2A000000, "BHS", -0, BRANCH, 0x3A000000, "BCC", -0, BRANCH, 0x3A000000, "BLO", -0, BRANCH, 0x4A000000, "BMI", -0, BRANCH, 0x5A000000, "BPL", -0, BRANCH, 0x6A000000, "BVS", -0, BRANCH, 0x7A000000, "BVC", -0, BRANCH, 0x8A000000, "BHI", -0, BRANCH, 0x9A000000, "BLS", -0, BRANCH, 0xAA000000, "BGE", -0, BRANCH, 0xBA000000, "BLT", -0, BRANCH, 0xCA000000, "BGT", -0, BRANCH, 0xDA000000, "BLE", -0, BRANCH, 0xEA000000, "BAL", -0, BRANCH, 0xFA000000, "BNV", - -0, DATA1, ADC, "ADC", -0, DATA1, ADD, "ADD", -0, DATA1, AND, "AND", -0, DATA1, BIC, "BIC", -0, DATA1, EOR, "EOR", -0, DATA1, ORR, "ORR", -0, DATA1, RSB, "RSB", -0, DATA1, RSC, "RSC", -0, DATA1, SBC, "SBC", -0, DATA1, SUB, "SUB", -0, DATA2, MOV, "MOV", -0, DATA2, MVN, "MVN", -0, DATA3, CMN, "CMN", -0, DATA3, CMP, "CMP", -0, DATA3, TEQ, "TEQ", -0, DATA3, TST, "TST", - -0, SET, 0x00100000, ".S", - -0, PEE, 0x0010F000, ".P", - -0, REG, 0, "R0", -0, REG, 1, "R1", -0, REG, 2, "R2", -0, REG, 3, "R3", -0, REG, 4, "R4", -0, REG, 5, "R5", -0, REG, 6, "R6", -0, REG, 7, "R7", -0, REG, 8, "R8", -0, REG, 9, "R9", -0, REG, 10, "R10", -0, REG, 11, "R11", -0, REG, 12, "R12", -0, REG, 13, "R13", -0, REG, 14, "R14", -0, REG, 15, "R15", -0, REG, 15, "PC", - -0, SHIFT, 0x00000000, "LSL", -0, SHIFT, 0x00000000, "ASL", -0, SHIFT, 0x00000020, "LSR", -0, SHIFT, 0x00000040, "ASR", -0, SHIFT, 0x00000060, "ROR", - -0, RRX, 0x00000060, "RRX", - -0, SDT, 0x04100000, "LDR", -0, SDT, 0x04000000, "STR", - -0, BYTE, 0x00400000, ".B", - -0, TRANS, 0x00200000, ".T", - -0, BDT, 0x09100000, "LDMDB", -0, BDT, 0x08100000, "LDMDA", -0, BDT, 0x09900000, "LDMIB", -0, BDT, 0x08900000, "LDMIA", -0, BDT, 0x08900000, "LDMFD", -0, BDT, 0x08100000, "LDMFA", -0, BDT, 0x09900000, "LDMED", -0, BDT, 0x09100000, "LDMEA", -0, BDT, 0x09000000, "STMDB", -0, BDT, 0x08000000, "STMDA", -0, BDT, 0x09800000, "STMIB", -0, BDT, 0x08800000, "STMIA", -0, BDT, 0x09000000, "STMFD", -0, BDT, 0x09800000, "STMFA", -0, BDT, 0x08000000, "STMED", -0, BDT, 0x08800000, "STMEA", - -0, SWI, 0x0F000000, "SWI", - -0, ADR, 0x00000000, "ADR", - -0, MUL, 0x00000090, "MUL", -0, MLA, 0x00200090, "MLA", +0, COND, 0x00000000, ".eq", +0, COND, 0x10000000, ".ne", +0, COND, 0x20000000, ".cs", +0, COND, 0x20000000, ".hs", +0, COND, 0x30000000, ".cc", +0, COND, 0x30000000, ".lo", +0, COND, 0x40000000, ".mi", +0, COND, 0x50000000, ".pl", +0, COND, 0x60000000, ".vs", +0, COND, 0x70000000, ".vc", +0, COND, 0x80000000, ".hi", +0, COND, 0x90000000, ".ls", +0, COND, 0xA0000000, ".ge", +0, COND, 0xB0000000, ".lt", +0, COND, 0xC0000000, ".gt", +0, COND, 0xD0000000, ".le", +0, COND, 0xE0000000, ".al", +0, COND, 0xF0000000, ".nv", + +0, LINK, 0x01000000, ".l", +0, BRANCH, 0xEB000000, "bl", + +0, BRANCH, 0x0A000000, "beq", +0, BRANCH, 0x1A000000, "bne", +0, BRANCH, 0x2A000000, "bcs", +0, BRANCH, 0x2A000000, "bhs", +0, BRANCH, 0x3A000000, "bcc", +0, BRANCH, 0x3A000000, "blo", +0, BRANCH, 0x4A000000, "bmi", +0, BRANCH, 0x5A000000, "bpl", +0, BRANCH, 0x6A000000, "bvs", +0, BRANCH, 0x7A000000, "bvc", +0, BRANCH, 0x8A000000, "bhi", +0, BRANCH, 0x9A000000, "bls", +0, BRANCH, 0xAA000000, "bge", +0, BRANCH, 0xBA000000, "blt", +0, BRANCH, 0xCA000000, "bgt", +0, BRANCH, 0xDA000000, "ble", +0, BRANCH, 0xEA000000, "b", +0, BRANCH, 0xFA000000, "bnv", + +0, DATA1, ADC, "adc", +0, DATA1, ADD, "add", +0, DATA1, AND, "and", +0, DATA1, BIC, "bic", +0, DATA1, EOR, "eor", +0, DATA1, ORR, "orr", +0, DATA1, RSB, "rsb", +0, DATA1, RSC, "rsc", +0, DATA1, SBC, "sbc", +0, DATA1, SUB, "sub", +0, DATA2, MOV, "mov", +0, DATA2, MVN, "mvn", +0, DATA3, CMN, "cmn", +0, DATA3, CMP, "cmp", +0, DATA3, TEQ, "teq", +0, DATA3, TST, "tst", + +0, SET, 0x00100000, ".s", + +0, PEE, 0x0010F000, ".p", + +0, REG, 0, "r0", +0, REG, 1, "r1", +0, REG, 2, "r2", +0, REG, 3, "r3", +0, REG, 4, "r4", +0, REG, 5, "r5", +0, REG, 6, "r6", +0, REG, 7, "r7", +0, REG, 8, "r8", +0, REG, 9, "r9", +0, REG, 10, "r10", +0, REG, 11, "r11", +0, REG, 12, "r12", +0, REG, 13, "r13", +0, REG, 14, "r14", +0, REG, 15, "r15", + +0, REG, 11, "fp", +0, REG, 12, "ip", +0, REG, 13, "sp", +0, REG, 14, "lr", +0, REG, 15, "pc", + +0, SHIFT, 0x00000000, "lsl", +0, SHIFT, 0x00000000, "asl", +0, SHIFT, 0x00000020, "lsr", +0, SHIFT, 0x00000040, "asr", +0, SHIFT, 0x00000060, "ror", + +0, RRX, 0x00000060, "rrx", + +0, SDT, 0x04100000, "ldr", +0, SDT, 0x04000000, "str", + +0, BYTE, 0x00400000, ".b", + +0, TRANS, 0x00200000, ".t", + +0, BDT, 0x09100000, "ldmdb", +0, BDT, 0x08100000, "ldmda", +0, BDT, 0x09900000, "ldmib", +0, BDT, 0x08900000, "ldmia", +0, BDT, 0x08900000, "ldmfd", +0, BDT, 0x08100000, "ldmfa", +0, BDT, 0x09900000, "ldmed", +0, BDT, 0x09100000, "ldmea", +0, BDT, 0x09000000, "stmdb", +0, BDT, 0x08000000, "stmda", +0, BDT, 0x09800000, "stmib", +0, BDT, 0x08800000, "stmia", +0, BDT, 0x09000000, "stmfd", +0, BDT, 0x09800000, "stmfa", +0, BDT, 0x08000000, "stmed", +0, BDT, 0x08800000, "stmea", + +0, SWI, 0x0F000000, "swi", + +0, ADR, 0x00000000, "adr", + +0, MUL, 0x00000090, "mul", +0, MLA, 0x00200090, "mla", diff --git a/mach/arm/as/mach4.c b/mach/arm/as/mach4.c index 9142ac682..7051ce9de 100644 --- a/mach/arm/as/mach4.c +++ b/mach/arm/as/mach4.c @@ -1,7 +1,7 @@ /* $Id: mach4.c, v1.9 15-Mar-89 AJM */ operation : BRANCH optlink expr - {branch($1, $2, $3.val);} + {branch($1, $2, &$3);} | DATA1 optcond opts optp REG ',' REG ',' operand {data($1,$2|$3|$4|$5<<12|$7<<16,$9.val,$9.typ);} | DATA2 optcond opts optp REG ',' operand diff --git a/mach/arm/as/mach5.c b/mach/arm/as/mach5.c index 1eedbaf8d..18a4cc272 100644 --- a/mach/arm/as/mach5.c +++ b/mach/arm/as/mach5.c @@ -1,19 +1,29 @@ -/* $Id: mach5.c, v3.3 25-Apr-89 AJM */ +#include -branch(brtyp, link, val) -word_t brtyp; -word_t link; -valu_t val; +#define maskx(v, x) (v & ((1<<(x))-1)) + +void branch(word_t brtyp, word_t link, struct expr_t* expr) { - valu_t offset; + uint32_t pc = DOTVAL; + uint32_t type = expr->typ & S_TYP; + int d; - offset = val - DOTVAL - 8; /* Allow for pipeline */ - if ((offset & 0xFC000000) != 0 && (offset & 0xFC000000) != 0xFC000000){ - serror("offset out of range"); - } - offset = offset>>2 & 0xFFFFFF; - emit4(brtyp|link|offset); - return; + /* Sanity checking. */ + + if (type == S_ABS) + serror("can't use absolute addresses here"); + + /* Calculate the instruction displacement. */ + + d = (int32_t)expr->val - (int32_t)pc; + if ((pass == 2) && (d > 0) && !(expr->typ & S_DOT)) + d -= DOTGAIN; + d = (d - 8) >> 2; + + if (type != DOTTYP) + newrelo(expr->typ, RELOARM|RELPC); + + emit4(brtyp|link | maskx(d, 24)); } data(opc, ins, val, typ) diff --git a/man/arm_as.6 b/man/arm_as.6 new file mode 100644 index 000000000..c6b0efdf6 --- /dev/null +++ b/man/arm_as.6 @@ -0,0 +1,25 @@ +.\" $Header$ +.TH ARM_AS 1 +.ad +.SH NAME +arm_as \- assembler for ARM + +.SH SYNOPSIS +/usr/em/lib/arm_as [options] argument ... + +.SH DESCRIPTION +This assembler is made with the general framework +described in \fIuni_ass\fP(6). + +.SH SYNTAX +This assembler is very old and doesn't use standard opcode mnemonics. Use at +your own risk. + +.SH "SEE ALSO" +uni_ass(6), +ack(1), +.SH EXAMPLE +.nf +.ta 8n 16n 24n 32n 40n 48n +Todo. +.fi -- 2.34.1