From 3f65a2495154111caa3295ba347a37b7294378eb Mon Sep 17 00:00:00 2001 From: Nick Downing Date: Mon, 21 Jul 2025 22:52:40 +1000 Subject: [PATCH] More work on node names and many additional circuits, code cleanup --- 8085/node_names.txt | 236 +++++++++++++++++++++--------------------- scripts/blocks.py | 229 +++++++++++++++++++--------------------- scripts/circuits.py | 201 ++++++++++++++++++++++++----------- scripts/gates.py | 6 +- scripts/join_lines.sh | 8 ++ 5 files changed, 384 insertions(+), 296 deletions(-) create mode 100755 scripts/join_lines.sh diff --git a/8085/node_names.txt b/8085/node_names.txt index f2ed6e8..ba8070b 100644 --- a/8085/node_names.txt +++ b/8085/node_names.txt @@ -156,18 +156,18 @@ 3_0428_4695 bus_d5 3_0431_4675 bus_d6 3_0443_4655 bus_d7 -3_0651_3587 alu0_0 -3_0682_3609 alu0_1 -3_0703_3680 alu0_2 -3_0727_3609 alu0_3 -3_0744_3746 alu0_4 +3_0651_3587 alu_le_int_to_x +3_0682_3609 alu_le_bus_to_q +3_0703_3680 alu_le_fill_y_to_q +3_0727_3609 alu_le_x_to_q +3_0744_3746 alu_sel_int_to_bus 3_0818_3471 alu47_0 3_0843_3413 alu0_5 3_0955_3427 alu0_6 3_1014_0982 reg3_0 -3_1014_1033 alu_c0 -3_1014_1219 alu_oen_dx -3_1023_3471 alu7_0 +3_1014_1033 alu_c7 +3_1014_1219 alu_oen_int_or_x_to_bus_phi1 +3_1023_3471 alu_mode_shr_hibit_arithn 3_1036_0982 reg2_0 3_1053_1093 alu_x7 3_1053_1322 alu7_2 @@ -177,34 +177,34 @@ 3_1081_0982 reg0_0 3_1090_1164 alu7_3 3_1093_1111 alu7_4 -3_1127_1244 alu567_0 +3_1127_1244 alu_set_q5_q6 3_1127_1946 alu124_0 -3_1154_3537 alu_1 -3_1167_1117 alu_sel_qd -3_1185_1141 alu_sel_qy -3_1204_1127 alu_y7 -3_1228_3471 alu_sel_zn +3_1154_3537 alu_mode2 +3_1167_1117 alu_le_bus_to_q_phi1 +3_1185_1141 alu_le_fill_y_to_q_phi1 +3_1204_1127 alu_y +3_1228_3471 alu_sel_neg 3_1241_1092 alu_q7 -3_1241_1508 alu56_0 -3_1241_1720 alu45_0 -3_1241_1931 alu34_1 -3_1241_2185 alu23_0 -3_1241_2397 alu12_0 -3_1241_2608 alu01_0 -3_1241_2837 alu0_7 -3_1259_1164 alu_sel_qx -3_1278_1129 alu_sel_od -3_1295_1153 alu_d7 -3_1295_1404 alu06_0 -3_1295_1616 alu05_0 -3_1295_1827 alu04_0 -3_1295_2081 alu03_0 -3_1295_2293 alu02_0 -3_1295_2504 alu01_1 -3_1295_2733 alu01_2 -3_1313_1198 alu_sel_ox -3_1353_1275 alu0_8 -3_1360_2891 alu_le_x +3_1241_1508 alu_q6 +3_1241_1720 alu_q5 +3_1241_1931 alu_q4 +3_1241_2185 alu_q3 +3_1241_2397 alu_q2 +3_1241_2608 alu_q1 +3_1241_2837 alu_q0 +3_1259_1164 alu_le_x_to_q_phi1 +3_1278_1129 alu_sel_int_to_bus_super +3_1295_1153 alu_int_d7 +3_1295_1404 alu_int_d6 +3_1295_1616 alu_int_d5 +3_1295_1827 alu_int_d4 +3_1295_2081 alu_int_d3 +3_1295_2293 alu_int_d2 +3_1295_2504 alu_int_d1 +3_1295_2733 alu_int_d0 +3_1313_1198 alu_sel_x_to_bus_super +3_1353_1275 alu_zero0 +3_1360_2891 alu_le_int_to_x_phi1 3_1466_1184 alu67_2 3_1466_1435 alu56_1 3_1466_1647 alu45_1 @@ -212,8 +212,8 @@ 3_1466_2112 alu23_1 3_1466_2324 alu12_1 3_1508_1143 alu67_3 -3_1510_2908 alu_10 -3_1534_3292 alu_11 +3_1510_2908 alu_mode1 +3_1534_3292 alu_mode_shr 3_1560_1186 alu7_5 3_1560_1437 alu6_0 3_1560_1649 alu5_0 @@ -223,16 +223,16 @@ 3_1560_2537 alu1_0 3_1560_2766 alu0_9 3_1576_2925 alu0_10 -3_1636_1210 alu67_4 -3_1636_1461 alu56_2 -3_1636_1673 alu45_2 -3_1636_1885 alu34_3 -3_1636_2138 alu23_2 -3_1636_2350 alu12_2 -3_1636_2561 alu01_3 -3_1698_2889 alu7_6 -3_1756_2890 alu_12 -3_1805_2922 alu_le_z +3_1636_1210 alu_c6 +3_1636_1461 alu_c5 +3_1636_1673 alu_c4 +3_1636_1885 alu_c3 +3_1636_2138 alu_c2 +3_1636_2350 alu_c1 +3_1636_2561 alu_c0 +3_1698_2889 alu_hibit +3_1756_2890 alu_mode0 +3_1805_2922 alu_le_bus_to_z 3_1812_1094 alu7_7 3_1812_1345 alu6_1 3_1812_1556 alu5_1 @@ -241,33 +241,33 @@ 3_1812_2240 alu2_1 3_1812_2445 alu1_1 3_1812_2674 alu0_11 -3_1882_2916 alu_sel_z -3_1961_3411 alu_le_r +3_1882_2916 alu_sel_pos +3_1961_3411 alu_le_bus_to_r 3_1964_2888 alu2_2 -3_1976_1127 alu_z0 -3_1976_1378 alu6_2 -3_1976_1590 alu5_2 -3_1976_1802 alu4_2 -3_1976_2056 alu3_2 -3_1976_2267 alu2_3 -3_1976_2604 alu1_2 -3_1976_2707 alu0_12 -3_1988_3526 alu_oen_r -3_1995_1475 alu26_0 +3_1976_1127 alu_z7 +3_1976_1378 alu_z6 +3_1976_1590 alu_z5 +3_1976_1802 alu_z4 +3_1976_2056 alu_z3 +3_1976_2267 alu_z2 +3_1976_2604 alu_z1 +3_1976_2707 alu_z0 +3_1988_3526 alu_oen_r_to_bus +3_1995_1475 alu_s5 3_1995_2341 alu2regf_0 -3_2012_1493 alu46_0 -3_2012_1975 alu34_4 -3_2029_1521 alu56_3 -3_2030_1731 alu5_3 +3_2012_1493 alu_s2 +3_2012_1975 alu_s4 +3_2029_1521 alu_s1 +3_2030_1731 alu_le_s1_to_r1 3_2051_1094 alu_r7 3_2051_1235 alu_r7fb -3_2051_1554 alu5_4 -3_2051_1767 alu4_3 -3_2051_1984 alu34_5 -3_2051_2194 alu2_4 -3_2051_2421 alu01_4 +3_2051_1554 alu_r1 +3_2051_1767 alu_r2 +3_2051_1984 alu_r4 +3_2051_2194 alu_r5 +3_2051_2421 alu_r6 3_2072_2894 alu0_13 -3_2146_2842 alu_17 +3_2146_2842 alu_le_s_to_r # but int_d7 to r7, and doesn't control s1 to r1 3_2278_2717 alu0_14 3_2534_0986 reg7_0 3_2558_1004 reg6_0 @@ -480,44 +480,44 @@ 4_0900_2558 alu0_16 4_0975_1934 alu4_6 4_1023_1177 alu7_12 -4_1053_1779 alu47_2 -4_1054_2029 alu3_5 -4_1057_1357 alu67_6 -4_1057_1564 alu57_0 -4_1058_2241 alu23_3 -4_1058_2452 alu13_0 +4_1053_1779 alu_x4 +4_1054_2029 alu_x3 +4_1057_1357 alu_x6 +4_1057_1564 alu_x5 +4_1058_2241 alu_x2 +4_1058_2452 alu_x1 4_1081_2988 alu0_17 4_1164_1177 alu_q7n -4_1164_1426 alu6_5 -4_1164_1638 alu5_7 -4_1164_1852 alu4_7 -4_1164_2103 alu3_6 -4_1164_2314 alu2_7 -4_1164_2526 alu1_5 -4_1164_2755 alu0_18 -4_1166_1158 alu_q0fb -4_1166_1409 alu6_6 -4_1166_1621 alu5_8 -4_1166_1832 alu4_8 -4_1166_2086 alu3_7 -4_1166_2297 alu2_8 -4_1166_2509 alu1_6 -4_1166_2738 alu0_19 +4_1164_1426 alu_q6n +4_1164_1638 alu_q5n +4_1164_1852 alu_q4n +4_1164_2103 alu_q3n +4_1164_2314 alu_q2n +4_1164_2526 alu_q1n +4_1164_2755 alu_q0n +4_1166_1158 alu_q7fb +4_1166_1409 alu_q6fb +4_1166_1621 alu_q5fb +4_1166_1832 alu_q4fb +4_1166_2086 alu_q3fb +4_1166_2297 alu_q2fb +4_1166_2509 alu_q1fb +4_1166_2738 alu_q0fb 4_1172_3006 alu0_20 4_1215_3024 alu0_21 4_1271_3078 alu0_22 -4_1282_2752 alu0_23 +4_1282_2752 alu_x0 4_1298_2929 alu0_24 4_1372_3057 alu0_25 4_1377_2904 alu0_26 4_1385_1179 alu_x7n -4_1385_1431 alu6_7 -4_1385_1643 alu5_9 -4_1385_1854 alu4_9 -4_1385_2107 alu3_8 -4_1385_2319 alu2_9 -4_1385_2531 alu1_7 -4_1385_2760 alu0_27 +4_1385_1431 alu_x6n +4_1385_1643 alu_x5n +4_1385_1854 alu_x4n +4_1385_2107 alu_x3n +4_1385_2319 alu_x2n +4_1385_2531 alu_x1n +4_1385_2760 alu_x0n 4_1542_1109 alu7_16 4_1542_1360 alu6_8 4_1542_1572 alu5_10 @@ -554,27 +554,27 @@ 4_1748_2473 alu1_11 4_1748_2702 alu0_31 4_1851_1122 alu_z7n -4_1851_1374 alu6_12 -4_1851_1586 alu5_14 -4_1851_1797 alu4_14 -4_1851_2051 alu3_13 -4_1851_2262 alu2_14 -4_1851_2474 alu1_12 -4_1851_2703 alu0_32 -4_1992_2574 alu01_5 +4_1851_1374 alu_z6n +4_1851_1586 alu_z5n +4_1851_1797 alu_z4n +4_1851_2051 alu_z3n +4_1851_2262 alu_z2n +4_1851_2474 alu_z1n +4_1851_2703 alu_z0n +4_1992_2574 alu_s6 4_2009_1178 alu_r7n -4_2009_1639 alu5_15 -4_2009_1852 alu4_15 -4_2009_2068 alu3_14 -4_2009_2278 alu2_15 -4_2009_2506 alu1_13 +4_2009_1639 alu_r1n +4_2009_1852 alu_r2n +4_2009_2068 alu_r4n +4_2009_2278 alu_r5n +4_2009_2506 alu_r6n 4_2035_2687 alu0_33 -4_2047_2611 alu0_34 -4_2053_1651 alu5_16 -4_2053_1864 alu4_16 -4_2053_2080 alu3_15 -4_2053_2290 alu2_16 -4_2053_2518 alu1_14 +4_2047_2611 alu_zero1 +4_2053_1651 alu_r1fb +4_2053_1864 alu_r2fb +4_2053_2080 alu_r4fb +4_2053_2290 alu_r5fb +4_2053_2518 alu_r6fb 4_2144_1208 alu7_25 4_2144_1669 alu5_17 4_2144_1882 alu4_17 @@ -1032,3 +1032,7 @@ 5_3851_2414 regd_37 5_3851_2509 rege_37 5_3851_2604 regf_37 +3_0654_3746 alu_oen_int_or_x_to_bus +4_1747_3376 alu_r0 +3_1707_3438 alu_r0n +3_1624_3406 alu_r0fb diff --git a/scripts/blocks.py b/scripts/blocks.py index 85c1066..6bfc145 100755 --- a/scripts/blocks.py +++ b/scripts/blocks.py @@ -1,7 +1,6 @@ #!/usr/bin/env python3 import os -import re import sys SYMBOL_TYPE_FET = 0 @@ -9,13 +8,19 @@ SYMBOL_TYPE_GATE = 1 SYMBOL_TYPE_XOR = 2 SYMBOL_TYPE_TG_LATCH = 3 SYMBOL_TYPE_TG_LATCH_FB = 4 -SYMBOL_TYPE_SUPER = 5 -SYMBOL_TYPE_NOT_SUPER = 6 -SYMBOL_TYPE_SUPER_OE = 7 -SYMBOL_TYPE_NOT_SUPER_OE = 8 -SYMBOL_TYPE_NOR_SUPER = 9 -SYMBOL_TYPE_NOR_SUPER_HD = 10 -N_SYMBOL_TYPES = 11 +SYMBOL_TYPE_TG_LATCH_CLR = 5 +SYMBOL_TYPE_TG_LATCH_CLR_FB = 6 +SYMBOL_TYPE_TG_LATCH_SET = 7 +SYMBOL_TYPE_TG_LATCH_SET_FB = 8 +SYMBOL_TYPE_SUPER = 9 +SYMBOL_TYPE_NOT_SUPER = 10 +SYMBOL_TYPE_SUPER_OE = 11 +SYMBOL_TYPE_NOT_SUPER_OE = 12 +SYMBOL_TYPE_NOR_SUPER = 13 +SYMBOL_TYPE_NOR_SUPER_HD = 14 +SYMBOL_TYPE_MUX2 = 15 +SYMBOL_TYPE_MUX2_NOT = 16 +N_SYMBOL_TYPES = 17 dump_nets = False if len(sys.argv) >= 2 and sys.argv[1] == '--dump_nets': @@ -98,119 +103,16 @@ with open(symbols_txt) as fin: nets[net].add(block) symbols.append((symbol_type, block, (y_net, expr))) - elif symbol_type == SYMBOL_TYPE_XOR: - assert len(fields) >= 3 - y_net = fields[2] - a_nets = fields[3:] + elif symbol_type < N_SYMBOL_TYPES: + # generic handler for symbols with fixed I/O assignment + nets1 = tuple(fields[2:]) - for net in [y_net] + a_nets: + for net in nets1: if net not in nets: nets[net] = set() # blocks (of symbols) that the net visits nets[net].add(block) - symbols.append((symbol_type, block, (y_net, a_nets))) - elif symbol_type == SYMBOL_TYPE_TG_LATCH: - assert len(fields) == 7 - d_net, le_net, len_net, q_net, qn_net = fields[2:] - - for net in [d_net, le_net, len_net, q_net, qn_net]: - if net not in nets: - nets[net] = set() # blocks (of symbols) that the net visits - nets[net].add(block) - - symbols.append( - ( - symbol_type, - block, - (d_net, le_net, len_net, q_net, qn_net) - ) - ) - elif symbol_type == SYMBOL_TYPE_TG_LATCH_FB: - assert len(fields) == 8 - d_net, le_net, len_net, q_net, qn_net, fb_net = fields[2:] - - for net in [d_net, le_net, len_net, q_net, qn_net, fb_net]: - if net not in nets: - nets[net] = set() # blocks (of symbols) that the net visits - nets[net].add(block) - - symbols.append( - ( - symbol_type, - block, - (d_net, le_net, len_net, q_net, qn_net, fb_net) - ) - ) - elif ( - symbol_type == SYMBOL_TYPE_SUPER or - symbol_type == SYMBOL_TYPE_NOT_SUPER - ): - assert len(fields) == 4 - a_net, y_net = fields[2:] - - for net in [a_net, y_net]: - if net not in nets: - nets[net] = set() # blocks (of symbols) that the net visits - nets[net].add(block) - - symbols.append( - ( - symbol_type, - block, - (a_net, y_net) - ) - ) - elif ( - symbol_type == SYMBOL_TYPE_SUPER_OE or - symbol_type == SYMBOL_TYPE_NOT_SUPER_OE - ): - assert len(fields) == 5 - a_net, oen_net, y_net = fields[2:] - - for net in [a_net, oen_net, y_net]: - if net not in nets: - nets[net] = set() # blocks (of symbols) that the net visits - nets[net].add(block) - - symbols.append( - ( - symbol_type, - block, - (a_net, oen_net, y_net) - ) - ) - elif symbol_type == SYMBOL_TYPE_NOR_SUPER: - assert len(fields) == 5 - a_net, b_net, y_net = fields[2:] - - for net in [a_net, b_net, y_net]: - if net not in nets: - nets[net] = set() # blocks (of symbols) that the net visits - nets[net].add(block) - - symbols.append( - ( - symbol_type, - block, - (a_net, b_net, y_net) - ) - ) - elif symbol_type == SYMBOL_TYPE_NOR_SUPER_HD: - assert len(fields) == 6 - a_net, b_net, y_net, hd_net = fields[2:] - - for net in [a_net, b_net, y_net, hd_net]: - if net not in nets: - nets[net] = set() # blocks (of symbols) that the net visits - nets[net].add(block) - - symbols.append( - ( - symbol_type, - block, - (a_net, b_net, y_net, hd_net) - ) - ) + symbols.append((symbol_type, block, nets1)) else: assert False @@ -320,14 +222,15 @@ for block, block_symbols in sorted(blocks.items()): net_node = make_net_node(y_net) fout.write(f' "{node:s}" -> "{net_node:s}"\n') elif symbol_type == SYMBOL_TYPE_XOR: - _, _, (y_net, a_nets) = symbols[i] + _, _, (a_net, b_net, y_net) = symbols[i] node = f'{symbol_type:d}:{y_net:s}' fout.write(f' "{node:s}" [shape="invhouse", label="XOR"]\n') - for a_net in a_nets: - net_node = make_net_node(a_net) - fout.write(f' "{net_node:s}" -> "{node:s}"\n') + net_node = make_net_node(a_net) + fout.write(f' "{net_node:s}" -> "{node:s}"\n') + net_node = make_net_node(b_net) + fout.write(f' "{net_node:s}" -> "{node:s}"\n') net_node = make_net_node(y_net) fout.write(f' "{node:s}" -> "{net_node:s}"\n') elif symbol_type == SYMBOL_TYPE_TG_LATCH: @@ -364,6 +267,74 @@ for block, block_symbols in sorted(blocks.items()): fout.write(f' "{node:s}" -> "{net_node:s}" [label="/Q"]\n') net_node = make_net_node(fb_net) fout.write(f' "{node:s}" -> "{net_node:s}" [label="FB"]\n') + elif ( + symbol_type == SYMBOL_TYPE_TG_LATCH_CLR or + symbol_type == SYMBOL_TYPE_TG_LATCH_SET + ): + ( + _, + _, + (d_net, le_net, len_net, clr_set_net, q_net, qn_net) + ) = symbols[i] + + node = f'{symbol_type:d}:{q_net:s}' + clr_set = ( + 'CLR' + if symbol_type == SYMBOL_TYPE_TG_LATCH_CLR else + 'SET' + ) + label = f'TG_LATCH_{clr_set:s}' + fout.write( + f' "{node:s}" [shape="invhouse", label="{label:s}"]\n' + ) + + net_node = make_net_node(d_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="D"]\n') + net_node = make_net_node(le_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="LE"]\n') + net_node = make_net_node(len_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="/LE"]\n') + net_node = make_net_node(clr_set_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="{clr_set:s}"]\n') + net_node = make_net_node(q_net) + fout.write(f' "{node:s}" -> "{net_node:s}" [label="Q"]\n') + net_node = make_net_node(qn_net) + fout.write(f' "{node:s}" -> "{net_node:s}" [label="/Q"]\n') + elif ( + symbol_type == SYMBOL_TYPE_TG_LATCH_CLR_FB or + symbol_type == SYMBOL_TYPE_TG_LATCH_SET_FB + ): + ( + _, + _, + (d_net, le_net, len_net, clr_set_net, q_net, qn_net, fb_net) + ) = symbols[i] + + node = f'{symbol_type:d}:{q_net:s}' + clr_set = ( + 'CLR' + if symbol_type == SYMBOL_TYPE_TG_LATCH_CLR_FB else + 'SET' + ) + label = f'TG_LATCH_{clr_set:s}_FB' + fout.write( + f' "{node:s}" [shape="invhouse", label="{label:s}"]\n' + ) + + net_node = make_net_node(d_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="D"]\n') + net_node = make_net_node(le_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="LE"]\n') + net_node = make_net_node(len_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="/LE"]\n') + net_node = make_net_node(clr_set_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="{clr_set:s}"]\n') + net_node = make_net_node(q_net) + fout.write(f' "{node:s}" -> "{net_node:s}" [label="Q"]\n') + net_node = make_net_node(qn_net) + fout.write(f' "{node:s}" -> "{net_node:s}" [label="/Q"]\n') + net_node = make_net_node(fb_net) + fout.write(f' "{node:s}" -> "{net_node:s}" [label="FB"]\n') elif ( symbol_type == SYMBOL_TYPE_SUPER or symbol_type == SYMBOL_TYPE_NOT_SUPER @@ -421,6 +392,24 @@ for block, block_symbols in sorted(blocks.items()): fout.write(f' "{node:s}" -> "{net_node:s}" [label="Y"]\n') net_node = make_net_node(hd_net) fout.write(f' "{node:s}" -> "{net_node:s}" [label="HD"]\n') + elif ( + symbol_type == SYMBOL_TYPE_MUX2 or + symbol_type == SYMBOL_TYPE_MUX2_NOT + ): + _, _, (a_net, b_net, s_net, y_net) = symbols[i] + + node = f'{symbol_type:d}:{y_net:s}' + label = 'MUX2' if symbol_type == SYMBOL_TYPE_MUX2 else 'MUX2_NOT' + fout.write(f' "{node:s}" [shape="invhouse", label="{label:s}"]\n') + + net_node = make_net_node(a_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="A"]\n') + net_node = make_net_node(b_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="B"]\n') + net_node = make_net_node(s_net) + fout.write(f' "{net_node:s}" -> "{node:s}" [label="S"]\n') + net_node = make_net_node(y_net) + fout.write(f' "{node:s}" -> "{net_node:s}" [label="Y"]\n') else: assert False fout.write('}\n') diff --git a/scripts/circuits.py b/scripts/circuits.py index dece518..8a855d6 100755 --- a/scripts/circuits.py +++ b/scripts/circuits.py @@ -9,30 +9,36 @@ SYMBOL_TYPE_GATE = 1 SYMBOL_TYPE_XOR = 2 SYMBOL_TYPE_TG_LATCH = 3 SYMBOL_TYPE_TG_LATCH_FB = 4 -SYMBOL_TYPE_SUPER = 5 -SYMBOL_TYPE_NOT_SUPER = 6 -SYMBOL_TYPE_SUPER_OE = 7 -SYMBOL_TYPE_NOT_SUPER_OE = 8 -SYMBOL_TYPE_NOR_SUPER = 9 -SYMBOL_TYPE_NOR_SUPER_HD = 10 -N_SYMBOL_TYPES = 11 +SYMBOL_TYPE_TG_LATCH_CLR = 5 +SYMBOL_TYPE_TG_LATCH_CLR_FB = 6 +SYMBOL_TYPE_TG_LATCH_SET = 7 +SYMBOL_TYPE_TG_LATCH_SET_FB = 8 +SYMBOL_TYPE_SUPER = 9 +SYMBOL_TYPE_NOT_SUPER = 10 +SYMBOL_TYPE_SUPER_OE = 11 +SYMBOL_TYPE_NOT_SUPER_OE = 12 +SYMBOL_TYPE_NOR_SUPER = 13 +SYMBOL_TYPE_NOR_SUPER_HD = 14 +SYMBOL_TYPE_MUX2 = 15 +SYMBOL_TYPE_MUX2_NOT = 16 +N_SYMBOL_TYPES = 17 CIRCUITS = [ # XOR gate as follows: - # int = a NOR b - # q = (a AND b) NOR int + # x = a NOR b + # y = (a AND b) NOR x # virtual nets are: # 0 = a # 1 = b - # 2 = int - # 3 = out + # 2 = x + # 3 = y ( [ (SYMBOL_TYPE_GATE, (3, [[0, 1], [2]])), (SYMBOL_TYPE_GATE, (2, [[0], [1]])), ], [ - (SYMBOL_TYPE_XOR, (3, [0, 1])), + (SYMBOL_TYPE_XOR, (0, 1, 3)), ], [False, False, True, False], ), @@ -72,6 +78,80 @@ CIRCUITS = [ ], [False, False, False, False, False, False] ), + # transmission-gate latch with d, le, /le, clr, q, /q as follows: + # fb = le ? d : /le ? q : Z + # /q = fb + # q = clr NOR /q + # virtual nets are: + # 0 = d + # 1 = le + # 2 = /le + # 3 = clr + # 4 = fb + # 5 = /q + # 6 = q + ( + [ + (SYMBOL_TYPE_GATE, (5, [[4]])), + (SYMBOL_TYPE_GATE, (6, [[3], [5]])), + (SYMBOL_TYPE_FET, (1, [0, 4])), + (SYMBOL_TYPE_FET, (2, [4, 6])), + ], + [ + (SYMBOL_TYPE_TG_LATCH_CLR, (0, 1, 2, 3, 6, 5)), + ], + [False, False, False, False, True, False, False] + ), + # special case of SYMBOL_TYPE_TG_LATCH_CLR where fb signal is external + ( + [ + (SYMBOL_TYPE_GATE, (5, [[4]])), + (SYMBOL_TYPE_GATE, (6, [[3], [5]])), + (SYMBOL_TYPE_FET, (1, [0, 4])), + (SYMBOL_TYPE_FET, (2, [4, 6])), + ], + [ + (SYMBOL_TYPE_TG_LATCH_CLR_FB, (0, 1, 2, 3, 6, 5, 4)), + ], + [False, False, False, False, False, False, False] + ), + # transmission-gate latch with d, le, /le, set, q, /q as follows: + # fb = le ? d : /le ? q : Z + # /q = set NOR fb + # q = NOT /q + # virtual nets are: + # 0 = d + # 1 = le + # 2 = /le + # 3 = set + # 4 = fb + # 5 = /q + # 6 = q + ( + [ + (SYMBOL_TYPE_GATE, (5, [[3], [4]])), + (SYMBOL_TYPE_GATE, (6, [[5]])), + (SYMBOL_TYPE_FET, (1, [0, 4])), + (SYMBOL_TYPE_FET, (2, [4, 6])), + ], + [ + (SYMBOL_TYPE_TG_LATCH_SET, (0, 1, 2, 3, 6, 5)), + ], + [False, False, False, False, True, False, False] + ), + # special case of SYMBOL_TYPE_TG_LATCH_SET where fb signal is external + ( + [ + (SYMBOL_TYPE_GATE, (5, [[3], [4]])), + (SYMBOL_TYPE_GATE, (6, [[5]])), + (SYMBOL_TYPE_FET, (1, [0, 4])), + (SYMBOL_TYPE_FET, (2, [4, 6])), + ], + [ + (SYMBOL_TYPE_TG_LATCH_SET_FB, (0, 1, 2, 3, 6, 5, 4)), + ], + [False, False, False, False, False, False, False] + ), # non-inverting superbuffer with a, y as follows: # ld = NOT a # y = a ? VCC : ld ? GND : Z @@ -227,6 +307,47 @@ CIRCUITS = [ ], [False, False, False, False], ), + # 2-input multiplexer with a, b, s, y as follows: + # /s = NOT s + # /y = (/s AND a) NOR (s AND b) + # y = NOT /y + # virtual nets are: + # 0 = a + # 1 = b + # 2 = s + # 3 = /s + # 4 = /y + # 5 = y + ( + [ + (SYMBOL_TYPE_GATE, (3, [[2]])), + (SYMBOL_TYPE_GATE, (4, [[3, 0], [2, 1]])), + (SYMBOL_TYPE_GATE, (5, [[4]])), + ], + [ + (SYMBOL_TYPE_MUX2, (0, 1, 2, 5)), + ], + [False, False, False, True, True, False], + ), + # 2-input multiplexer with inverted output and a, b, s, y as follows: + # /s = NOT s + # y = (/s AND a) NOR (s AND b) + # virtual nets are: + # 0 = a + # 1 = b + # 2 = s + # 3 = /s + # 4 = y + ( + [ + (SYMBOL_TYPE_GATE, (3, [[2]])), + (SYMBOL_TYPE_GATE, (4, [[3, 0], [2, 1]])), + ], + [ + (SYMBOL_TYPE_MUX2_NOT, (0, 1, 2, 4)), + ], + [False, False, False, True, False], + ), ] if len(sys.argv) < 4: @@ -498,7 +619,9 @@ print('output') with open(circuits_txt, 'w') as fout: for i in range(len(symbols)): symbol_type = symbols[i][0] - if symbol_type == SYMBOL_TYPE_FET: + if symbol_type == -1: + pass # deleted + elif symbol_type == SYMBOL_TYPE_FET: [ _, block, @@ -531,49 +654,9 @@ with open(circuits_txt, 'w') as fout: print(symbol_type, block, y_net, len(expr), file = fout) for i in expr: print(' ' + ' '.join(i), file = fout) - elif symbol_type == SYMBOL_TYPE_XOR: - [_, block, (y_net, a_nets)] = symbols[i] - print(symbol_type, block, y_net, ' '.join(a_nets), file = fout) - elif symbol_type == SYMBOL_TYPE_TG_LATCH: - [_, block, (d_net, le_net, len_net, q_net, qn_net)] = symbols[i] - print( - symbol_type, - block, - d_net, - le_net, - len_net, - q_net, - qn_net, - file = fout - ) - elif symbol_type == SYMBOL_TYPE_TG_LATCH_FB: - [_, block, (d_net, le_net, len_net, q_net, qn_net, fb_net)] = symbols[i] - print( - symbol_type, - block, - d_net, - le_net, - len_net, - q_net, - qn_net, - fb_net, - file = fout - ) - elif ( - symbol_type == SYMBOL_TYPE_SUPER or - symbol_type == SYMBOL_TYPE_NOT_SUPER - ): - [_, block, (a_net, y_net)] = symbols[i] - print(symbol_type, block, a_net, y_net, file = fout) - elif ( - symbol_type == SYMBOL_TYPE_SUPER_OE or - symbol_type == SYMBOL_TYPE_NOT_SUPER_OE - ): - [_, block, (a_net, oen_net, y_net)] = symbols[i] - print(symbol_type, block, a_net, oen_net, y_net, file = fout) - elif symbol_type == SYMBOL_TYPE_NOR_SUPER: - [_, block, (a_net, b_net, y_net)] = symbols[i] - print(symbol_type, block, a_net, b_net, y_net, file = fout) - elif symbol_type == SYMBOL_TYPE_NOR_SUPER_HD: - [_, block, (a_net, b_net, y_net, hd_net)] = symbols[i] - print(symbol_type, block, a_net, b_net, y_net, hd_net, file = fout) + elif symbol_type < N_SYMBOL_TYPES: + # generic handler for symbols with fixed I/O assignment + [_, block, nets1] = symbols[i] + print(symbol_type, block, ' '.join(nets1), file = fout) + else: + assert False diff --git a/scripts/gates.py b/scripts/gates.py index 45fecc3..963fc18 100755 --- a/scripts/gates.py +++ b/scripts/gates.py @@ -146,7 +146,9 @@ print('output') with open(gates_txt, 'w') as fout: for i in range(len(symbols)): symbol_type = symbols[i][0] - if symbol_type == SYMBOL_TYPE_FET: + if symbol_type == -1: + pass # deleted + elif symbol_type == SYMBOL_TYPE_FET: [ _, block, @@ -179,3 +181,5 @@ with open(gates_txt, 'w') as fout: print(symbol_type, block, y_net, len(expr), file = fout) for i in expr: print(' ' + ' '.join(i), file = fout) + else: + assert False diff --git a/scripts/join_lines.sh b/scripts/join_lines.sh new file mode 100755 index 0000000..220ffca --- /dev/null +++ b/scripts/join_lines.sh @@ -0,0 +1,8 @@ +#!/bin/sh + +# join continuation lines that start with whitespace (see sed documentation) + +sed -E ':a ; $!N ; s/\n\s+/ / ; ta ; P ; D' + +# A portable (non-gnu) variation: +# sed -e :a -e '$!N;s/\n */ /;ta' -e 'P;D' -- 2.34.1