From 04736784912bd45613126bf8b1f010e67b878f9d Mon Sep 17 00:00:00 2001 From: sater Date: Wed, 18 Jul 1984 11:05:28 +0000 Subject: [PATCH] added patterns for unsigned shifting added patterns to delay additive operations until after multiplicative, this can be useful for some register machines --- util/opt/patterns | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/util/opt/patterns b/util/opt/patterns index 163eb792e..d6b685431 100644 --- a/util/opt/patterns +++ b/util/opt/patterns @@ -3,6 +3,8 @@ loc adi loc sbi $2==w && $4==w: loc $1-$3 adi w ldc adi ldc sbi $2==2*w && $4==2*w: ldc $1-$3 adi 2*w loc adi loc adi $2==w && $4==w: loc $1+$3 adi w ldc adi ldc adi $2==2*w && $4==2*w: ldc $1+$3 adi 2*w +loc adi loc mli $2==w && $4==w: loc $3 mli w loc $1*$3 adi w +loc adi loc sli $2==w && $4==w && $3==1: loc $3 sli w loc 2*$1 adi w adp $1==0: adp adp : adp $1+$2 adp lof : lof $1+$2 @@ -167,6 +169,14 @@ loc mli $1==32 && $2==w: loc 5 sli w loc mli $1==64 && $2==w: loc 6 sli w loc mli $1==128 && $2==w: loc 7 sli w loc mli $1==256 && $2==w: loc 8 sli w +loc mlu $1==2 && $2==w: loc 1 slu w +loc mlu $1==4 && $2==w: loc 2 slu w +loc mlu $1==8 && $2==w: loc 3 slu w +loc mlu $1==16 && $2==w: loc 4 slu w +loc mlu $1==32 && $2==w: loc 5 slu w +loc mlu $1==64 && $2==w: loc 6 slu w +loc mlu $1==128 && $2==w: loc 7 slu w +loc mlu $1==256 && $2==w: loc 8 slu w loc adi !defined($2): adi $1 loc sbi !defined($2): sbi $1 loc mli !defined($2): mli $1 @@ -314,6 +324,8 @@ loc sbi loc sbi $2==w && $4==w: loc $1+$3 sbi w ldc sbi ldc sbi $2==2*w && $4==2*w: ldc $1+$3 sbi 2*w loc sbi loc adi $2==w && $4==w: loc $1-$3 sbi w ldc sbi ldc adi $2==2*w && $4==2*w: ldc $1-$3 sbi 2*w +loc sbi loc mli $2==w && $4==w: loc $3 mli w loc $1*$3 sbi w +loc sbi loc sli $2==w && $4==w && $3==1: loc $3 sli w loc 2*$1 sbi w teq teq : tne teq tne : teq teq zne : zeq $2 -- 2.34.1