From: sater <none@none>
Date: Tue, 4 Dec 1984 15:33:28 +0000 (+0000)
Subject: Initial revision
X-Git-Tag: release-5-5~5898
X-Git-Url: https://git.ndcode.org/public/gitweb.cgi?a=commitdiff_plain;h=d9fe7e9cf053a36b7ded39d5309f7c6c0fbcd211;p=ack.git

Initial revision
---

diff --git a/man/6805_as.1 b/man/6805_as.1
new file mode 100644
index 000000000..4cb2a7dce
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+.\" $Header$
+.TH 6805_AS 1
+.ad
+.SH NAME
+6805_as \- assembler for Motorola 6805
+.SH SYNOPSIS
+/usr/em/lib/6805_as [options] argument ...
+.SH DESCRIPTION
+This assembler is made with the general framework
+described in \fIuni_ass\fP(6).
+.SH SYNTAX
+.IP registers
+The 6805 has an accumulator register A and an index register X. An
+instruction (from the read-modify-write group) that references the
+A-register has an "a" suffixed to the mnemonic. In a similar way
+the X-register, apart from indexing operations, is addressed with
+an "x" suffix, i.e. "lsra" and "negx".
+.IP "addressing modes"
+The assembler automatically selects the shortest opcode if
+appropriate and possible. Thus "sub 10" will use the direct
+addressing mode whereas "neg 0,x" will use indexed (no offset) mode.
+There are sick constructions where the assembler can't find out
+the shortest form in time. In those cases the longest form is used.
+.br
+Branches are handled in much the same way. If a branch is out of
+range it is replaced by a reversed condition branch, followed by
+a jump, automatically.
+.sp
+.nf
+.ta 8 16 24 32 40 48
+syntax		meaning (name)
+
+#expr		a one byte value (immediate)
+<expr		1-byte zero page address. Allowed in  
+		the register/memory and read-modify-
+		write instruction groups. (direct)
+>expr		2-byte address. Allowed in the register
+		memory group. (extended)
+expr		1-byte address if appropriate, 2-byte 
+		in other cases. (auto-direct/extended)
+,x		indexed with zero offset. (indexed)
+<expr,x		indexed with 8 bit offset. (indexed-1)
+>expr,x		indexed with 16 bit offset. (indexed-2)
+expr,x		indexed with the shortest possible off-
+		set. (auto indexed)
+bit,expr	bit number and direct address. 
+		(bit set/clear)
+bit,expr,tag	bit number, direct address and branch 
+		tag. Automatically changed to reversed 
+		condition branch and jump if appropri-
+		ate. (bit test and branch)
+tag		branch tag. Converted to reversed con-
+		dition branch and jump if appropriate. 
+		(branch)
+.fi
+.IP "PSEUDO INSTRUCTIONS"
+ 
+ .dram		use the zero page ram/io segment.
+ .dprom		use the zero page (ep)rom segment.
+ .cmos		assemble cmos version instructions.
+.SH "SEE ALSO"
+uni_ass(6),
+ack(1),
+.br
+M6805 HMOS, M146805 CMOS family, Motorola, 
+Prentice-Hall, Inc., 1983, (ISBN 0-13-541375-3).
+.SH EXAMPLE
+An example of Motorola 6805 assembly code.
+.sp 2
+.nf
+.ta 8 16 32 40 48 56 64
+.dram
+one:	.space	1		! a-port
+.dprom
+c1:	.byte	1
+.text
+start:	ldx	#c1		! load address of c1
+	txa
+	sta	one
+	add	c1		! add one
+	brset	1,one,whoop	! jif bit one of aport 
+	bset	1,one		! set it now
+.data
+	.ascii	"unused string"
+.text
+whoop:	nop
+.org 0xff8
+	.word	start		! set vector address
+.text	
+	nop			! resume code
+.fi
+.SH AUTHOR
+Written by Gijs Mos.
+Not a member of the ACK group.
+.SH BUGS
+The assembler has not been well tested.