From: David Given Date: Sat, 21 Jan 2017 22:21:33 +0000 (+0100) Subject: Loading longs might corrupt the input register (if the output register pair X-Git-Url: https://git.ndcode.org/public/gitweb.cgi?a=commitdiff_plain;h=b9757724559803181a7eca3c92f177a9110b1df4;p=ack.git Loading longs might corrupt the input register (if the output register pair aliases it). --- diff --git a/mach/powerpc/mcg/table b/mach/powerpc/mcg/table index 496101238..340652cd4 100644 --- a/mach/powerpc/mcg/table +++ b/mach/powerpc/mcg/table @@ -307,6 +307,7 @@ PATTERNS cost 4; out:(long)reg = LOAD.L(addr:address) + with corrupted(%addr) emit "lwz %out.0, 4+%addr" emit "lwz %out.1, 0+%addr" cost 8;