From: ceriel Date: Wed, 10 Jan 1990 11:23:45 +0000 (+0000) Subject: bug fix: cannot optimize IMUL X-Git-Tag: release-5-5~1964 X-Git-Url: https://git.ndcode.org/public/gitweb.cgi?a=commitdiff_plain;h=776f85238f8c4b1719ab63fbbec92ce0caf6eda0;p=ack.git bug fix: cannot optimize IMUL --- diff --git a/mach/i386/as/mach4.c b/mach/i386/as/mach4.c index 7dda649ef..c5cb214bc 100644 --- a/mach/i386/as/mach4.c +++ b/mach/i386/as/mach4.c @@ -88,9 +88,9 @@ oper : NOOP_1 | IMUL ea_2 { reg_1 = IS_R32; imul(0); } | IMUL R32 ',' ea_2 - { reg_1 = $2 | IS_R32; imul($2); } + { reg_1 = $2 | IS_R32; imul($2|0x10); } | IMUL R32 ',' ea_ea - { imul($2);} + { imul($2|0x10);} | INT absexp { if ($2==3) emit1(0314); diff --git a/mach/i386/as/mach5.c b/mach/i386/as/mach5.c index 4a483331e..a2370f8e8 100644 --- a/mach/i386/as/mach5.c +++ b/mach/i386/as/mach5.c @@ -507,23 +507,30 @@ imul(reg) if (exp_2.typ == S_ABS && fitb(exp_2.val)) { /* case 1: 1 byte encoding of immediate */ emit1(0153); - ea_1(reg << 3); + ea_1((reg & 07) << 3); emit1((int)(exp_2.val)); } else { /* case 2: WORD or DWORD encoding of immediate */ emit1(0151); - ea_1(reg << 3); + ea_1((reg & 07) << 3); RELOMOVE(relonami, rel_2); opsize_exp(exp_2, 1); } } - else if (is_reg(reg_1) && ((reg_1&7) == reg)) { + else if (is_reg(reg_1) && ((reg_1&7) == (reg & 07))) { /* the "reg" field and the "reg_or_mem" field are the same, and the 3rd operand is not an immediate ... */ if (reg == 0) { /* how lucky we are, the target is the ax register */ + /* However, we cannot make an optimization for f.i. + imul eax, blablabla + because the latter does not affect edx, whereas + imul blablabla + does! Therefore, "reg" is or-ed with 0x10 in the + former case, so that the test above fails. + */ emit1(0367); ea_2(050); } @@ -531,7 +538,7 @@ imul(reg) /* another register ... */ emit1(0xF); emit1(0257); - ea_2(reg << 3); + ea_2((reg & 07) << 3); } } else badsyntax();