From: ceriel <none@none>
Date: Fri, 21 Jul 1995 12:05:26 +0000 (+0000)
Subject: Fixes: some conditionals were evaluated wrong due to the overflow bit
X-Git-Tag: release-5-5~116
X-Git-Url: https://git.ndcode.org/public/gitweb.cgi?a=commitdiff_plain;h=5e03b1bebb25f070839afe8ed0e26ba810b16c76;p=ack.git

Fixes: some conditionals were evaluated wrong due to the overflow bit
---

diff --git a/mach/i386/ncg/table b/mach/i386/ncg/table
index e2580d93c..a41d7a5f5 100644
--- a/mach/i386/ncg/table
+++ b/mach/i386/ncg/table
@@ -227,6 +227,7 @@ jcxz label cost(1,4).
 je label cost(1,4).
 jg label cost(1,4).
 jge label cost(1,4).
+jgt label cost(1,4).
 jl label cost(1,4).
 jle label cost(1,4).
 jne label cost(1,4).
@@ -234,6 +235,8 @@ jmp label cost(1,4).
 proccall "call" label+rm cost(1,8).
 jxx "syntax error" label cost(1,4).
 setxx "syntax error" REG:rw cost(2,4).
+setle REG:rw cost(2,4).
+setgt REG:rw cost(2,4).
 lea anyreg:rw, halfindir:ro.
 lea LOCAL:rw, halfindir:ro.	/* only for register variables, UNSAFE!!! */
 leave cost(1,4).
@@ -299,6 +302,7 @@ xorw "o16 xor" rm2:rw:cc, regorconst124:ro.
 xorw "o16 xor" anyreg:rw:cc, rmorconst2:ro.
 
 killreg "! kill" anyreg:wo cost(0,0).
+killcc "! kill cc" kills:cc cost(0,0).
 
 
 /*****************************************************************/
@@ -2452,12 +2456,31 @@ uses REG = {ANYCON,0}
   gen test %1
       setxx* %a			    yields %a
 
-pat tlt call txx("setl")
-pat tle call txx("setle")
+pat tlt call txx("sets")
 pat teq call txx("sete")
 pat tne call txx("setne")
-pat tge call txx("setge")
-pat tgt call txx("setg")
+pat tge call txx("setns")
+
+/* Explicit test for TLE and TGT. We must make sure that the OC
+   flag is cleared.
+*/
+pat tle
+with rm
+uses REG = {ANYCON,0}
+  gen
+      killcc.
+      test %1
+      setle %a
+				   yields %a
+
+pat tgt
+with rm
+uses REG = {ANYCON,0}
+  gen
+      killcc.
+      test %1
+      setgt %a
+				   yields %a
 
 proc txxior
 with rm REG
@@ -2657,10 +2680,25 @@ with rm STACK
   gen test %1
       jxx* {label,$1}
 
-pat zlt		call zxx("jl")
-pat zle		call zxx("jle")
-pat zge		call zxx("jge")
-pat zgt		call zxx("jg")
+pat zlt		call zxx("js")
+pat zge		call zxx("jns")
+
+/* Explicit test for ZLE and ZGT. We must make sure that the OC
+   flag is cleared.
+*/
+pat zle
+with rm STACK
+  gen 
+      killcc.
+      test %1
+      jle {label,$1}
+
+pat zgt
+with rm STACK
+  gen
+      killcc.
+      test %1
+      jgt {label, $1}
 
 pat zne
 with rm+rm1 STACK
diff --git a/mach/i86/ncg/table b/mach/i86/ncg/table
index 7e8f4d4d1..ffbd7101e 100644
--- a/mach/i86/ncg/table
+++ b/mach/i86/ncg/table
@@ -268,6 +268,7 @@ xor anyreg:rw:cc, rmorconst:ro.
 xorb rm1:rw:cc, regorconst12:ro.
 xorb anyreg:rw:cc, rm1:ro.
 killreg "! kill" anyreg:wo cost(0,0).
+killcc "! kill cc" kills:cc cost(0,0).
 
 data ".sect .data".
 word ".data2" const:ro.
@@ -2644,12 +2645,32 @@ uses REG = {ANYCON,0}
       inc %a
       1:                            yields %a
 
-pat tlt call txx("jge")
-pat tle call txx("jg")
+pat tlt call txx("jns")
 pat teq call txx("jne")
 pat tne call txx("je")
-pat tge call txx("jl")
-pat tgt call txx("jle")
+pat tge call txx("js")
+
+/* For the next two patterns there is no I8086 test instruction (one that
+   ignores the OF flag. Therefore, condition codes are killed and the test
+   is done again.
+*/
+pat tgt
+with rm
+uses REG = {ANYCON, 0}
+  gen killcc.
+      test %1
+      jle {label, 1f}
+      inc %a
+      1:			    yields %a
+
+pat tle
+with rm
+uses REG = {ANYCON, 0}
+  gen killcc.
+      test %1
+      jg {label, 1f}
+      inc %a
+      1:			    yields %a
 
 proc txxior
 with rm REG
@@ -2658,12 +2679,30 @@ with rm REG
       or  %2,{ANYCON,1}
       1:                            yields %2
 
-pat tlt ior $2==2 call txxior("jge")
-pat tle ior $2==2 call txxior("jg")
+pat tlt ior $2==2 call txxior("jns")
+pat tge ior $2==2 call txxior("js")
 pat teq ior $2==2 call txxior("jne")
 pat tne ior $2==2 call txxior("je")
-pat tge ior $2==2 call txxior("jl")
-pat tgt ior $2==2 call txxior("jle")
+
+/* For the next two patterns there is no I8086 test instruction (one that
+   ignores the OF flag. Therefore, condition codes are killed and the test
+   is done again.
+*/
+pat tle ior $2==2
+with rm REG
+  gen killcc.
+      test %1
+      jg {label,1f}
+      or  %2,{ANYCON,1}
+      1:                            yields %2
+
+pat tgt ior $2==2
+with rm REG
+  gen killcc.
+      test %1
+      jle {label,1f}
+      or  %2,{ANYCON,1}
+      1:                            yields %2
 
 proc cmixxior
 with regorconst rm REG
@@ -3013,10 +3052,24 @@ with rm STACK
   gen test %1
       jxx* {label,$1}
 
-pat zlt		call zxx("jl")
-pat zle		call zxx("jle")
-pat zge		call zxx("jge")
-pat zgt		call zxx("jg")
+pat zlt		call zxx("js")
+pat zge		call zxx("jns")
+
+/* For the next two patterns there is no I8086 test instruction (one that
+   ignores the OF flag. Therefore, condition codes are killed and the test
+   is done again.
+*/
+pat zle
+with rm STACK
+  gen killcc.
+      test %1
+      jle {label,$1}
+
+pat zgt
+with rm STACK
+  gen killcc.
+      test %1
+      jg {label,$1}
 
 pat zne
 with rm+rm1 STACK