image:
sdasz80 -o bootrom.s
sdldz80 -m -i bootrom.rel
- makebin -s 256 bootrom.ihx > bootrom.bin
- cat bootrom.bin ../fuzix.bin > fuzix.rom
+ makebin -s 136 bootrom.ihx > bootrom.bin
+ cat bootrom.bin ../fuzix.bin | dd conv=sync bs=65536 count=1 of=fuzix.rom
../cpm-loader/makecpmloader ../cpm-loader/cpmload.bin ../fuzix.bin 0x88 fuzix.com
/* UART0 as the console */
#define BOOT_TTY (512 + 1)
- #define TTY_INIT_BAUD B115200
+ #define TTY_INIT_BAUD B38400
#endif
#define TTYDEV BOOT_TTY /* Device used by kernel for messages, panics */
.area _DISCARD
.area _COMMONMEM
+ ; exported symbols
+ .globl init
+ .globl init_from_rom
+ .globl _boot_from_rom
+
; imported symbols
.globl _fuzix_main
.globl init_early
; startup code
.area _CODE
-init:
+init: ; must be at 0x88 -- warm boot methods enter here
+ xor a
+ jr init_common
+init_from_rom: ; must be at 0x8B -- bootrom.s enters here
+ ld a, #1
+ ; fall through
+init_common:
di
ld sp, #kstack_top
; move the common memory where it belongs
ld bc, #l__DATA - 1
ld (hl), #0
ldir
+
+ ; save ROM boot flag
+ ld (_boot_from_rom), a
; setup the rest of the memory paging
call init_early
di
stop: halt
jr stop
+
+ .area _DATA
+_boot_from_rom: .ds 1
uint8_t lcr = 0;
if (minor == 1) {
b = ttydata[minor].termios.c_cflag & CBAUD;
- if (b > 0 && b < 16) {
+ if (boot_from_rom && b > 0 && b < 16) {
UART0_LCR = 0x80; /* LCR = DLAB ON */
UART0_DLL = divisor_table[b] & 0xFF;
UART0_DLH = divisor_table[b] >> 8;
.globl unix_syscall_entry
.globl nmi_handler
.globl null_handler
+ .globl _boot_from_rom
; exported debugging tools
.globl inchar
ld (_procmem), hl
; initialize UART0
+ ld a, (_boot_from_rom) ; do not set the baud rate and other
+ or a ; serial line parameters if the BIOS
+ jr z, init_partial_uart ; already set them for us.
ld a,#0x80 ; LCR = DLAB ON
out (UART0_LCR),a ; set LCR
ld a,#CONSOLE_DIVISOR_LOW ; baud rate divisor - low byte
out (UART0_DLL),a ; set low byte of divisor
ld a,#CONSOLE_DIVISOR_HIGH ; baud rate divisor - high byte
out (UART0_DLH),a ; set high byte of divisor
- ld a,#0x03 ; value for LCR and MCR
+ ld a,#0x03 ; value for LCR
out (UART0_LCR),a ; 8 bit data, 1 stop, no parity
+init_partial_uart:
+ ld a,#0x03 ; value for MCR
out (UART0_MCR),a ; DTR ON, RTS ON
ld a,#0x06 ; disable and clear FIFOs
out (UART0_FCR),a