DISCARD_CSRCS = discard.c
DISCARD_DSRCS = ../dev/devide_discard.c ../dev/ds1302_discard.c
DSRCS = ../dev/devfd.c ../dev/devide.c ../dev/mbr.c ../dev/blkdev.c
-DSRCS += ../dev/ds1302.c
+DSRCS += ../dev/ds1302.c ../dev/ppide_rbc.c
DASRCS = ../dev/devfd_hw.s ../dev/ds1302_rc2014.s
NSRCS = ../dev/net/net_native.c
+/* System level configuration */
+
+/* Set this if you have the RC2014 CF adapter at 0x10/0x90 */
+#define CONFIG_RC2014_CF
+/* Set this to be able to do networking over the second serial port */
+#define CONFIG_RC2014_NET
+/* Set this if you have the 8255 IDE adapter (mutually exclusive of RC2014_CF) */
+#undef CONFIG_RC2014_PPIDE
+/* Set this if you have the floppy interface */
+#undef CONFIG_RC2014_FLOPPY
+/* Set this if you have a VFD interface */
+#undef CONFIG_RC2014_VFD
+
+
+/*
+ * Turn selections into system level defines
+ */
+
+#ifdef CONFIG_RC2014_CF
+#define CONFIG_IDE
+#endif
+#ifdef CONFIG_RC2014_PPIDE
+#define CONFIG_IDE
+#define CONFIG_PPIDE
+#endif
+#ifdef CONFIG_RC2014_NET
+/* Core Networking support */
+#define CONFIG_NET
+/* User mode uIP TCP/IP daemon */
+#define CONFIG_NET_NATIVE
+#endif
+#ifdef CONFIG_RC2014_FLOPPY
+#define CONFIG_FLOPPY
+#endif
+#ifdef CONFIG_RC2014_VFD
+#define CONFIG_VFD_TERM
+#endif
+
/* Enable to make ^Z dump the inode table for debug */
#undef CONFIG_IDUMP
/* Enable to make ^A drop back into the monitor */
#define PROGTOP 0xD000 /* Top of program, base of U_DATA copy */
/* FIXME: check this... for discard looks wrong */
#define KERNTOP 0xC000 /* Top of kernel (first 3 banks), base of shared bank */
-#define PROC_SIZE 64 /* Memory needed per process */
//#define SWAPDEV (swap_dev) /* A variable for dynamic, or a device major/minor */
extern unsigned int swap_dev;
#define CONFIG_RTC_FULL
#define CONFIG_NO_CLOCK
-/* Floppy support */
-#define CONFIG_FLOPPY /* #define CONFIG_FLOPPY to enable floppy */
-/* IDE/CF support */
-#define CONFIG_IDE
-
-#undef CONFIG_VFD_TERM /* #define CONFIG_VFD_TERM to show console output on VFD display */
-
#define CONFIG_INPUT /* Input device for joystick */
#define CONFIG_INPUT_GRABMAX 0 /* No keyboard to grab */
-/* Core Networking support */
-#define CONFIG_NET
-/* User mode uIP TCP/IP daemon */
-#define CONFIG_NET_NATIVE
-
#define NUM_DEV_TTY 2
-
/* UART0 as the console */
#define BOOT_TTY (512 + 1)
#define TTY_INIT_BAUD B115200 /* Hardwired generally */
a fancier autodetect! Also you'll need to change rc2014.s */
#undef CONFIG_SIO_BAKER
-#define platform_copyright() // for now
\ No newline at end of file
+#define platform_copyright() // for now
uint8_t progress;
/* Check for an interrupt */
- SIOA_C = 0;
- if (!(SIOA_C & 2))
- return;
+// SIOA_C = 0;
+// if (!(SIOA_C & 2))
+// return;
/* FIXME: need to process error/event interrupts as we can get
spurious characters or lines on an unused SIO floating */
#include <ds1302.h>
#include <devide.h>
#include <blkdev.h>
+#include <ppide.h>
#include "config.h"
#include "devrd.h"
#include "vfd-term.h"
void init_hardware_c(void)
{
#ifdef CONFIG_VFD_TERM
- vfd_term_init();
+ vfd_term_init();
#endif
- ramsize = 512;
- procmem = 512 - 80;
+ ramsize = 512;
+ procmem = 512 - 80;
}
void pagemap_init(void)
* corresponding pages are 32-63 (page size is 16 KiB)
* Pages 32-34 are used by the kernel
* Page 35 is the common area for init
- * Page 36 is the disk cache
+ * Page 36 is the disk cache
*/
for (i = 32 + 5; i < 64; i++)
pagemap_add(i);
void map_init(void)
{
/* Point the buffers into the 16-32K range that will be used by
- the buffer remap. It's an ideal location because it has no
- vectors and is low enough it will overlay only code so we never
- worry about copying into the overlaid address space */
+ the buffer remap. We offset by 0x4000 if need be in the access
+ functions when handling overlaps */
bufptr bp = bufpool;
- uint8_t *p = (uint8_t *)0x4000;
- while(bp < bufpool_end) {
+ uint8_t *p = (uint8_t *) 0x4000;
+ while (bp < bufpool_end) {
bp++->__bf_data = p;
p += BLKSIZE;
}
*/
void platform_swap_found(uint8_t letter, uint8_t m)
{
- blkdev_t *blk = blk_op.blkdev;
- uint16_t n;
- if (swap_dev != 0xFFFF)
- return;
- letter -= 'a';
- kputs("(swap) ");
- swap_dev = letter << 4 | m;
- n = blk->lba_count[m - 1] / SWAP_SIZE;
- if (n > MAX_SWAPS)
- n = MAX_SWAPS;
+ blkdev_t *blk = blk_op.blkdev;
+ uint16_t n;
+ if (swap_dev != 0xFFFF)
+ return;
+ letter -= 'a';
+ kputs("(swap) ");
+ swap_dev = letter << 4 | m;
+ n = blk->lba_count[m - 1] / SWAP_SIZE;
+ if (n > MAX_SWAPS)
+ n = MAX_SWAPS;
#ifdef SWAPDEV
- while(n)
- swapmap_add(n--);
+ while (n)
+ swapmap_add(n--);
#endif
}
ds1302_init();
#ifdef CONFIG_IDE
devide_init();
+#ifdef CONFIG_PPIDE
+ ppide_init();
+#endif
#endif
}
#define ide_select(x)
#define ide_deselect()
-/*8bit, no altstatus/control */
+#ifndef CONFIG_PPIDE
+
+/*CF card: 8bit, no altstatus/control */
#define IDE_8BIT_ONLY
#define IDE_REG_CS1_BASE 0x10
+
+#else
+
+/* PPIDE */
+
+#define PPIDE_BASE 0x60 /* Base address of 8255A */
+#define IDE_REG_INDIRECT /* IDE registers are not directly connected to the CPU bus */
+
+/* IDE control signal to 8255 port C mapping */
+#define PPIDE_A0_LINE 0x01 // Direct from 8255 to IDE interface
+#define PPIDE_A1_LINE 0x02 // Direct from 8255 to IDE interface
+#define PPIDE_A2_LINE 0x04 // Direct from 8255 to IDE interface
+#define PPIDE_CS0_LINE 0x08 // Inverter between 8255 and IDE interface
+#define PPIDE_CS1_LINE 0x10 // Inverter between 8255 and IDE interface
+#define PPIDE_WR_LINE 0x20 // Inverter between 8255 and IDE interface
+#define PPIDE_WR_BIT 5 // (1 << PPIDE_WR_BIT) = PPIDE_WR_LINE
+#define PPIDE_RD_LINE 0x40 // Inverter between 8255 and IDE interface
+#define PPIDE_RD_BIT 6 // (1 << PPIDE_RD_BIT) = PPIDE_RD_LINE
+#define PPIDE_RST_LINE 0x80 // Inverter between 8255 and IDE interface
+
+/* 8255 configuration */
+#define PPIDE_PPI_BUS_READ 0x92
+#define PPIDE_PPI_BUS_WRITE 0x80
+
+/* IDE register addresses */
+#define ide_reg_data (PPIDE_CS0_LINE)
+#define ide_reg_error (PPIDE_CS0_LINE | PPIDE_A0_LINE)
+#define ide_reg_features (PPIDE_CS0_LINE | PPIDE_A0_LINE)
+#define ide_reg_sec_count (PPIDE_CS0_LINE | PPIDE_A1_LINE)
+#define ide_reg_lba_0 (PPIDE_CS0_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE)
+#define ide_reg_lba_1 (PPIDE_CS0_LINE | PPIDE_A2_LINE)
+#define ide_reg_lba_2 (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A0_LINE)
+#define ide_reg_lba_3 (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE)
+#define ide_reg_devhead (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE)
+#define ide_reg_command (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE)
+#define ide_reg_status (PPIDE_CS0_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE)
+#define ide_reg_altstatus (PPIDE_CS1_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE)
+#define ide_reg_control (PPIDE_CS1_LINE | PPIDE_A2_LINE | PPIDE_A1_LINE | PPIDE_A0_LINE)
+
+#endif /* CONFIG_PPIDE */
+++ /dev/null
-/* 2015-04-24 WRS: devide glue functions for PPIDE */
-
-#include <kernel.h>
-#include <kdata.h>
-#include <printf.h>
-#include <stdbool.h>
-#include <timer.h>
-#include <devide.h>
-#include <blkdev.h>
-
-__sfr __at (PPIDE_BASE + 0x00) ppi_port_a; /* IDE bus LSB */
-__sfr __at (PPIDE_BASE + 0x01) ppi_port_b; /* IDE bus MSB */
-__sfr __at (PPIDE_BASE + 0x02) ppi_port_c; /* IDE bus control signals */
-__sfr __at (PPIDE_BASE + 0x03) ppi_control; /* 8255 command register */
-
-void ppide_init(void)
-{
- ppi_control = PPIDE_PPI_BUS_READ;
- ppi_port_c = ide_reg_status;
-}
-
-uint8_t devide_readb(uint8_t regaddr)
-{
- uint8_t r;
-
- /* note: ppi_control should contain PPIDE_PPI_BUS_READ already */
- ppi_port_c = regaddr;
- ppi_control = 1 | (PPIDE_RD_BIT << 1); /* begin /RD pulse */
- r = ppi_port_a;
- ppi_control = 0 | (PPIDE_RD_BIT << 1); /* end /RD pulse */
- return r;
-}
-
-void devide_writeb(uint8_t regaddr, uint8_t value)
-{
- ppi_control = PPIDE_PPI_BUS_WRITE;
- ppi_port_c = regaddr;
- ppi_port_a = value;
- ppi_port_b = 0;
- ppi_control = 1 | (PPIDE_WR_BIT << 1); /* begin /WR pulse */
- ppi_control = 0 | (PPIDE_WR_BIT << 1); /* end /WR pulse */
- ppi_control = PPIDE_PPI_BUS_READ;
-}
-
-/****************************************************************************/
-/* The innermost part of the transfer routines has to live in common memory */
-/* since it must be able to bank switch to the user memory bank. */
-/****************************************************************************/
-COMMON_MEMORY
-
-void devide_read_data(void) __naked
-{
- __asm
- ld a, #ide_reg_data
- ld c, #PPIDE_BASE+2 ; select control lines
- out (c), a ; select IDE data register
- ld hl, (_blk_op+BLKPARAM_ADDR_OFFSET) ; blkparam.addr
- ld d, #ide_reg_data ; register address
- ld e, #ide_reg_data | PPIDE_RD_LINE ; register address with /RD asserted
- ld b, #0 ; setup count
- ld a, (_blk_op+BLKPARAM_IS_USER_OFFSET) ; blkparam.is_user
- or a ; test is_user
- push af ; save flags
- ld a, #PPIDE_BASE+0 ; I will be needing this later
- call nz, map_process_always ; map user memory first if required
-goread: ; now we do the transfer
- out (c), e ; assert /RD
- ld c, a ; PPIDE_BASE
- ini ; read byte from LSB
- inc c ; up to MSB
- ini ; read byte from MSB
- inc c ; control lines
- out (c), d ; de-assert /RD
- inc b ; (delay) counteract second ini instruction
- jr nz, goread ; (delay) next word
- ; read completed
- pop af ; recover is_user test result
- ret z ; done if kernel memory transfer
- jp map_kernel ; else map kernel then return
- __endasm;
-}
-
-void devide_write_data(void) __naked
-{
- __asm
- ld c, #PPIDE_BASE+2 ; select control lines
- ld a, #ide_reg_data
- out (c), a ; select data register
- ld a, #PPIDE_PPI_BUS_WRITE
- inc c ; up to 8255A command register
- out (c), a ; 8255A ports A, B to output mode
- dec c ; back down to the control lines
- ld hl, (_blk_op+BLKPARAM_ADDR_OFFSET) ; blkparam.addr
- ld d, #ide_reg_data ; register address
- ld e, #ide_reg_data | PPIDE_WR_LINE ; register address with /WR asserted
- ld b, #0 ; setup count
- ld a, (_blk_op+BLKPARAM_IS_USER_OFFSET) ; blkparam.is_user
- or a ; test is_user
- push af ; save flags
- ld a, #PPIDE_BASE+0 ; I will be needing this later
- call nz, map_process_always ; map user memory first if required
-gowrite: ; now we do the transfer
- out (c), d ; de-assert /WR
- ld c, a ; PPIDE_BASE
- outi ; write byte to LSB
- inc c ; up to MSB
- outi ; write byte to MSB
- inc c ; up to control lines
- out (c), e ; assert /WR
- inc b ; (delay) offset to counteract second outi instruction
- jr nz, gowrite ; (delay) next word
- ; write completed
- out (c), d ; de-assert /WR
- ld a, #PPIDE_PPI_BUS_READ
- inc c ; up to 8255A command register
- out (c), a ; 8255A ports A, B to read mode
- pop af ; recover is_user test result
- ret z ; done if kernel memory transfer
- jp map_kernel ; else map kernel then return
- __endasm;
-}
public / FUZIX.git / commitdiff