0, NOOP_1, 0237, "lahf",
0, NOOP_1, 0244, "movsb",
0, NOOP_1, 0245, "movs",
+0, NOOP_1, 0245, "movsw",
0, NOOP_1, 0246, "cmpsb",
0, NOOP_1, 0247, "cmps",
+0, NOOP_1, 0247, "cmpsw",
0, NOOP_1, 0252, "stosb",
0, NOOP_1, 0253, "stos",
+0, NOOP_1, 0253, "stosw",
0, NOOP_1, 0254, "lodsb",
0, NOOP_1, 0255, "lods",
+0, NOOP_1, 0255, "lodsw",
0, NOOP_1, 0256, "scasb",
0, NOOP_1, 0257, "scas",
+0, NOOP_1, 0257, "scasw",
0, NOOP_1, 0316, "into",
0, NOOP_1, 0317, "iret",
0, NOOP_1, 0327, "xlat",
0, PUSHOP, 1, "pop",
0, IOOP, 0344, "inb",
0, IOOP, 0345, "in",
+0, IOOP, 0345, "inw",
0, IOOP, 0346, "outb",
0, IOOP, 0347, "out",
+0, IOOP, 0347, "outw",
0, ADDOP, 000, "addb",
0, ADDOP, 001, "add",
0, ADDOP, 010, "orb",
0, NOTOP, 040, "mulb",
0, NOTOP, 041, "mul",
0, NOTOP, 050, "imulb",
-0, NOTOP, 051, "imul",
+0, IMUL, 051, "imul", /* for 80286 */
0, NOTOP, 060, "divb",
0, NOTOP, 061, "div",
0, NOTOP, 070, "idivb",
0, TEST, 1, "test",
0, MOV, 0, "movb",
0, MOV, 1, "mov",
+0, MOV, 1, "movw",
/* Intel 8087 coprocessor keywords */
0, FNOOP, FESC+1+(0xFC<<8), "frndint",
0, FNOOP, FESC+1+(0xFD<<8), "fscale",
0, FNOOP, FESC+1+(0xFA<<8), "fsqrt",
-/* 0, FNOOP, FESC+7+(0xE0<<8), "fstswax", /* 80287 */
+0, FNOOP, FESC+7+(0xE0<<8), "fstswax", /* 80287 */
0, FNOOP, FESC+1+(0xE4<<8), "ftst",
0, FNOOP, FESC+1+(0xE5<<8), "fxam",
0, FNOOP, FESC+1+(0xF4<<8), "fxtract",
0, FST_ST2, FESC+2+(0xE0<<8), "fsubp",
0, FST_ST2, FESC+0+(0xE8<<8), "fsubr",
0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp",
+
+/* 80286 keywords */
+0, NOOP_1, 0140, "pusha",
+0, NOOP_1, 0141, "popa",
+0, NOOP_1, 0156, "outsb",
+0, NOOP_1, 0157, "outs",
+0, NOOP_1, 0157, "outsw",
+0, NOOP_1, 0246, "insb",
+0, NOOP_1, 0247, "ins",
+0, NOOP_1, 0247, "insw",
+
+0, ENTER, 0310, "enter",
+0, NOOP_1, 0311, "leave",
+0, LEAOP, 0142, "bound",
+
+0, NOOP_2, 017+06<<8, "clts",
+
+0, EXTOP, 0002, "lar",
+0, EXTOP, 0003, "lsl",
+
+0, EXTOP1, 0021, "lgdt",
+0, EXTOP1, 0001, "sgdt",
+0, EXTOP1, 0031, "lidt",
+0, EXTOP1, 0011, "sidt",
+0, EXTOP1, 0020, "lldt",
+0, EXTOP1, 0000, "sldt",
+0, EXTOP1, 0030, "ltr",
+0, EXTOP1, 0010, "str",
+0, EXTOP1, 0061, "lmsw",
+0, EXTOP1, 0041, "smsw",
+0, EXTOP1, 0050, "verw",
+0, EXTOP1, 0040, "verr",
ea_1(param) {
- if ((mrg_1 & 070) || (param & ~070))
+ if ((mrg_1 & 070) || (param & ~070)) {
serror("bad operand");
+ }
emit1(mrg_1 | param);
switch(mrg_1 >> 6) {
case 0:
} else if (mrg_1 >= 0300) {
emit1(0120 | opc<<3 | (mrg_1&7));
} else if (opc == 0) {
- emit1(0377); ea_1(6<<3);
+ if (mrg_1 & 040) { /* 070 ??? */
+ if (small(exp_1.typ == S_ABS && fitb(exp_1.val),1)) {
+ emit1(0152);
+ emit1((int) exp_1.val);
+ } else {
+ emit1(0150);
+ RELOMOVE(relonami, rel_1);
+#ifdef RELOCATION
+ newrelo(exp_1.typ, RELO2);
+ emit2((int) exp_1.val);
+#endif
+ }
+ } else {
+ emit1(0377); ea_1(6<<3);
+ }
} else {
emit1(0217); ea_1(0<<3);
}
regsize(opc);
if (cmrg == 0301) {
emit1(0322 | (opc&1)); ea_1(opc&070);
- } else if ((cmrg & 040) && exp_2.val == 1) {
- emit1(0320 | (opc&1)); ea_1(opc&070);
+ } else if (cmrg & 040) {
+ if (exp_2.val == 1) {
+ emit1(0320 | (opc&1)); ea_1(opc&070);
+ } else {
+ fit(fitb(exp_2.val));
+ emit1(0300|(opc&1)); ea_1(opc&070);
+ emit1((int)exp_2.val);
+ }
} else
badsyntax();
}
emit1(0210 | opc); ea_1((mrg_2&7)<<3);
} else if (mrg_1 >= 0300) {
emit1(0212 | opc); ea_2((mrg_1&7)<<3);
- } else
+ } else {
badsyntax();
+ }
+}
+
+imul(opc)
+ int opc;
+{
+ regsize(opc);
+ if (exp_2.typ != S_ABS || ((mrg_2 & 040) == 0)) {
+ serror("bad operand");
+ } else {
+ if (small(exp_2.typ == S_ABS && fitb(exp_2.val),1)) {
+ emit1(0153);
+ ea_1((mrg_2&7)<<3);
+ emit1((int)exp_2.val);
+ } else {
+ emit1(0151);
+ ea_1((mrg_2&7)<<3);
+ RELOMOVE(relonami, rel_2);
+#ifdef RELOCATION
+ newrelo(exp_2.typ, RELO2);
+ emit2((int) exp_2.val);
+#endif
+ }
+ }
}