fixes to additions

diff --git a/mach/i86/cg/table b/mach/i86/cg/table
index 0c948bc..5227ecf 100644 (file)
--- a/mach/i86/cg/table
+++ b/mach/i86/cg/table
@@ -1132,34 +1132,41 @@ ldl adi sdl $1==$3 && $2==4 | regorconst regorconst |
                        "add $1(bp),%[1]"
                        "adc %($1+2%)(bp),%[2]"            | | |
 #ifdef REGVARS
-lol loc sbi stl $1==$4 && $3==2 | |
+lol loc sbi stl $1==$4 && $3==2 && inreg($1)==2 | |
                        remove(regvar($1))
                        "sub %(regvar($1)%),$2"
                        setcc(regvar($1))                  | | |
-lol loc sli stl $1==$4 && $2==1 && $3==2 | |
+#endif
+lol loc sbi stl $1==$4 && $3==2 | |
+                       remove(indexed)
+                       remove(locals, %[ind]>=$1 && %[ind]<$1+2 )
+                       "sub $1(bp),%[1]"
+                       setcc({LOCAL2, $1, 2})            | | |
+#ifdef REGVARS
+lol loc sli stl $1==$4 && $2==1 && $3==2 && inreg($1)==2 | |
                        remove(regvar($1))
                        "sal %(regvar($1)%),1"
                        setcc(regvar($1))               | | |
-lol loc sli stl $1==$4 && $2==2 && $3==2 | |
+lol loc sli stl $1==$4 && $2==2 && $3==2 && inreg($1)==2 | |
                        remove(regvar($1))
                        "sal %(regvar($1)%),1"
                        "sal %(regvar($1)%),1"
                        setcc(regvar($1))               | | |
-lol loc sli stl $1==$4 && $3==2 | |
+lol loc sli stl $1==$4 && $3==2 && inreg($1)==2 | |
                        remove(regvar($1))
                        allocate(CXREG = {ANYCON, $2})
                        "sar %(regvar($1)%),cl"
                        setcc(regvar($1))               | | |
-lol loc sri stl $1==$4 && $2==1 && $3==2 | |
+lol loc sri stl $1==$4 && $2==1 && $3==2 && inreg($1)==2 | |
                        remove(regvar($1))
                        "sar %(regvar($1)%),1"
                        setcc(regvar($1))               | | |
-lol loc sri stl $1==$4 && $2==2 && $3==2 | |
+lol loc sri stl $1==$4 && $2==2 && $3==2 && inreg($1)==2 | |
                        remove(regvar($1))
                        "sar %(regvar($1)%),1"
                        "sar %(regvar($1)%),1"
                        setcc(regvar($1))               | | |
-lol loc sri stl $1==$4 && $3==2 | |
+lol loc sri stl $1==$4 && $3==2 && inreg($1)==2 | |
                        remove(regvar($1))
                        allocate(CXREG = {ANYCON, $2})
                        "sar %(regvar($1)%),cl"