Bug fixed for pattern 'sti $1 > 4' (ADDREG -> ADDSCR)

Bug was present since version 1.1

diff --git a/mach/m68k2/cg/table b/mach/m68k2/cg/table
index 2a327bf..ef2ee0a 100644 (file)
--- a/mach/m68k2/cg/table
+++ b/mach/m68k2/cg/table
@@ -461,7 +461,7 @@ sti $1 == 2 | ADDREG ANY |  remove(MEM_ALL)
                                move(%[2],{IADDREG,%[1]}) | | |
 sti $1 == 4  | ADDREG ANY4 |   remove(MEM_ALL)
                                move(%[2],{IADDREG4,%[1]}) | | |
-sti $1 > 4 | ADDREG |          remove(ALL)
+sti $1 > 4 | ADDSCR |          remove(ALL)
                                allocate(DATAREG4={IMMEDIATE4,$1/2-1})
                                "1:"
                                "move.w (sp)+,(%[1])+"