--- /dev/null
+#define DUK
+#define RCSID0 "$Header$"
+
+/*
+ * Intel 8080 options
+ */
+#define LISTING
+#define RELOCATION
+#define NOLD
--- /dev/null
+#define RCSID1 "$Header$"
+
+/*
+ * Intel 8080 register names
+ */
+
+#define B 0
+#define C 1
+#define D 2
+#define E 3
+#define H 4
+#define L 5
+#define M 6
+#define A 7
+#define SP 6
+#define PSW 6
+
+#define low3(z) ((z) & 07)
+#define fit3(z) (low3(z) == (z))
--- /dev/null
+#define RCSID2 "$Header$"
+
+/*
+ * Intel 8080 tokens
+ */
+%token <y_word> REG
+%token <y_word> NOOPOP
+%token <y_word> DSTOP
+%token <y_word> SRCOP
+%token <y_word> D8OP
+%token <y_word> D16OP
+%token <y_word> R16OP
+%token <y_word> MOV
+%token <y_word> MVI
+%token <y_word> LXI
+%token <y_word> RST
+%token <y_word> STLDAX
+
+%type <y_word> r16 r8
--- /dev/null
+#define RCSID3 "$Header$"
+
+/*
+ * Intel 8080 keywords
+ */
+0, REG, B, "b",
+0, REG, C, "c",
+0, REG, D, "d",
+0, REG, E, "e",
+0, REG, H, "h",
+0, REG, L, "l",
+0, REG, M, "m",
+0, REG, A, "a",
+0, REG, SP, "sp",
+0, REG, PSW, "psw",
+0, D16OP, 0315, "call",
+0, D16OP, 0334, "cc",
+0, D16OP, 0324, "cnc",
+0, D16OP, 0314, "cz",
+0, D16OP, 0304, "cnz",
+0, D16OP, 0364, "cp",
+0, D16OP, 0374, "cm",
+0, D16OP, 0354, "cpe",
+0, D16OP, 0344, "cpo",
+0, NOOPOP, 0311, "ret",
+0, NOOPOP, 0330, "rc",
+0, NOOPOP, 0320, "rnc",
+0, NOOPOP, 0310, "rz",
+0, NOOPOP, 0300, "rnz",
+0, NOOPOP, 0360, "rp",
+0, NOOPOP, 0370, "rm",
+0, NOOPOP, 0350, "rpe",
+0, NOOPOP, 0340, "rpo",
+0, RST, 0307, "rst",
+0, D8OP, 0333, "in",
+0, D8OP, 0323, "out",
+0, LXI, 0001, "lxi",
+0, R16OP, 0305, "push",
+0, R16OP, 0301, "pop",
+0, D16OP, 0062, "sta",
+0, D16OP, 0072, "lda",
+0, NOOPOP, 0353, "xchg",
+0, NOOPOP, 0343, "xthl",
+0, NOOPOP, 0371, "sphl",
+0, NOOPOP, 0351, "pchl",
+0, R16OP, 0011, "dad",
+0, STLDAX, 0002, "stax",
+0, STLDAX, 0012, "ldax",
+0, R16OP, 0003, "inx",
+0, MOV, 0100, "mov",
+0, NOOPOP, 0166, "hlt",
+0, MVI, 0006, "mvi",
+0, DSTOP, 0004, "inr",
+0, DSTOP, 0005, "dcr",
+0, SRCOP, 0200, "add",
+0, SRCOP, 0210, "adc",
+0, SRCOP, 0220, "sub",
+0, SRCOP, 0230, "sbb",
+0, SRCOP, 0240, "ana",
+0, SRCOP, 0250, "xra",
+0, SRCOP, 0260, "ora",
+0, SRCOP, 0270, "cmp",
+0, D8OP, 0306, "adi",
+0, D8OP, 0316, "aci",
+0, D8OP, 0326, "sui",
+0, D8OP, 0336, "sbi",
+0, D8OP, 0346, "ani",
+0, D8OP, 0356, "xri",
+0, D8OP, 0366, "ori",
+0, D8OP, 0376, "cpi",
+0, NOOPOP, 0007, "rlc",
+0, NOOPOP, 0017, "rrc",
+0, NOOPOP, 0027, "ral",
+0, NOOPOP, 0037, "rar",
+0, D16OP, 0303, "jmp",
+0, D16OP, 0332, "jc",
+0, D16OP, 0322, "jnc",
+0, D16OP, 0312, "jz",
+0, D16OP, 0302, "jnz",
+0, D16OP, 0362, "jp",
+0, D16OP, 0372, "jm",
+0, D16OP, 0352, "jpe",
+0, D16OP, 0342, "jpo",
+0, R16OP, 0013, "dcx",
+0, NOOPOP, 0057, "cma",
+0, NOOPOP, 0067, "stc",
+0, NOOPOP, 0077, "cmc",
+0, NOOPOP, 0047, "daa",
+0, D16OP, 0042, "shld",
+0, D16OP, 0052, "lhld",
+0, NOOPOP, 0373, "ei",
+0, NOOPOP, 0363, "di",
+0, NOOPOP, 0000, "nop",
+0, NOOPOP, 0040, "rim", /* 8085 */
+0, NOOPOP, 0060, "sim", /* 8085 */
--- /dev/null
+#define RCSID4 "$Header$"
+
+/*
+ * (c) copyright 1983 by the Vrije Universiteit, Amsterdam, The Netherlands.
+ *
+ * This product is part of the Amsterdam Compiler Kit.
+ *
+ * Permission to use, sell, duplicate or disclose this software must be
+ * obtained in writing. Requests for such permissions may be sent to
+ *
+ * Dr. Andrew S. Tanenbaum
+ * Wiskundig Seminarium
+ * Vrije Universiteit
+ * Postbox 7161
+ * 1007 MC Amsterdam
+ * The Netherlands
+ *
+ */
+
+/*
+ * Intel 8080 parsing rules
+ */
+operation
+ : NOOPOP
+ { emit1($1);}
+ |
+ D8OP expr
+ { emit1($1);
+#ifdef RELOCATION
+ newrelo($2.typ, RELO1);
+#endif
+ emit1($2.val);
+ }
+ |
+ D16OP expr
+ { emit1($1);
+#ifdef RELOCATION
+ newrelo($2.typ, RELO2);
+#endif
+ emit2($2.val);
+ }
+ |
+ R16OP r16
+ { emit1($1 | ($2 << 3));}
+ |
+ MOV r8 ',' r8
+ { if ($2 == M && $4 == M)
+ serror("register error");
+ emit1($1 | ($2 << 3) | $4);
+ }
+ |
+ MVI r8 ',' expr
+ { emit1($1 | ($2 << 3));
+#ifdef RELOCATION
+ newrelo($4.typ, RELO1);
+#endif
+ emit1($4.val);
+ }
+ |
+ LXI r16 ',' expr
+ { emit1($1 | ($2 << 3));
+#ifdef RELOCATION
+ newrelo($4.typ, RELO2);
+#endif
+ emit2($4.val);
+ }
+ |
+ SRCOP r8
+ { emit1($1 | $2);}
+ |
+ DSTOP r8
+ { emit1($1 | ($2 << 3));}
+ |
+ RST absexp
+ { fit(fit3($2));
+ emit1($1 | (low3($2) << 3));
+ }
+ |
+ STLDAX r16
+ {
+ if ($2 != B && $2 != D)
+ serror("register error");
+ emit1($1 | (($2 & 02) << 3));
+ }
+ ;
+r16 : REG
+ { if ($1 & ~06)
+ serror("register error");
+ $$ = $1 & 06;
+ }
+ ;
+r8 : REG
+ { if (($1 & ~07) != 0)
+ serror("register error");
+ $$ = $1 & 07;
+ }
+ ;
public / ack.git / commitdiff