je label cost(1,4).
jg label cost(1,4).
jge label cost(1,4).
+jgt label cost(1,4).
jl label cost(1,4).
jle label cost(1,4).
jne label cost(1,4).
proccall "call" label+rm cost(1,8).
jxx "syntax error" label cost(1,4).
setxx "syntax error" REG:rw cost(2,4).
+setle REG:rw cost(2,4).
+setgt REG:rw cost(2,4).
lea anyreg:rw, halfindir:ro.
lea LOCAL:rw, halfindir:ro. /* only for register variables, UNSAFE!!! */
leave cost(1,4).
xorw "o16 xor" anyreg:rw:cc, rmorconst2:ro.
killreg "! kill" anyreg:wo cost(0,0).
+killcc "! kill cc" kills:cc cost(0,0).
/*****************************************************************/
gen test %1
setxx* %a yields %a
-pat tlt call txx("setl")
-pat tle call txx("setle")
+pat tlt call txx("sets")
pat teq call txx("sete")
pat tne call txx("setne")
-pat tge call txx("setge")
-pat tgt call txx("setg")
+pat tge call txx("setns")
+
+/* Explicit test for TLE and TGT. We must make sure that the OC
+ flag is cleared.
+*/
+pat tle
+with rm
+uses REG = {ANYCON,0}
+ gen
+ killcc.
+ test %1
+ setle %a
+ yields %a
+
+pat tgt
+with rm
+uses REG = {ANYCON,0}
+ gen
+ killcc.
+ test %1
+ setgt %a
+ yields %a
proc txxior
with rm REG
gen test %1
jxx* {label,$1}
-pat zlt call zxx("jl")
-pat zle call zxx("jle")
-pat zge call zxx("jge")
-pat zgt call zxx("jg")
+pat zlt call zxx("js")
+pat zge call zxx("jns")
+
+/* Explicit test for ZLE and ZGT. We must make sure that the OC
+ flag is cleared.
+*/
+pat zle
+with rm STACK
+ gen
+ killcc.
+ test %1
+ jle {label,$1}
+
+pat zgt
+with rm STACK
+ gen
+ killcc.
+ test %1
+ jgt {label, $1}
pat zne
with rm+rm1 STACK
xorb rm1:rw:cc, regorconst12:ro.
xorb anyreg:rw:cc, rm1:ro.
killreg "! kill" anyreg:wo cost(0,0).
+killcc "! kill cc" kills:cc cost(0,0).
data ".sect .data".
word ".data2" const:ro.
inc %a
1: yields %a
-pat tlt call txx("jge")
-pat tle call txx("jg")
+pat tlt call txx("jns")
pat teq call txx("jne")
pat tne call txx("je")
-pat tge call txx("jl")
-pat tgt call txx("jle")
+pat tge call txx("js")
+
+/* For the next two patterns there is no I8086 test instruction (one that
+ ignores the OF flag. Therefore, condition codes are killed and the test
+ is done again.
+*/
+pat tgt
+with rm
+uses REG = {ANYCON, 0}
+ gen killcc.
+ test %1
+ jle {label, 1f}
+ inc %a
+ 1: yields %a
+
+pat tle
+with rm
+uses REG = {ANYCON, 0}
+ gen killcc.
+ test %1
+ jg {label, 1f}
+ inc %a
+ 1: yields %a
proc txxior
with rm REG
or %2,{ANYCON,1}
1: yields %2
-pat tlt ior $2==2 call txxior("jge")
-pat tle ior $2==2 call txxior("jg")
+pat tlt ior $2==2 call txxior("jns")
+pat tge ior $2==2 call txxior("js")
pat teq ior $2==2 call txxior("jne")
pat tne ior $2==2 call txxior("je")
-pat tge ior $2==2 call txxior("jl")
-pat tgt ior $2==2 call txxior("jle")
+
+/* For the next two patterns there is no I8086 test instruction (one that
+ ignores the OF flag. Therefore, condition codes are killed and the test
+ is done again.
+*/
+pat tle ior $2==2
+with rm REG
+ gen killcc.
+ test %1
+ jg {label,1f}
+ or %2,{ANYCON,1}
+ 1: yields %2
+
+pat tgt ior $2==2
+with rm REG
+ gen killcc.
+ test %1
+ jle {label,1f}
+ or %2,{ANYCON,1}
+ 1: yields %2
proc cmixxior
with regorconst rm REG
gen test %1
jxx* {label,$1}
-pat zlt call zxx("jl")
-pat zle call zxx("jle")
-pat zge call zxx("jge")
-pat zgt call zxx("jg")
+pat zlt call zxx("js")
+pat zge call zxx("jns")
+
+/* For the next two patterns there is no I8086 test instruction (one that
+ ignores the OF flag. Therefore, condition codes are killed and the test
+ is done again.
+*/
+pat zle
+with rm STACK
+ gen killcc.
+ test %1
+ jle {label,$1}
+
+pat zgt
+with rm STACK
+ gen killcc.
+ test %1
+ jg {label,$1}
pat zne
with rm+rm1 STACK