echo '#ifndef lint' > Version.c
echo 'char Version[] = "ACK Pascal compiler Version XXX";' | \
sed "s/XXX/`RC -i`/" >> Version.c
- echo '#endif lint' >> Version.c
+ echo '#endif' >> Version.c
}
va_end(ap);
}
-#endif DEBUG
+#endif /* DEBUG */
/*VARARGS*/
error(va_alist)
case VDEBUG:
remark = "(debug)";
break;
-#endif DEBUG
+#endif /* DEBUG */
}
/* the place */
case FATAL:
#ifdef DEBUG
case VDEBUG:
-#endif DEBUG
+#endif /* DEBUG */
ln = LineNumber;
break;
}
}
#ifdef DEBUG
}
-#endif DEBUG
+#endif /* DEBUG */
if( FileName ) fprint(ERROUT, "\"%s\", line %u: ", FileName, ln);
LexScan();
return 0; /* running the optimizer is not very useful */
}
-#endif DEBUG
+#endif /* DEBUG */
C_init(word_size, pointer_size);
if( !C_open(dst) )
fatal("couldn't open output file");
C_close();
#ifdef DEBUG
if( options['I'] ) Info();
-#endif DEBUG
+#endif /* DEBUG */
return !err_occurred;
}
}
}
break;
-#endif NOCROSS
+#endif /* NOCROSS */
}
}
}
#define long_size (SZ_LONG)
#define pointer_size (SZ_POINTER)
#define real_size (SZ_REAL)
-#else NOCROSS
+#else /* NOCROSS */
extern int
word_align,
int_align,
long_size,
pointer_size,
real_size; /* All from type.c */
-#endif NOCROSS
+#endif /* NOCROSS */
extern arith
align();
long_size = SZ_LONG,
pointer_size = SZ_POINTER,
real_size = SZ_REAL;
-#endif NOCROSS
+#endif /* NOCROSS */
extern arith max_int;
#else
$$.typ = $1.typ; /* Even if $1.typ is relocatable, it should be */
/* absolute by the final pass. */
-#endif RELOCATION
+#endif /* RELOCATION */
}
;
operation
}
fputs("leave\nret\n", codefile);
}
-#endif REGVARS
+#endif /* REGVARS */
mes(type) word type ; {
int argt, a1, a2 ;
}
else fputs("jmp .cret\n", codefile);
}
-#endif REGVARS
+#endif /* REGVARS */
mes(type) word type ; {
int argt ;
#ifdef ASLD
#define T_EMIT2(a,b,c,d) t_emit2(a,b,c,(valu_t)0)
#define T_EMIT4(a,b,c,d) t_emit4(a,b,c,(valu_t)0)
-#else ALSD
+#else /* ALSD */
#define T_EMIT2(a,b,c,d) t_emit2(a,b,c,(valu_t)d)
#define T_EMIT4(a,b,c,d) t_emit4(a,b,c,(valu_t)d)
-#endif ASLD
+#endif /* ASLD */
#else
#define T_EMIT2(a,b,c,d) t_emit2(a)
#define T_EMIT4(a,b,c,d) t_emit4(a)
t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
-#else TBL68020
+#else /* TBL68020 */
/* Part (iii) */
absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
#define t_regAregXcon regAregXcon
#define t_regAcon regAcon
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE!=2
#define DLOCAL LOCAL
alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG .
-#else TBL68020
+#else /* TBL68020 */
data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
offsetted4 + OFF_off4 + OFF_indoff4 +
alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG. /* all four above together */
-#endif TBL68020
+#endif /* TBL68020 */
/* This is a common part */
#if WORD_SIZE==2
/* Not any4, since any is used in 'with' and not in 'kills' */
t_regAcon + t_regAregXcon ) .
use_index = index_off4 + index_off2 + index_off1 .
-#else TBL68020
+#else /* TBL68020 */
reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
memind4 = reg_memind4 +
use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
-#endif TBL68020
+#endif /* TBL68020 */
/* A common part */
posextern = absolute + all_indir .
#endif
test_set1 = datalt1 .
-#else TBL68020
+#else /* TBL68020 */
imm_cmp4 = any4 - immediate4 - A_REG .
imm_cmp2 = any2 - consts .
#endif
test_set1 = data1 - consts .
-#endif TBL68020
+#endif /* TBL68020 */
test_set = test_set4 + test_set2 + test_set1 .
#ifndef TBL68020
t_address = address + t_regAregXcon + t_regAcon .
-#else TBL68020
+#else /* TBL68020 */
#define t_address address
-#endif TBL68020
+#endif /* TBL68020 */
#if TBL68881
freg = FD_REG + FS_REG .
divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
#endif
-#else TBL68020
+#else /* TBL68020 */
pea address+control4 cost(2,4).
-#endif TBL68020
+#endif /* TBL68020 */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Extra pseudo instruction; it just kills a D_REG;
from t_regAcon to A_REG+areg
gen move_l %1.reg, %2
add_l {const4, %1.bd}, %2
-#endif TBL68020
+#endif /* TBL68020 */
from address - ext_addr to A_REG+areg
gen lea %1, %2
from t_regAcon to STACK
gen move_l %1.reg, {pre_dec4, sp}
add_l {const4, %1.bd}, {indirect4, sp}
-#endif TBL68020
+#endif /* TBL68020 */
from A_REG to STACK
gen pea {indirect4, %1}
#ifdef TBL68020
from regX to STACK
gen pea %1
-#endif TBL68020
+#endif /* TBL68020 */
/* This last stackingrule is never used: whenever regX is put on
* the fakestack, some em-instuctions are left that remove it
* immediately. However cgg complained about not having a
uses reusing %1, AA_REG=%1.reg
gen add_l {const4, %1.bd}, %a
yields %a
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
from regAregXcon %bd==0 && %sc==1
with data_int
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
gen mulu_i %1, {LOCAL, $1}
-#endif TBL68020
+#endif /* TBL68020 */
proc lolxxxstl example lol adi stl
with conreg_int-bconst
with exact ext_addr yields {absolute_int, %1.bd+$1}
#ifndef TBL68020
with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
#ifdef FANCY_MODES
#ifndef TBL68020
with regAcon yields {offsetted1, %1.reg, %1.bd}
with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted1, %1.reg, %1.bd}
with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#ifdef FANCY_MODES
#ifndef TBL68020
with regAcon yields {offsetted2, %1.reg, %1.bd}
with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted2, %1.reg, %1.bd}
with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==2
#ifndef TBL68020
with regAcon yields {offsetted4, %1.reg, %1.bd}
with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted4, %1.reg, %1.bd}
with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==4
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
#endif
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon store_int
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
kills allexceptcon
gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==1
with A_REG any1
with regAregXcon any1
kills allexceptcon
gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon any1
kills allexceptcon
gen move %2, {offsetted1, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==2
with A_REG any2
with regAregXcon any2
kills allexceptcon
gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon any2
kills allexceptcon
gen move %2, {offsetted2, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==4
with A_REG store4-sconsts4
with regAregXcon store4-sconsts4
kills allexceptcon
gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon store4
kills allexceptcon
gen move %2, {offsetted4, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat sti $1==6
#ifdef TBL68020
with data4 DD_REG4
gen muls_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".mli"}
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen divs_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat rmi $1==2
killreg %2
/* !!!! contents of %2 have changed: make this known to cg */
yields %a
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
yields dl2
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat ngi $1==2
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen mulu_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".mlu"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat dvu $1==2
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen divu_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvu"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat rmu $1==2
killreg %2
/* !!!! contents of %2 have changed: make this known to cg */
yields %a
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvu"}
yields dl2
-#endif TBL68020
+#endif /* TBL68020 */
pat slu leaving sli $1
with exact absolute4 ext_regX
yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
/* I WOULD ALSO LIKE THIS:
* pat ads
gen add_l %1, %1 yields %1
#endif
-#endif TBL68020
+#endif /* TBL68020 */
/************************************************
pat lae aar $2==4 && nicesize(rom($1,3))
with D_REG yields {regX, rom($1,3), %1}
leaving ads 4 adp rom($1,3)*(0-rom($1,1))
-#else TBL68020
+#else /* TBL68020 */
pat lae aar $2==4 && rom($1,3)==2
with DD_REG
gen asl_l {small_const, 1}, %1
gen asl_l {small_const, 3}, %1
yields %1
leaving ads 4 adp (0 - rom($1,1))<<3
-#endif TBL68020
+#endif /* TBL68020 */
#endif /* ARR_OPT */
#endif /* WORD_SIZE!=2 */
pea {absolute4, 1} /* push constant 1 == ERANGE */
jsr {absolute4, ".trp"}
1: yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".rck"}
-#endif TBL68020
+#endif /* TBL68020 */
#endif /* WORD_SIZE==4 || TBL68020 */
pat rtt leaving ret 0
#else
#ifdef TBL68020
extb_l {LOCAL,$4}
-#else TBL68020
+#else /* TBL68020 */
ext_w {LOCAL,$4}
ext_l {LOCAL,$4}
-#endif TBL68020
+#endif /* TBL68020 */
#endif
pat loc loc cii $1==2 && $2==4
#else
if (exp_2.typ != S_ABS)
sm = 0;
-#endif ASLD
+#endif /* ASLD */
sm = small(sm, 2);
if (sm)
mrg_2 = 070;
t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
-#else TBL68020
+#else /* TBL68020 */
/* Part (iii) */
absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
#define t_regAregXcon regAregXcon
#define t_regAcon regAcon
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE!=2
#define DLOCAL LOCAL
alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG .
-#else TBL68020
+#else /* TBL68020 */
data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
offsetted4 + OFF_off4 + OFF_indoff4 +
alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG. /* all four above together */
-#endif TBL68020
+#endif /* TBL68020 */
/* This is a common part */
#if WORD_SIZE==2
/* Not any4, since any is used in 'with' and not in 'kills' */
t_regAcon + t_regAregXcon ) .
use_index = index_off4 + index_off2 + index_off1 .
-#else TBL68020
+#else /* TBL68020 */
reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
memind4 = reg_memind4 +
use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
-#endif TBL68020
+#endif /* TBL68020 */
/* A common part */
posextern = absolute + all_indir .
#endif
test_set1 = datalt1 .
-#else TBL68020
+#else /* TBL68020 */
imm_cmp4 = any4 - immediate4 - A_REG .
imm_cmp2 = any2 - consts .
#endif
test_set1 = data1 - consts .
-#endif TBL68020
+#endif /* TBL68020 */
test_set = test_set4 + test_set2 + test_set1 .
#ifndef TBL68020
t_address = address + t_regAregXcon + t_regAcon .
-#else TBL68020
+#else /* TBL68020 */
#define t_address address
-#endif TBL68020
+#endif /* TBL68020 */
#if TBL68881
freg = FD_REG + FS_REG .
divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
#endif
-#else TBL68020
+#else /* TBL68020 */
pea address+control4 cost(2,4).
-#endif TBL68020
+#endif /* TBL68020 */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Extra pseudo instruction; it just kills a D_REG;
from t_regAcon to A_REG+areg
gen move_l %1.reg, %2
add_l {const4, %1.bd}, %2
-#endif TBL68020
+#endif /* TBL68020 */
from address - ext_addr to A_REG+areg
gen lea %1, %2
from t_regAcon to STACK
gen move_l %1.reg, {pre_dec4, sp}
add_l {const4, %1.bd}, {indirect4, sp}
-#endif TBL68020
+#endif /* TBL68020 */
from A_REG to STACK
gen pea {indirect4, %1}
#ifdef TBL68020
from regX to STACK
gen pea %1
-#endif TBL68020
+#endif /* TBL68020 */
/* This last stackingrule is never used: whenever regX is put on
* the fakestack, some em-instuctions are left that remove it
* immediately. However cgg complained about not having a
uses reusing %1, AA_REG=%1.reg
gen add_l {const4, %1.bd}, %a
yields %a
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
from regAregXcon %bd==0 && %sc==1
with data_int
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
gen mulu_i %1, {LOCAL, $1}
-#endif TBL68020
+#endif /* TBL68020 */
proc lolxxxstl example lol adi stl
with conreg_int-bconst
with exact ext_addr yields {absolute_int, %1.bd+$1}
#ifndef TBL68020
with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
#ifdef FANCY_MODES
#ifndef TBL68020
with regAcon yields {offsetted1, %1.reg, %1.bd}
with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted1, %1.reg, %1.bd}
with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#ifdef FANCY_MODES
#ifndef TBL68020
with regAcon yields {offsetted2, %1.reg, %1.bd}
with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted2, %1.reg, %1.bd}
with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==2
#ifndef TBL68020
with regAcon yields {offsetted4, %1.reg, %1.bd}
with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted4, %1.reg, %1.bd}
with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==4
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
#endif
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon store_int
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
kills allexceptcon
gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==1
with A_REG any1
with regAregXcon any1
kills allexceptcon
gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon any1
kills allexceptcon
gen move %2, {offsetted1, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==2
with A_REG any2
with regAregXcon any2
kills allexceptcon
gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon any2
kills allexceptcon
gen move %2, {offsetted2, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==4
with A_REG store4-sconsts4
with regAregXcon store4-sconsts4
kills allexceptcon
gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon store4
kills allexceptcon
gen move %2, {offsetted4, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat sti $1==6
#ifdef TBL68020
with data4 DD_REG4
gen muls_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".mli"}
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen divs_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat rmi $1==2
killreg %2
/* !!!! contents of %2 have changed: make this known to cg */
yields %a
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
yields dl2
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat ngi $1==2
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen mulu_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".mlu"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat dvu $1==2
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen divu_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvu"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat rmu $1==2
killreg %2
/* !!!! contents of %2 have changed: make this known to cg */
yields %a
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvu"}
yields dl2
-#endif TBL68020
+#endif /* TBL68020 */
pat slu leaving sli $1
with exact absolute4 ext_regX
yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
/* I WOULD ALSO LIKE THIS:
* pat ads
gen add_l %1, %1 yields %1
#endif
-#endif TBL68020
+#endif /* TBL68020 */
/************************************************
pat lae aar $2==4 && nicesize(rom($1,3))
with D_REG yields {regX, rom($1,3), %1}
leaving ads 4 adp rom($1,3)*(0-rom($1,1))
-#else TBL68020
+#else /* TBL68020 */
pat lae aar $2==4 && rom($1,3)==2
with DD_REG
gen asl_l {small_const, 1}, %1
gen asl_l {small_const, 3}, %1
yields %1
leaving ads 4 adp (0 - rom($1,1))<<3
-#endif TBL68020
+#endif /* TBL68020 */
#endif /* ARR_OPT */
#endif /* WORD_SIZE!=2 */
pea {absolute4, 1} /* push constant 1 == ERANGE */
jsr {absolute4, ".trp"}
1: yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".rck"}
-#endif TBL68020
+#endif /* TBL68020 */
#endif /* WORD_SIZE==4 || TBL68020 */
pat rtt leaving ret 0
#else
#ifdef TBL68020
extb_l {LOCAL,$4}
-#else TBL68020
+#else /* TBL68020 */
ext_w {LOCAL,$4}
ext_l {LOCAL,$4}
-#endif TBL68020
+#endif /* TBL68020 */
#endif
pat loc loc cii $1==2 && $2==4
t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
-#else TBL68020
+#else /* TBL68020 */
/* Part (iii) */
absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
#define t_regAregXcon regAregXcon
#define t_regAcon regAcon
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE!=2
#define DLOCAL LOCAL
alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG .
-#else TBL68020
+#else /* TBL68020 */
data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
offsetted4 + OFF_off4 + OFF_indoff4 +
alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG. /* all four above together */
-#endif TBL68020
+#endif /* TBL68020 */
/* This is a common part */
#if WORD_SIZE==2
/* Not any4, since any is used in 'with' and not in 'kills' */
t_regAcon + t_regAregXcon ) .
use_index = index_off4 + index_off2 + index_off1 .
-#else TBL68020
+#else /* TBL68020 */
reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
memind4 = reg_memind4 +
use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
-#endif TBL68020
+#endif /* TBL68020 */
/* A common part */
posextern = absolute + all_indir .
#endif
test_set1 = datalt1 .
-#else TBL68020
+#else /* TBL68020 */
imm_cmp4 = any4 - immediate4 - A_REG .
imm_cmp2 = any2 - consts .
#endif
test_set1 = data1 - consts .
-#endif TBL68020
+#endif /* TBL68020 */
test_set = test_set4 + test_set2 + test_set1 .
#ifndef TBL68020
t_address = address + t_regAregXcon + t_regAcon .
-#else TBL68020
+#else /* TBL68020 */
#define t_address address
-#endif TBL68020
+#endif /* TBL68020 */
#if TBL68881
freg = FD_REG + FS_REG .
divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
#endif
-#else TBL68020
+#else /* TBL68020 */
pea address+control4 cost(2,4).
-#endif TBL68020
+#endif /* TBL68020 */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Extra pseudo instruction; it just kills a D_REG;
from t_regAcon to A_REG+areg
gen move_l %1.reg, %2
add_l {const4, %1.bd}, %2
-#endif TBL68020
+#endif /* TBL68020 */
from address - ext_addr to A_REG+areg
gen lea %1, %2
from t_regAcon to STACK
gen move_l %1.reg, {pre_dec4, sp}
add_l {const4, %1.bd}, {indirect4, sp}
-#endif TBL68020
+#endif /* TBL68020 */
from A_REG to STACK
gen pea {indirect4, %1}
#ifdef TBL68020
from regX to STACK
gen pea %1
-#endif TBL68020
+#endif /* TBL68020 */
/* This last stackingrule is never used: whenever regX is put on
* the fakestack, some em-instuctions are left that remove it
* immediately. However cgg complained about not having a
uses reusing %1, AA_REG=%1.reg
gen add_l {const4, %1.bd}, %a
yields %a
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
from regAregXcon %bd==0 && %sc==1
with data_int
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
gen mulu_i %1, {LOCAL, $1}
-#endif TBL68020
+#endif /* TBL68020 */
proc lolxxxstl example lol adi stl
with conreg_int-bconst
with exact ext_addr yields {absolute_int, %1.bd+$1}
#ifndef TBL68020
with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
#ifdef FANCY_MODES
#ifndef TBL68020
with regAcon yields {offsetted1, %1.reg, %1.bd}
with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted1, %1.reg, %1.bd}
with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#ifdef FANCY_MODES
#ifndef TBL68020
with regAcon yields {offsetted2, %1.reg, %1.bd}
with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted2, %1.reg, %1.bd}
with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==2
#ifndef TBL68020
with regAcon yields {offsetted4, %1.reg, %1.bd}
with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted4, %1.reg, %1.bd}
with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==4
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
#endif
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon store_int
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
kills allexceptcon
gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==1
with A_REG any1
with regAregXcon any1
kills allexceptcon
gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon any1
kills allexceptcon
gen move %2, {offsetted1, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==2
with A_REG any2
with regAregXcon any2
kills allexceptcon
gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon any2
kills allexceptcon
gen move %2, {offsetted2, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==4
with A_REG store4-sconsts4
with regAregXcon store4-sconsts4
kills allexceptcon
gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon store4
kills allexceptcon
gen move %2, {offsetted4, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat sti $1==6
#ifdef TBL68020
with data4 DD_REG4
gen muls_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".mli"}
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen divs_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat rmi $1==2
killreg %2
/* !!!! contents of %2 have changed: make this known to cg */
yields %a
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
yields dl2
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat ngi $1==2
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen mulu_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".mlu"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat dvu $1==2
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen divu_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvu"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat rmu $1==2
killreg %2
/* !!!! contents of %2 have changed: make this known to cg */
yields %a
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvu"}
yields dl2
-#endif TBL68020
+#endif /* TBL68020 */
pat slu leaving sli $1
with exact absolute4 ext_regX
yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
/* I WOULD ALSO LIKE THIS:
* pat ads
gen add_l %1, %1 yields %1
#endif
-#endif TBL68020
+#endif /* TBL68020 */
/************************************************
pat lae aar $2==4 && nicesize(rom($1,3))
with D_REG yields {regX, rom($1,3), %1}
leaving ads 4 adp rom($1,3)*(0-rom($1,1))
-#else TBL68020
+#else /* TBL68020 */
pat lae aar $2==4 && rom($1,3)==2
with DD_REG
gen asl_l {small_const, 1}, %1
gen asl_l {small_const, 3}, %1
yields %1
leaving ads 4 adp (0 - rom($1,1))<<3
-#endif TBL68020
+#endif /* TBL68020 */
#endif /* ARR_OPT */
#endif /* WORD_SIZE!=2 */
pea {absolute4, 1} /* push constant 1 == ERANGE */
jsr {absolute4, ".trp"}
1: yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".rck"}
-#endif TBL68020
+#endif /* TBL68020 */
#endif /* WORD_SIZE==4 || TBL68020 */
pat rtt leaving ret 0
#else
#ifdef TBL68020
extb_l {LOCAL,$4}
-#else TBL68020
+#else /* TBL68020 */
ext_w {LOCAL,$4}
ext_l {LOCAL,$4}
-#endif TBL68020
+#endif /* TBL68020 */
#endif
pat loc loc cii $1==2 && $2==4
t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
-#else TBL68020
+#else /* TBL68020 */
/* Part (iii) */
absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
#define t_regAregXcon regAregXcon
#define t_regAcon regAcon
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE!=2
#define DLOCAL LOCAL
alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG .
-#else TBL68020
+#else /* TBL68020 */
data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
offsetted4 + OFF_off4 + OFF_indoff4 +
alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG. /* all four above together */
-#endif TBL68020
+#endif /* TBL68020 */
/* This is a common part */
#if WORD_SIZE==2
/* Not any4, since any is used in 'with' and not in 'kills' */
t_regAcon + t_regAregXcon ) .
use_index = index_off4 + index_off2 + index_off1 .
-#else TBL68020
+#else /* TBL68020 */
reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
memind4 = reg_memind4 +
use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
-#endif TBL68020
+#endif /* TBL68020 */
/* A common part */
posextern = absolute + all_indir .
#endif
test_set1 = datalt1 .
-#else TBL68020
+#else /* TBL68020 */
imm_cmp4 = any4 - immediate4 - A_REG .
imm_cmp2 = any2 - consts .
#endif
test_set1 = data1 - consts .
-#endif TBL68020
+#endif /* TBL68020 */
test_set = test_set4 + test_set2 + test_set1 .
#ifndef TBL68020
t_address = address + t_regAregXcon + t_regAcon .
-#else TBL68020
+#else /* TBL68020 */
#define t_address address
-#endif TBL68020
+#endif /* TBL68020 */
#if TBL68881
freg = FD_REG + FS_REG .
divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
#endif
-#else TBL68020
+#else /* TBL68020 */
pea address+control4 cost(2,4).
-#endif TBL68020
+#endif /* TBL68020 */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Extra pseudo instruction; it just kills a D_REG;
from t_regAcon to A_REG+areg
gen move_l %1.reg, %2
add_l {const4, %1.bd}, %2
-#endif TBL68020
+#endif /* TBL68020 */
from address - ext_addr to A_REG+areg
gen lea %1, %2
from t_regAcon to STACK
gen move_l %1.reg, {pre_dec4, sp}
add_l {const4, %1.bd}, {indirect4, sp}
-#endif TBL68020
+#endif /* TBL68020 */
from A_REG to STACK
gen pea {indirect4, %1}
#ifdef TBL68020
from regX to STACK
gen pea %1
-#endif TBL68020
+#endif /* TBL68020 */
/* This last stackingrule is never used: whenever regX is put on
* the fakestack, some em-instuctions are left that remove it
* immediately. However cgg complained about not having a
uses reusing %1, AA_REG=%1.reg
gen add_l {const4, %1.bd}, %a
yields %a
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
from regAregXcon %bd==0 && %sc==1
with data_int
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
gen mulu_i %1, {LOCAL, $1}
-#endif TBL68020
+#endif /* TBL68020 */
proc lolxxxstl example lol adi stl
with conreg_int-bconst
with exact ext_addr yields {absolute_int, %1.bd+$1}
#ifndef TBL68020
with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
#ifdef FANCY_MODES
#ifndef TBL68020
with regAcon yields {offsetted1, %1.reg, %1.bd}
with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted1, %1.reg, %1.bd}
with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#ifdef FANCY_MODES
#ifndef TBL68020
with regAcon yields {offsetted2, %1.reg, %1.bd}
with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted2, %1.reg, %1.bd}
with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==2
#ifndef TBL68020
with regAcon yields {offsetted4, %1.reg, %1.bd}
with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon yields {offsetted4, %1.reg, %1.bd}
with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==4
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
#endif
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon store_int
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
kills allexceptcon
gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==1
with A_REG any1
with regAregXcon any1
kills allexceptcon
gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon any1
kills allexceptcon
gen move %2, {offsetted1, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==2
with A_REG any2
with regAregXcon any2
kills allexceptcon
gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon any2
kills allexceptcon
gen move %2, {offsetted2, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
pat sti $1==4
with A_REG store4-sconsts4
with regAregXcon store4-sconsts4
kills allexceptcon
gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
-#else TBL68020
+#else /* TBL68020 */
with exact regAcon store4
kills allexceptcon
gen move %2, {offsetted4, %1.reg, %1.bd}
kills allexceptcon
gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat sti $1==6
#ifdef TBL68020
with data4 DD_REG4
gen muls_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".mli"}
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen divs_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat rmi $1==2
killreg %2
/* !!!! contents of %2 have changed: make this known to cg */
yields %a
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
yields dl2
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat ngi $1==2
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen mulu_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".mlu"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat dvu $1==2
#ifdef TBL68020
with data4-sconsts4 DD_REG4
gen divu_l %1, %2 yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvu"}
yields dl1
-#endif TBL68020
+#endif /* TBL68020 */
#if WORD_SIZE==2
pat rmu $1==2
killreg %2
/* !!!! contents of %2 have changed: make this known to cg */
yields %a
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".dvu"}
yields dl2
-#endif TBL68020
+#endif /* TBL68020 */
pat slu leaving sli $1
with exact absolute4 ext_regX
yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
#endif /* FANCY_MODES */
-#endif TBL68020
+#endif /* TBL68020 */
/* I WOULD ALSO LIKE THIS:
* pat ads
gen add_l %1, %1 yields %1
#endif
-#endif TBL68020
+#endif /* TBL68020 */
/************************************************
pat lae aar $2==4 && nicesize(rom($1,3))
with D_REG yields {regX, rom($1,3), %1}
leaving ads 4 adp rom($1,3)*(0-rom($1,1))
-#else TBL68020
+#else /* TBL68020 */
pat lae aar $2==4 && rom($1,3)==2
with DD_REG
gen asl_l {small_const, 1}, %1
gen asl_l {small_const, 3}, %1
yields %1
leaving ads 4 adp (0 - rom($1,1))<<3
-#endif TBL68020
+#endif /* TBL68020 */
#endif /* ARR_OPT */
#endif /* WORD_SIZE!=2 */
pea {absolute4, 1} /* push constant 1 == ERANGE */
jsr {absolute4, ".trp"}
1: yields %2
-#else TBL68020
+#else /* TBL68020 */
with STACK
kills ALL
gen jsr {absolute4, ".rck"}
-#endif TBL68020
+#endif /* TBL68020 */
#endif /* WORD_SIZE==4 || TBL68020 */
pat rtt leaving ret 0
#else
#ifdef TBL68020
extb_l {LOCAL,$4}
-#else TBL68020
+#else /* TBL68020 */
ext_w {LOCAL,$4}
ext_l {LOCAL,$4}
-#endif TBL68020
+#endif /* TBL68020 */
#endif
pat loc loc cii $1==2 && $2==4
#ifdef REGPATCH
#define SL 8
#define SSL "010"
-#else REGPATCH
+#else /* REGPATCH */
#define SL 4
#define SSL "4"
-#endif REGPATCH
+#endif /* REGPATCH */
#define NC nocoercions:
#ifndef ASLD
#ifndef RELOCATION
separate linker only possible if relocation info produced
-#endif RELOCATION
-#endif ASLD
+#endif /* RELOCATION */
+#endif /* ASLD */
#ifndef DEBUG
#define DEBUG 1
#else
#define PASS_SYMB 1
#define PASS_RELO 1
-#endif THREE_PASS
+#endif /* THREE_PASS */
#ifdef ASLD
#define RELOMOVE(a,b) /* empty */
#ifdef ASLD
#ifdef RELOCATION
extern short rflag; /* -r option (relocation info) */
-#endif RELOCATION
+#endif /* RELOCATION */
#else
#define rflag 1
extern valu_t relonami;
-#endif ASLD
+#endif /* ASLD */
#ifdef THREE_PASS
extern short bflag; /* -b option (no optimizations) */
else if (listtemp) { listflag = listtemp; listeoln = 1; }
#else
#define LISTLINE(n) /* empty */
-#endif LISTING
+#endif /* LISTING */
#ifdef ASLD
#define RELODONE /* empty */
#ifdef RELOCATION
#ifdef ASLD
rflag = 1;
-#endif ASLD
-#endif RELOCATION
+#endif /* ASLD */
+#endif /* RELOCATION */
break;
case 'b':
#ifdef THREE_PASS
#ifdef RELOCATION
if (rflag)
sflag |= SYM_SCT;
-#endif RELOCATION
+#endif /* RELOCATION */
pass_1(argc, argv);
#ifdef THREE_PASS
pass_23(PASS_2);
#endif
return(need);
}
-#endif ASLD
+#endif /* ASLD */
parse(s)
char *s;
machstart(n);
#ifndef ASLD
newmodule(modulename);
-#endif ASLD
+#endif /* ASLD */
ffreopen(temppath, tempfile);
yyparse();
commfinish();
0,
load(ip)
);
-#else not ASLD
+#else /* not ASLD */
#ifdef THREE_PASS
if (pass == PASS_2) {
cp->c_size -= sp->s_gain;
}
-#endif THREE_PASS
+#endif /* THREE_PASS */
}
if (pass == PASS_1) cp->c_size = ip->i_valu;
if (PASS_SYMB) {
cp->c_size
);
}
-#endif not ASLD
+#endif /* not ASLD */
}
if (PASS_SYMB == 0)
return;
(valu_t)0
);
}
-#endif not ASLD
+#endif /* not ASLD */
/*
* produce symbol table entries for sections
*/
typ = S_VAR;
else if (pass == PASS_2 && (ip->i_type & S_TYP) == S_UND)
ip->i_type |= typ;
-#endif THREE_PASS
+#endif /* THREE_PASS */
if (typ == S_UND)
serror("illegal equate");
if (pass == PASS_3)
register flag;
#ifdef GENLAB
static char genlab[] = GENLAB;
-#endif GENLAB
+#endif /* GENLAB */
if (pass == PASS_1) {
/* printf("declare %s: %o\n", ip->i_name, typ); */
flag = SYM_LOC;
#else
flag = SYM_EXT|SYM_LOC; /* S_EXT not stable in PASS_1 */
-#endif THREE_PASS
+#endif /* THREE_PASS */
#ifdef GENLAB
if (!(flag & SYM_EXT) &&
strncmp(ip->i_name, genlab, sizeof(genlab)-1) == 0)
flag = SYM_LAB;
-#endif GENLAB
+#endif /* GENLAB */
if (sflag & flag)
newsymb(
ip->i_name,
listcolm = 0;
listflag = listtemp;
}
-#endif LISTING
+#endif /* LISTING */
/* ---------- code optimization ---------- */
#ifdef MAXSPLIT
sret = split(tp,&tokexp[i],ply,toplevel);
if (sret==0) {
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
totalcost += stackupto(tp,ply,toplevel);
CHKCOST();
break;
#ifdef MAXSPLIT
}
i += sret;
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
} else
i += 1;
tp--;
extern c1_t c1coercs[]; /* coercions type 1 */
#ifdef MAXSPLIT
extern c2_t c2coercs[]; /* coercions type 2 */
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
extern c3_t c3coercs[]; /* coercions type 3 */
extern struct reginfo **reglist[]; /* lists of registers per property */
if (b==0
#ifdef BSS_INIT
|| (t==sp_cstx && argval==BSS_INIT)
-#endif BSS_INIT
+#endif /* BSS_INIT */
) {
switchseg(SEGBSS);
newlbss(labstr,n);
for(j=0;j<nregvar[i];j++)
inctcount(rvnumbers[i][j]);
}
-#endif REGVARS
+#endif /* REGVARS */
for (rp=machregs;rp<machregs+NREGS;rp++) {
assert(rp->r_refcount==rp->r_tcount);
rp->r_tcount=0;
}
}
-#endif REGVARS
+#endif /* REGVARS */
/* nothing after this */
return(tokens[inp->in_info[0]].t_size);
}
}
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
tref(tp,amount) register token_p tp; {
register i;
fakestack[stackheight++] = savestack[i];
return(cp->c2_nsplit);
}
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
unsigned docoerc(tp,cp,ply,toplevel,forced) token_p tp; c3_p cp; {
token_t savestack[MAXSAVE];
#define word long
#ifndef WRD_FMT
#define WRD_FMT "%ld"
-#endif WRD_FMT
+#endif /* WRD_FMT */
*lp <<= count;
}
}
-#else USE_DIVIDE
+#else /* USE_DIVIDE */
u[4] = (e1->m2 & 1) << 15;
b64_rsft(&(e1->m1));
#ifdef MAXSPLIT
sret = split(tp,&tokexp[i],ply,toplevel);
if (sret==0) {
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
totalcost += stackupto(tp,ply,toplevel);
CHKCOST();
break;
#ifdef MAXSPLIT
}
i += sret;
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
} else
i += 1;
tp--;
extern c1_t c1coercs[]; /* coercions type 1 */
#ifdef MAXSPLIT
extern c2_t c2coercs[]; /* coercions type 2 */
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
extern c3_t c3coercs[]; /* coercions type 3 */
extern struct reginfo **reglist[]; /* lists of registers per property */
if (b==0
#ifdef BSS_INIT
|| (t==sp_cstx && argval==BSS_INIT)
-#endif BSS_INIT
+#endif /* BSS_INIT */
) {
switchseg(SEGBSS);
newlbss(labstr,n);
for(j=0;j<nregvar[i];j++)
inctcount(rvnumbers[i][j]);
}
-#endif REGVARS
+#endif /* REGVARS */
for (rp=machregs+1;rp<machregs+NREGS;rp++) {
assert(rp->r_refcount==rp->r_tcount);
rp->r_tcount=0;
}
}
-#endif REGVARS
+#endif /* REGVARS */
/* nothing after this */
return(tokens[inp->in_info[0]].t_size);
}
}
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
tref(tp,amount) register token_p tp; {
register i;
rest_stack();
return(cp->c2_nsplit);
}
-#endif MAXSPLIT
+#endif /* MAXSPLIT */
unsigned docoerc(tp,cp,ply,toplevel,forced) token_p tp; register c3_p cp; {
unsigned cost;
#define word long
#ifndef WRD_FMT
#define WRD_FMT "%ld"
-#endif WRD_FMT
+#endif /* WRD_FMT */
#ifndef lint
static char rcsid[] = "$Header$";
-#endif lint
+#endif /* lint */
/*
* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
* See the copyright notice in the ACK home directory, in the file "Copyright".
fprintf(codefile,"\tsubl2\t$%ld,sp\n",nlocals);
}
-#endif not REGVARS
+#endif /* not REGVARS */
char *segname[] = {
".sect .text", /* SEGTXT */
return i - 1;
}
-#endif REGVARS
+#endif /* REGVARS */
R9 = ("r9",4) regvar,RREG.
RA = ("r10",4) regvar,RREG.
RB = ("r11",4) regvar,RREG.
-#else REGVARS
+#else /* REGVARS */
R4 = ("r4",4),REG.
R5 = ("r5",4),REG.
R6 = ("r6",4),REG.
R9 = ("r9",4),REG.
RA = ("r10",4),REG.
RB = ("r11",4),REG.
-#endif REGVARS
+#endif /* REGVARS */
QR0 = ("r0",8,R0,R1),QREG.
QR2 = ("r2",8,R2,R3),QREG.
#ifndef REGVARS
QR6 = ("r6",8,R6,R7),QREG.
QR8 = ("r8",8,R8,R9),QREG.
QRA = ("r10",8,RA,RB),QREG.
-#endif REGVARS
+#endif /* REGVARS */
QR1 = ("r1",8,R1,R2),QREG.
#ifndef REGVARS
QR3 = ("r3",8,R3,R4),QREG.
QR5 = ("r5",8,R5,R6),QREG.
QR7 = ("r7",8,R7,R8),QREG.
QR9 = ("r9",8,R9,RA),QREG.
-#endif REGVARS
+#endif /* REGVARS */
TOKENS:
regdec2 = {REGISTER reg;} 4 cost=(0,3) "-(%[reg])"
regdec4 = {REGISTER reg;} 4 cost=(0,3) "-(%[reg])"
regdec8 = {REGISTER reg;} 8 cost=(0,6) "-(%[reg])"
-#endif REGVARS
+#endif /* REGVARS */
displ1 = {REGISTER reg; STRING ind;} 4 cost=(2,6) "%[ind](%[reg])"
displ2 = {REGISTER reg; STRING ind;} 4 cost=(2,6) "%[ind](%[reg])"
displ4 = {REGISTER reg; STRING ind;} 4 cost=(2,6) "%[ind](%[reg])"
source1 = Xsource1
#ifdef REGVARS
+ reginc1 + regdec1
-#endif REGVARS
+#endif /* REGVARS */
Xsource2 = regdef2 + displ2 + displdef2 +
EXTERNAL2 + reldef2 + CONST2 + LOCAL2 + ind2
source2 = Xsource2
#ifdef REGVARS
+ reginc2 + regdec2
-#endif REGVARS
+#endif /* REGVARS */
Xsource4 = REG + regdef4 + displ4 + displdef4 + LocaLBase +
EXTERNAL4 + reldef4 + CONST + DOUBLE + LOCAL4 + ind4
source4 = Xsource4
#ifdef REGVARS
+ RREG + reginc4 + regdec4
-#endif REGVARS
+#endif /* REGVARS */
dups4 = CONST + regdef1 + displ1 + LOCAL1 +
REG + regdef2 + displ2 + LOCAL2 +
RREG + regdef4 + displ4 + LOCAL4 + DOUBLE
source8 = Xsource8
#ifdef REGVARS
+ reginc8 + regdec8
-#endif REGVARS
+#endif /* REGVARS */
source1or2 = source1 + source2 - ind2
source1or2or4 = source1or2 + source4 - (ind2 + ind4)
source2or4 = source2 + source4 - ind4
regch4 = reginc1 + regdec1 + reginc2 + regdec2 + reginc4 + regdec4
regch8 = reginc8 + regdec8
regch = regch4 + regch8
-#endif REGVARS
+#endif /* REGVARS */
displs = displ1 + displ2 + displ4 + displ8 +
regdef1 + regdef2 + regdef4 + regdef8
#ifdef REGVARS
+ regch
-#endif REGVARS
+#endif /* REGVARS */
displdefs = displdef1 + displdef2 + displdef4 + displdef8
EXTERNALS = EXTERNAL1 + EXTERNAL2 + EXTERNAL4 + EXTERNAL8
LOCALS = LOCAL1 + LOCAL2 + LOCAL4 + LOCAL8
#ifdef REGVARS
reg4 = REG + RREG + LocaLBase
reg8 = QREG
-#else REGVARS
+#else /* REGVARS */
reg4 = REG
reg8 = QREG
-#endif REGVARS
+#endif /* REGVARS */
sreg4 = REG * SCRATCH
sreg8 = QREG * SCRATCH
bigsource4 = source1or2or4 + nonexist + ind2 + ind4
#ifdef REGVARS
#define REMEXTANDLOC remove(externals) remove(LOCALS,inreg(%[num])==0)
#define REMREG(x) remove(regch,%[reg]==regvar(x))
-#else REGVARS
+#else /* REGVARS */
#define REMEXTANDLOC remove(extandloc)
-#endif REGVARS
+#endif /* REGVARS */
CODE:
ldc | | | {CONST8,$1} | |
#ifdef REGVARS
lol inreg($1)==2 | | REMREG($1) | regvar($1) | |
-#endif REGVARS
+#endif /* REGVARS */
lol $1 < 0 | | | {LOCAL4,LB,$1,4} | |
lol $1 >= 0 | | | {LOCAL4,AP,$1,4} | |
loe | | | {EXTERNAL4,$1} | |
#ifdef REGVARS
lil inreg($1)==2 | | REMREG($1) | {regdef4,regvar($1)} | |
-#endif REGVARS
+#endif /* REGVARS */
lil $1 < 0 | | | {displdef4,LB,tostring($1)} | |
lil $1 >= 0 | | | {displdef4,AP,tostring($1)} | |
lof | | | | adp $1 loi 4 |
move(%[1],regvar($1)) | | |
... | STACK |
"movl\t(sp)+,%(regvar($1)%)" | | | (3,7)
-#endif REGVARS
+#endif /* REGVARS */
stl $1 < 0 | NC bigsource4 |
remove(displaced)
remove(LOCALS,%[num] <= $1+3 && %[num]+%[size] > $1)
move(%[1],{regdef4,regvar($1)}) | | |
... | STACK |
"movl\t(sp)+,(%(regvar($1)%))" | | | (3,10)
-#endif REGVARS
+#endif /* REGVARS */
sil $1 < 0 | NC bigsource4 |
REMEXTANDLOC
move(%[1],{displdef4,LB,tostring($1)}) | | |
"addl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
adi stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"addl3\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
adi sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
"subl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
sbi stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"subl3\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
sbi sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
"mull3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
mli stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"mull3\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
mli sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
"divl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
dvi stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"divl3\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
dvi sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
"subl3\t%[a],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
rmi stl $1==4 && $2<0
| Xsource4 Xsource4 |
remove(displaced)
"mull2\t%[1],%[a]"
"subl3\t%[a],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
rmi sil $1==4 && $2<0
| Xsource4 Xsource4 |
REMEXTANDLOC
"mnegl\t%[1],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
ngi stl $1==4 && $2<0
| source4 |
remove(displaced)
REMEXTANDLOC
"mnegl\t%[1],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
ngi sil $1==4 && $2<0
| source4 |
REMEXTANDLOC
"ashl\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
sli stl $1==4 && $2<0
| source1or2or4 source4 |
remove(displaced)
REMEXTANDLOC
"ashl\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
sli sil $1==4 && $2<0
| source1or2or4 source4 |
REMEXTANDLOC
"ashl\t$$%(0-%[1.num]%),%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | | (6,10)+%[1]+%[2]
-#endif REGVARS
+#endif /* REGVARS */
sri stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"ashl\t$$%(0-%[1.num]%),%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | | (6,10)+%[1]+%[2]
-#endif REGVARS
+#endif /* REGVARS */
sri sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
remove(regvar($2))
"addf3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
adf stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
remove(regvar($2))
"addf3\t%[1],%[2],(%(regvar($2)%))"
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
adf sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
remove(externals)
"addf3\t%[1],%[2],$2"
setcc({EXTERNAL4,$2}) | | |
-#endif FLOAT4
+#endif /* FLOAT4 */
adf $1==8 | source8 source8 |
allocate(%[1],%[2],QREG)
"addd3\t%[1],%[2],%[a]"
remove(externals)
"addd3\t%[1],%[2],$2"
setcc({EXTERNAL8,$2}) | | |
-#endif FLOAT8
+#endif /* FLOAT8 */
adf !defined($1) | source4 |
remove(ALL)
move(%[1],R0)
"subf3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
sbf stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
remove(regvar($2))
"subf3\t%[1],%[2],(%(regvar($2)%))"
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
sbf sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
remove(externals)
"subf3\t%[1],%[2],$2"
setcc({EXTERNAL4,$2}) | | |
-#endif FLOAT4
+#endif /* FLOAT4 */
sbf $1==8 | source8 source8 |
allocate(%[1],%[2],QREG)
"subd3\t%[1],%[2],%[a]"
remove(externals)
"subd3\t%[1],%[2],$2"
setcc({EXTERNAL8,$2}) | | |
-#endif FLOAT8
+#endif /* FLOAT8 */
sbf !defined($1) | source1or2or4 |
remove(ALL)
move(%[1],R0)
remove(regvar($2))
"mulf3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
mlf stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
remove(regvar($2))
"mulf3\t%[1],%[2],(%(regvar($2)%))"
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
mlf sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
remove(externals)
"mulf3\t%[1],%[2],$2"
setcc({EXTERNAL4,$2}) | | |
-#endif FLOAT4
+#endif /* FLOAT4 */
mlf $1==8 | source8 source8 |
allocate(%[1],%[2],QREG)
"muld3\t%[1],%[2],%[a]"
remove(externals)
"muld3\t%[1],%[2],$2"
setcc({EXTERNAL8,$2}) | | |
-#endif FLOAT8
+#endif /* FLOAT8 */
mlf !defined($1) | source1or2or4 |
remove(ALL)
move(%[1],R0)
"divf3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
dvf stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
remove(regvar($2))
"divf3\t%[1],%[2],(%(regvar($2)%))"
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
dvf sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
remove(externals)
"divf3\t%[1],%[2],$2"
setcc({EXTERNAL4,$2}) | | |
-#endif FLOAT4
+#endif /* FLOAT4 */
dvf $1==8 | source8 source8 |
allocate(%[1],%[2],QREG)
"divd3\t%[1],%[2],%[a]"
remove(externals)
"divd3\t%[1],%[2],$2"
setcc({EXTERNAL8,$2}) | | |
-#endif FLOAT8
+#endif /* FLOAT8 */
dvf !defined($1) | source1or2or4 |
remove(ALL)
move(%[1],R0)
"mnegf\t%[1],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
ngf stl $1==4 && $2<0
| source4 |
remove(displaced)
remove(regvar($2))
"mnegf\t%[1],(%(regvar($2)%))"
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
ngf sil $1==4 && $2<0
| source4 |
REMEXTANDLOC
remove(externals)
"mnegf\t%[1],$2"
setcc({EXTERNAL4,$2}) | | |
-#endif FLOAT4
+#endif /* FLOAT4 */
ngf $1==8 | source8 |
allocate(%[1],QREG)
"mnegd\t%[1],%[a]"
remove(externals)
"mnegd\t%[1],$2"
setcc({EXTERNAL8,$2}) | | |
-#endif FLOAT8
+#endif /* FLOAT8 */
ngf !defined($1) | source1or2or4 |
remove(ALL)
move(%[1],R0)
| | remove(regvar($1))
"addl2\t$$$2,%(regvar($1)%)"
erase(regvar($1)) | | |
-#endif REGVARS
+#endif /* REGVARS */
lol adp stl $1==$3 && $1<0
| | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
"incl\t%(regvar($1)%)"
erase(regvar($1))
setcc(regvar($1)) | | |
-#endif REGVARS
+#endif /* REGVARS */
inl $1<0 | | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
"incl\t$1(fp)"
"incl\t%(regvar($1)%)"
erase(regvar($1))
setcc(regvar($1)) | %[a] | |
-#endif REGVARS
+#endif /* REGVARS */
ine | | remove(externals)
"incl\t$1"
setcc({EXTERNAL4,$1}) | | |
"decl\t%(regvar($1)%)"
erase(regvar($1))
setcc(regvar($1)) | | |
-#endif REGVARS
+#endif /* REGVARS */
del $1<0 | | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
"decl\t$1(fp)"
"decl\t%(regvar($1)%)"
erase(regvar($1))
setcc(regvar($1)) | %[a] | |
-#endif REGVARS
+#endif /* REGVARS */
dee | | remove(externals)
"decl\t$1"
setcc({EXTERNAL4,$1}) | | |
"clrl\t%(regvar($1)%)"
erase(regvar($1))
setcc(regvar($1)) | | |
-#endif REGVARS
+#endif /* REGVARS */
zrl $1<0 | | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
"clrl\t$1(fp)"
zrl zrl $1==$2+4 && $1<0
#ifdef REGVARS
&& inreg($1)<2 && inreg($2)<2
-#endif REGVARS
+#endif /* REGVARS */
| | remove(displaced)
remove(LOCALS,%[num]<=$2+7 && %[num]+%[size]>$2)
"clrq\t$2(fp)"
zrl zrl $1==$2+4 && $1>=0
#ifdef REGVARS
&& inreg($1)<2 && inreg($2)<2
-#endif REGVARS
+#endif /* REGVARS */
| | remove(displaced)
remove(LOCALS,%[num]<=$2+7 && %[num]+%[size]>$2)
"clrq\t$2(ap)"
#ifdef LOCLABS
"1:\tclrl\t-(sp)"
"sobgtr\tr0,1b"
-#else LOCLABS
+#else /* LOCLABS */
"clrl\t-(sp)"
"sobgtr\tr0,.-2"
-#endif LOCLABS
+#endif /* LOCLABS */
erase(R0) | | |
zer !defined($1) | source1or2or4 |
remove(ALL)
#ifdef LOCLABS
"1:\tclrl\t-(sp)"
"sobgtr\tr0,1b"
-#else LOCLABS
+#else /* LOCLABS */
"clrl\t-(sp)"
"sobgtr\tr0,.-2"
-#endif LOCLABS
+#endif /* LOCLABS */
erase(R0) | | |
/********************************
"cvtbl\t%[1],%(regvar($4)%)"
erase(regvar($1))
setcc(regvar($4)) | | |
-#endif REGVARS
+#endif /* REGVARS */
loc loc cii stl $1==1 && $2==4 && $4<0
| source1or2or4 |
remove(displaced)
"cvtwl\t%[1],%(regvar($4)%)"
erase(regvar($4))
setcc(regvar($4)) | | |
-#endif REGVARS
+#endif /* REGVARS */
loc loc cii stl $1==2 && $2==4 && $4<0
| source2or4 |
remove(displaced)
"cvtfl\t%[1],%(regvar($4)%)"
erase(regvar($4))
setcc(regvar($4)) | | |
-#endif REGVARS
+#endif /* REGVARS */
loc loc cfi stl $1==4 && $2==4 && $4<0
| source4 |
remove(displaced)
remove(externals)
"cvtfl\t%[1],$4"
setcc({EXTERNAL4,$4}) | | |
-#endif FLOAT4
+#endif /* FLOAT4 */
loc loc cfi $1==4 && $2==4 | source4 |
allocate(%[1],REG)
"cvtfl\t%[1],%[a]"
"cvtdl\t%[1],%(regvar($4)%)"
erase(regvar($4))
setcc(regvar($4)) | | |
-#endif REGVARS
+#endif /* REGVARS */
loc loc cfi stl $1==8 && $2==4 && $4<0
| source8 |
remove(displaced)
remove(externals)
"cvtdl\t%[1],$4"
setcc({EXTERNAL4,$4}) | | |
-#endif FLOAT8
+#endif /* FLOAT8 */
loc loc cfi $1==8 && $2==4 | source8 |
allocate(%[1],REG)
"cvtdl\t%[1],%[a]"
"cvtlf\t%[1],%(regvar($4)%)"
erase(regvar($4))
setcc(regvar($4)) | | |
-#endif REGVARS
+#endif /* REGVARS */
loc loc cif stl $1==4 && $2==4 && $4<0
| source4 |
remove(displaced)
loc loc cif ste $1==4 && $2==4 | source4 |
remove(externals)
"cvtlf\t%[1],$4" | | |
-#endif FLOAT4
+#endif /* FLOAT4 */
loc loc cif $1==4 && $2==4 | source4 |
allocate(%[1],REG)
"cvtlf\t%[1],%[a]" | %[a] | |
"cvtld\t%[1],%(regvar($4)%)"
erase(regvar($4))
setcc(regvar($4)) | | |
-#endif REGVARS
+#endif /* REGVARS */
*/
loc loc cif sdl $1==4 && $2==8 && $4<0
| source4 |
loc loc cif sde $1==4 && $2==8 | source4 |
remove(externals)
"cvtld\t%[1],$4" | | |
-#endif FLOAT8
+#endif /* FLOAT8 */
loc loc cif $1==4 && $2==8 | source4 |
allocate(%[1],QREG)
"cvtld\t%[1],%[a]" | %[a] | |
"cvtfd\t%[1],%(regvar($4)%)"
erase(regvar($4))
setcc(regvar($4)) | | |
-#endif REGVARS
+#endif /* REGVARS */
*/
loc loc cff sdl $1==4 && $2==8 && $4<0
| source4 |
loc loc cff sde $1==4 && $2==8 | source4 |
remove(externals)
"cvtfd\t%[1],$4" | | |
-#endif FLOAT8
+#endif /* FLOAT8 */
loc loc cff $1==4 && $2==8 | source4 |
allocate(%[1],QREG)
"cvtfd\t%[1],%[a]" | %[a] | |
"cvtdf\t%[1],%(regvar($4)%)"
erase(regvar($4))
setcc(regvar($4)) | | |
-#endif REGVARS
+#endif /* REGVARS */
loc loc cff stl $1==8 && $2==4 && $4<0
| source8 |
remove(displaced)
loc loc cff ste $1==8 && $2==4 | source8 |
remove(externals)
"cvtdf\t%[1],$4" | | |
-#endif FLOAT4
+#endif /* FLOAT4 */
loc loc cff $1==8 && $2==4 | source8 |
allocate(%[1],REG)
"cvtdf\t%[1],%[a]" | %[a] | |
"bicl3\t$$~%[2.num],%[1],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | | (4,4)+%[1]+%[2]
-#endif REGVARS
+#endif /* REGVARS */
and stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
"bicl3\t$$~%[2.num],%[1],(%(regvar($2)%))"
setcc({regdef4,regvar($2)})
| | | (6,12)+%[1]+%[2]
-#endif REGVARS
+#endif /* REGVARS */
and sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
"bisl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
ior stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"bisl3\t%[1],%[2],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
ior sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
"xorl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
xor stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"xorl3\t%[1],%[2],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
xor sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
"mcoml\t%[1],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
com stl $1==4 && $2<0
| source4 |
remove(displaced)
REMEXTANDLOC
"mcoml\t%[1],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
com sil $1==4 && $2<0
| source4 |
REMEXTANDLOC
"rotl\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
rol stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"rotl\t%[1],%[2],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
rol sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
"rotl\t$$%(32-%[1.num]%),%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
-#endif REGVARS
+#endif /* REGVARS */
ror stl $1==4 && $2<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"rotl\t$$%(32-%[1.num]%),%[2],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
ror sil $1==4 && $2<0
| source4 source4 |
REMEXTANDLOC
"bicl3\t%[1],%[2],%(regvar($3)%)"
erase(regvar($3))
setcc(regvar($3)) | | |
-#endif REGVARS
+#endif /* REGVARS */
com and stl $1==4 && $2==4 && $3<0
| source4 source4 |
remove(displaced)
REMEXTANDLOC
"bicl3\t%[1],%[2],(%(regvar($3)%))"
setcc({regdef4,regvar($3)}) | | |
-#endif REGVARS
+#endif /* REGVARS */
com and sil $1==4 && $2==4 && $3<0
| source4 source4 |
REMEXTANDLOC
#endif
erase(%[a])
setcc(%[a]) | %[a] | |
-#endif FLOAT4
+#endif /* FLOAT4 */
#ifdef FLOAT8
cmf tlt $1==8 | source8 source8 |
allocate(%[1],%[2],REG)
#endif
erase(%[a])
setcc(%[a]) | %[a] | |
-#endif FLOAT8
+#endif /* FLOAT8 */
/* Remember that cmu was replaced by cmp. */
cmp tlt | source4 source4 |
allocate(REG={CONST1,0})
#ifdef REGVARS
asp $1==4 | bigsource4 - regch4 | | | |
-#else REGVARS
+#else /* REGVARS */
asp $1==4 | NC bigsource4 | | | |
-#endif REGVARS
+#endif /* REGVARS */
... | STACK |
"tstl\t(sp)+" | | | (2,7)
asp $1>0 | STACK |
dup $1==4 | dups4 | | %[1] %[1] | |
#ifdef REGVARS
dup $1==8 | bigsource8-regch8 | | %[1] %[1] | |
-#else REGVARS
+#else /* REGVARS */
dup $1==8 | bigsource8 | | %[1] %[1] | |
-#endif REGVARS
+#endif /* REGVARS */
... | dups4 dups4 | | %[2] %[1] %[2] %[1] | |
dup | STACK |
allocate(REG,REG={CONST1,$1/4})
move(%[1],R0)
"jsb\t.rck"
erase(R0) | | |
-#else DORCK
+#else /* DORCK */
#ifdef REGVARS
rck defined($1) | bigsource4-regch4 | | | |
rck !defined($1) | bigsource4-regch4 bigsource4-regch4 | | | |
-#else REGVARS
+#else /* REGVARS */
rck defined($1) | bigsource4 | | | |
rck !defined($1) | bigsource4 bigsource4 | | | |
-#endif REGVARS
-#endif DORCK
+#endif /* REGVARS */
+#endif /* DORCK */
rtt | | "ret" | | |
sig | STACK |
"jsb\t.sig" | | |
setcc(%[2]) erase(%[2]),(3,4)+%[1])
(reginc8+regdec8,reg8, "movq\t%[1],%[2]"
setcc(%[2]) erase(%[2]),(3,7)+%[1])
-#endif REGVARS
+#endif /* REGVARS */
(source8,source8, "movq\t%[1],%[2]"
setcc(%[2]), (3,4)+%[1]+%[2])
(source4,source4, "movl\t%[1],%[2]"
#define printstate(s) dumpstate(s)
#else
#define printstate(s)
-#endif DEBUG
+#endif /* DEBUG */
/**** WHICH IS FASTER? ****
#define BTSCPY(pp,qq,i,p,q,n) btscpy(p,q,(n)*sizeof(struct e_instr))
public / ack.git / commitdiff