uses reusing %1, AA_REG = %1.reg
gen add_l {dreg4,%1.xreg},%a
yields %a
+
+from regAregXcon %sc==1
+ uses reusing %1, AA_REG = %1.reg
+ gen add_l {dreg4, %1.xreg}, %a
+ yields {regAcon, %a, %1.bd}
#endif
#if WORD_SIZE==2
pat lil inreg($1)==reg_pointer
kills pre_post %reg==regvar($1, reg_pointer)
yields {indirect_int, regvar($1, reg_pointer)}
+#if WORD_SIZE==4
pat lil inreg($1)==reg_any
uses AA_REG = {DLOCAL, $1}
yields {indirect_int, %a}
+#endif
pat lil
#if TBL68020
#endif /* FANCY_MODES */
#endif /* TBL68020 */
+#if WORD_SIZE==2
+pat loi $1==6
+with AA_REG
+ yields {offsetted2, %1, 4} {indirect4, %1}
+with exact local_addr
+ yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
+with exact ext_addr
+ yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
+#endif
+
pat loi $1==8
#if WORD_SIZE!=2
leaving ldf 0
yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
#endif
+#if WORD_SIZE==4
pat loi $1==3*WORD_SIZE
with AA_REG STACK
kills ALL
move_i {pre_dec_int, %1},{pre_dec_int, sp}
move_i {pre_dec_int, %1},{pre_dec_int, sp}
-/* ??? */
-#if WORD_SIZE==4
pat loi $1==4*WORD_SIZE
with AA_REG STACK
kills ALL
kills allexceptcon
gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
+#if WORD_SIZE==4
pat sil inreg($1)==reg_any
with store_int-sconsts
kills allexceptcon
kills allexceptcon
uses AA_REG = {DLOCAL, $1}
gen move_i {post_inc_int, sp}, {indirect_int, %a}
+#endif
pat sil
#if TBL68020
with exact ext_addr store_int
kills allexceptcon
gen move %2, {absolute_int, %1.bd+$1}
-#ifndef TBL68020
+#if TBL68000
+#if WORD_SIZE==4
with regAcon store_int
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
+#endif
#else TBL68020
with exact regAcon store_int
kills allexceptcon
#endif /* FANCY_MODES */
#endif TBL68020
+#if WORD_SIZE==2
+pat sti $1==6
+with A_REG any4 any2
+ kills ALL
+ gen move %2, {indirect4, %1}
+ move %3, {offsetted2, %1, 4}
+with AA_REG any4 any2
+ kills ALL
+ gen move %2, {post_inc4, %1}
+ move %3, {post_inc2, %1}
+with exact A_REG STACK
+ kills ALL
+ gen move_l {post_inc4, sp}, {indirect4, %1}
+ move_w {post_inc2, sp}, {offsetted2, %1, 4}
+with exact AA_REG STACK
+ kills ALL
+ gen move_l {post_inc4, sp}, {post_inc4, %1}
+ move_w {post_inc2, sp}, {post_inc2, %1}
+#endif
+
pat sti $1==8
#if WORD_SIZE!=2
leaving sdf 0
move_l %3,{absolute4, %1.bd+4}
#endif
+
+#if WORD_SIZE==4
pat sti $1==3*WORD_SIZE
with AA_REG STACK
kills ALL
move_i {post_inc_int, sp},{post_inc_int,%1}
move_i {post_inc_int, sp},{post_inc_int,%1}
-/* ??? */
-#if WORD_SIZE==4
pat sti $1==4*WORD_SIZE
with AA_REG STACK
kills ALL
kills ALL
gen jsr {absolute4, ".mli"}
yields dl1
-#endif TBL68020
+#endif
#if WORD_SIZE==2
pat dvi $1==2
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
- yields dl0
+ yields dl2
#endif TBL68020
#if WORD_SIZE==2
pat loc sli ads $1==3 && $2==4 && $3==4
with D_REG4 yields {regX, 8, %1}
leaving ads 4
+#else
+
+pat loc sli $1==1 && $2==WORD_SIZE
+with DD_REG
+ gen add_i %1, %1 yields %1
+
+#if WORD_SIZE==2
+pat loc sli $1==1 && $2==4
+with DD_REG4
+ gen add_l %1, %1 yields %1
+#endif
+
#endif TBL68020
with zero_const
yields {zero_const4, 0}
with any
-uses reusing %1, DD_REG4
+uses DD_REG4 = {zero_const4, 0}
gen move %1,%a.1
- ext_l %a yields %a
+ yields %a
pat loc loc ciu $1==4 && $2==2
with zero_const4
pat ret $1==0
gen return
-pat asp ret $1==0
+pat asp ret $2==0
gen return
#if WORD_SIZE==2
-pat ret $1 ==2
+pat ret $1==2
with any2
gen move %1, d0
return
bne {slabel, 1b}
2:
-/* ??? interface */
#if WORD_SIZE==2
pat csa $1==2
#if TBL68020
pat exg !defined($1)
with any_int STACK
kills ALL
- gen move_i %1, d0
+ gen move %1, d0
jsr {absolute4, ".exg"}
pat fil
kills ALL
gen jsr {absolute4, ".mon"}
+/* used by the ANSI-compiler to indicate volatile */
pat nop
with STACK
kills ALL
- gen jsr {absolute4, ".nop"} /* */
+/* gen jsr {absolute4, ".nop"} */
#if WORD_SIZE==2
#ifdef TBL68020
uses reusing %1, AA_REG = %1.reg
gen add_l {dreg4,%1.xreg},%a
yields %a
+
+from regAregXcon %sc==1
+ uses reusing %1, AA_REG = %1.reg
+ gen add_l {dreg4, %1.xreg}, %a
+ yields {regAcon, %a, %1.bd}
#endif
#if WORD_SIZE==2
pat lil inreg($1)==reg_pointer
kills pre_post %reg==regvar($1, reg_pointer)
yields {indirect_int, regvar($1, reg_pointer)}
+#if WORD_SIZE==4
pat lil inreg($1)==reg_any
uses AA_REG = {DLOCAL, $1}
yields {indirect_int, %a}
+#endif
pat lil
#if TBL68020
#endif /* FANCY_MODES */
#endif /* TBL68020 */
+#if WORD_SIZE==2
+pat loi $1==6
+with AA_REG
+ yields {offsetted2, %1, 4} {indirect4, %1}
+with exact local_addr
+ yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
+with exact ext_addr
+ yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
+#endif
+
pat loi $1==8
#if WORD_SIZE!=2
leaving ldf 0
yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
#endif
+#if WORD_SIZE==4
pat loi $1==3*WORD_SIZE
with AA_REG STACK
kills ALL
move_i {pre_dec_int, %1},{pre_dec_int, sp}
move_i {pre_dec_int, %1},{pre_dec_int, sp}
-/* ??? */
-#if WORD_SIZE==4
pat loi $1==4*WORD_SIZE
with AA_REG STACK
kills ALL
kills allexceptcon
gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
+#if WORD_SIZE==4
pat sil inreg($1)==reg_any
with store_int-sconsts
kills allexceptcon
kills allexceptcon
uses AA_REG = {DLOCAL, $1}
gen move_i {post_inc_int, sp}, {indirect_int, %a}
+#endif
pat sil
#if TBL68020
with exact ext_addr store_int
kills allexceptcon
gen move %2, {absolute_int, %1.bd+$1}
-#ifndef TBL68020
+#if TBL68000
+#if WORD_SIZE==4
with regAcon store_int
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
+#endif
#else TBL68020
with exact regAcon store_int
kills allexceptcon
#endif /* FANCY_MODES */
#endif TBL68020
+#if WORD_SIZE==2
+pat sti $1==6
+with A_REG any4 any2
+ kills ALL
+ gen move %2, {indirect4, %1}
+ move %3, {offsetted2, %1, 4}
+with AA_REG any4 any2
+ kills ALL
+ gen move %2, {post_inc4, %1}
+ move %3, {post_inc2, %1}
+with exact A_REG STACK
+ kills ALL
+ gen move_l {post_inc4, sp}, {indirect4, %1}
+ move_w {post_inc2, sp}, {offsetted2, %1, 4}
+with exact AA_REG STACK
+ kills ALL
+ gen move_l {post_inc4, sp}, {post_inc4, %1}
+ move_w {post_inc2, sp}, {post_inc2, %1}
+#endif
+
pat sti $1==8
#if WORD_SIZE!=2
leaving sdf 0
move_l %3,{absolute4, %1.bd+4}
#endif
+
+#if WORD_SIZE==4
pat sti $1==3*WORD_SIZE
with AA_REG STACK
kills ALL
move_i {post_inc_int, sp},{post_inc_int,%1}
move_i {post_inc_int, sp},{post_inc_int,%1}
-/* ??? */
-#if WORD_SIZE==4
pat sti $1==4*WORD_SIZE
with AA_REG STACK
kills ALL
kills ALL
gen jsr {absolute4, ".mli"}
yields dl1
-#endif TBL68020
+#endif
#if WORD_SIZE==2
pat dvi $1==2
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
- yields dl0
+ yields dl2
#endif TBL68020
#if WORD_SIZE==2
pat loc sli ads $1==3 && $2==4 && $3==4
with D_REG4 yields {regX, 8, %1}
leaving ads 4
+#else
+
+pat loc sli $1==1 && $2==WORD_SIZE
+with DD_REG
+ gen add_i %1, %1 yields %1
+
+#if WORD_SIZE==2
+pat loc sli $1==1 && $2==4
+with DD_REG4
+ gen add_l %1, %1 yields %1
+#endif
+
#endif TBL68020
with zero_const
yields {zero_const4, 0}
with any
-uses reusing %1, DD_REG4
+uses DD_REG4 = {zero_const4, 0}
gen move %1,%a.1
- ext_l %a yields %a
+ yields %a
pat loc loc ciu $1==4 && $2==2
with zero_const4
pat ret $1==0
gen return
-pat asp ret $1==0
+pat asp ret $2==0
gen return
#if WORD_SIZE==2
-pat ret $1 ==2
+pat ret $1==2
with any2
gen move %1, d0
return
bne {slabel, 1b}
2:
-/* ??? interface */
#if WORD_SIZE==2
pat csa $1==2
#if TBL68020
pat exg !defined($1)
with any_int STACK
kills ALL
- gen move_i %1, d0
+ gen move %1, d0
jsr {absolute4, ".exg"}
pat fil
kills ALL
gen jsr {absolute4, ".mon"}
+/* used by the ANSI-compiler to indicate volatile */
pat nop
with STACK
kills ALL
- gen jsr {absolute4, ".nop"} /* */
+/* gen jsr {absolute4, ".nop"} */
#if WORD_SIZE==2
#ifdef TBL68020
uses reusing %1, AA_REG = %1.reg
gen add_l {dreg4,%1.xreg},%a
yields %a
+
+from regAregXcon %sc==1
+ uses reusing %1, AA_REG = %1.reg
+ gen add_l {dreg4, %1.xreg}, %a
+ yields {regAcon, %a, %1.bd}
#endif
#if WORD_SIZE==2
pat lil inreg($1)==reg_pointer
kills pre_post %reg==regvar($1, reg_pointer)
yields {indirect_int, regvar($1, reg_pointer)}
+#if WORD_SIZE==4
pat lil inreg($1)==reg_any
uses AA_REG = {DLOCAL, $1}
yields {indirect_int, %a}
+#endif
pat lil
#if TBL68020
#endif /* FANCY_MODES */
#endif /* TBL68020 */
+#if WORD_SIZE==2
+pat loi $1==6
+with AA_REG
+ yields {offsetted2, %1, 4} {indirect4, %1}
+with exact local_addr
+ yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
+with exact ext_addr
+ yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
+#endif
+
pat loi $1==8
#if WORD_SIZE!=2
leaving ldf 0
yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
#endif
+#if WORD_SIZE==4
pat loi $1==3*WORD_SIZE
with AA_REG STACK
kills ALL
move_i {pre_dec_int, %1},{pre_dec_int, sp}
move_i {pre_dec_int, %1},{pre_dec_int, sp}
-/* ??? */
-#if WORD_SIZE==4
pat loi $1==4*WORD_SIZE
with AA_REG STACK
kills ALL
kills allexceptcon
gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
+#if WORD_SIZE==4
pat sil inreg($1)==reg_any
with store_int-sconsts
kills allexceptcon
kills allexceptcon
uses AA_REG = {DLOCAL, $1}
gen move_i {post_inc_int, sp}, {indirect_int, %a}
+#endif
pat sil
#if TBL68020
with exact ext_addr store_int
kills allexceptcon
gen move %2, {absolute_int, %1.bd+$1}
-#ifndef TBL68020
+#if TBL68000
+#if WORD_SIZE==4
with regAcon store_int
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
+#endif
#else TBL68020
with exact regAcon store_int
kills allexceptcon
#endif /* FANCY_MODES */
#endif TBL68020
+#if WORD_SIZE==2
+pat sti $1==6
+with A_REG any4 any2
+ kills ALL
+ gen move %2, {indirect4, %1}
+ move %3, {offsetted2, %1, 4}
+with AA_REG any4 any2
+ kills ALL
+ gen move %2, {post_inc4, %1}
+ move %3, {post_inc2, %1}
+with exact A_REG STACK
+ kills ALL
+ gen move_l {post_inc4, sp}, {indirect4, %1}
+ move_w {post_inc2, sp}, {offsetted2, %1, 4}
+with exact AA_REG STACK
+ kills ALL
+ gen move_l {post_inc4, sp}, {post_inc4, %1}
+ move_w {post_inc2, sp}, {post_inc2, %1}
+#endif
+
pat sti $1==8
#if WORD_SIZE!=2
leaving sdf 0
move_l %3,{absolute4, %1.bd+4}
#endif
+
+#if WORD_SIZE==4
pat sti $1==3*WORD_SIZE
with AA_REG STACK
kills ALL
move_i {post_inc_int, sp},{post_inc_int,%1}
move_i {post_inc_int, sp},{post_inc_int,%1}
-/* ??? */
-#if WORD_SIZE==4
pat sti $1==4*WORD_SIZE
with AA_REG STACK
kills ALL
kills ALL
gen jsr {absolute4, ".mli"}
yields dl1
-#endif TBL68020
+#endif
#if WORD_SIZE==2
pat dvi $1==2
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
- yields dl0
+ yields dl2
#endif TBL68020
#if WORD_SIZE==2
pat loc sli ads $1==3 && $2==4 && $3==4
with D_REG4 yields {regX, 8, %1}
leaving ads 4
+#else
+
+pat loc sli $1==1 && $2==WORD_SIZE
+with DD_REG
+ gen add_i %1, %1 yields %1
+
+#if WORD_SIZE==2
+pat loc sli $1==1 && $2==4
+with DD_REG4
+ gen add_l %1, %1 yields %1
+#endif
+
#endif TBL68020
with zero_const
yields {zero_const4, 0}
with any
-uses reusing %1, DD_REG4
+uses DD_REG4 = {zero_const4, 0}
gen move %1,%a.1
- ext_l %a yields %a
+ yields %a
pat loc loc ciu $1==4 && $2==2
with zero_const4
pat ret $1==0
gen return
-pat asp ret $1==0
+pat asp ret $2==0
gen return
#if WORD_SIZE==2
-pat ret $1 ==2
+pat ret $1==2
with any2
gen move %1, d0
return
bne {slabel, 1b}
2:
-/* ??? interface */
#if WORD_SIZE==2
pat csa $1==2
#if TBL68020
pat exg !defined($1)
with any_int STACK
kills ALL
- gen move_i %1, d0
+ gen move %1, d0
jsr {absolute4, ".exg"}
pat fil
kills ALL
gen jsr {absolute4, ".mon"}
+/* used by the ANSI-compiler to indicate volatile */
pat nop
with STACK
kills ALL
- gen jsr {absolute4, ".nop"} /* */
+/* gen jsr {absolute4, ".nop"} */
#if WORD_SIZE==2
#ifdef TBL68020
uses reusing %1, AA_REG = %1.reg
gen add_l {dreg4,%1.xreg},%a
yields %a
+
+from regAregXcon %sc==1
+ uses reusing %1, AA_REG = %1.reg
+ gen add_l {dreg4, %1.xreg}, %a
+ yields {regAcon, %a, %1.bd}
#endif
#if WORD_SIZE==2
pat lil inreg($1)==reg_pointer
kills pre_post %reg==regvar($1, reg_pointer)
yields {indirect_int, regvar($1, reg_pointer)}
+#if WORD_SIZE==4
pat lil inreg($1)==reg_any
uses AA_REG = {DLOCAL, $1}
yields {indirect_int, %a}
+#endif
pat lil
#if TBL68020
#endif /* FANCY_MODES */
#endif /* TBL68020 */
+#if WORD_SIZE==2
+pat loi $1==6
+with AA_REG
+ yields {offsetted2, %1, 4} {indirect4, %1}
+with exact local_addr
+ yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
+with exact ext_addr
+ yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
+#endif
+
pat loi $1==8
#if WORD_SIZE!=2
leaving ldf 0
yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
#endif
+#if WORD_SIZE==4
pat loi $1==3*WORD_SIZE
with AA_REG STACK
kills ALL
move_i {pre_dec_int, %1},{pre_dec_int, sp}
move_i {pre_dec_int, %1},{pre_dec_int, sp}
-/* ??? */
-#if WORD_SIZE==4
pat loi $1==4*WORD_SIZE
with AA_REG STACK
kills ALL
kills allexceptcon
gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
+#if WORD_SIZE==4
pat sil inreg($1)==reg_any
with store_int-sconsts
kills allexceptcon
kills allexceptcon
uses AA_REG = {DLOCAL, $1}
gen move_i {post_inc_int, sp}, {indirect_int, %a}
+#endif
pat sil
#if TBL68020
with exact ext_addr store_int
kills allexceptcon
gen move %2, {absolute_int, %1.bd+$1}
-#ifndef TBL68020
+#if TBL68000
+#if WORD_SIZE==4
with regAcon store_int
kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
+#endif
#else TBL68020
with exact regAcon store_int
kills allexceptcon
#endif /* FANCY_MODES */
#endif TBL68020
+#if WORD_SIZE==2
+pat sti $1==6
+with A_REG any4 any2
+ kills ALL
+ gen move %2, {indirect4, %1}
+ move %3, {offsetted2, %1, 4}
+with AA_REG any4 any2
+ kills ALL
+ gen move %2, {post_inc4, %1}
+ move %3, {post_inc2, %1}
+with exact A_REG STACK
+ kills ALL
+ gen move_l {post_inc4, sp}, {indirect4, %1}
+ move_w {post_inc2, sp}, {offsetted2, %1, 4}
+with exact AA_REG STACK
+ kills ALL
+ gen move_l {post_inc4, sp}, {post_inc4, %1}
+ move_w {post_inc2, sp}, {post_inc2, %1}
+#endif
+
pat sti $1==8
#if WORD_SIZE!=2
leaving sdf 0
move_l %3,{absolute4, %1.bd+4}
#endif
+
+#if WORD_SIZE==4
pat sti $1==3*WORD_SIZE
with AA_REG STACK
kills ALL
move_i {post_inc_int, sp},{post_inc_int,%1}
move_i {post_inc_int, sp},{post_inc_int,%1}
-/* ??? */
-#if WORD_SIZE==4
pat sti $1==4*WORD_SIZE
with AA_REG STACK
kills ALL
kills ALL
gen jsr {absolute4, ".mli"}
yields dl1
-#endif TBL68020
+#endif
#if WORD_SIZE==2
pat dvi $1==2
with STACK
kills ALL
gen jsr {absolute4, ".dvi"}
- yields dl0
+ yields dl2
#endif TBL68020
#if WORD_SIZE==2
pat loc sli ads $1==3 && $2==4 && $3==4
with D_REG4 yields {regX, 8, %1}
leaving ads 4
+#else
+
+pat loc sli $1==1 && $2==WORD_SIZE
+with DD_REG
+ gen add_i %1, %1 yields %1
+
+#if WORD_SIZE==2
+pat loc sli $1==1 && $2==4
+with DD_REG4
+ gen add_l %1, %1 yields %1
+#endif
+
#endif TBL68020
with zero_const
yields {zero_const4, 0}
with any
-uses reusing %1, DD_REG4
+uses DD_REG4 = {zero_const4, 0}
gen move %1,%a.1
- ext_l %a yields %a
+ yields %a
pat loc loc ciu $1==4 && $2==2
with zero_const4
pat ret $1==0
gen return
-pat asp ret $1==0
+pat asp ret $2==0
gen return
#if WORD_SIZE==2
-pat ret $1 ==2
+pat ret $1==2
with any2
gen move %1, d0
return
bne {slabel, 1b}
2:
-/* ??? interface */
#if WORD_SIZE==2
pat csa $1==2
#if TBL68020
pat exg !defined($1)
with any_int STACK
kills ALL
- gen move_i %1, d0
+ gen move %1, d0
jsr {absolute4, ".exg"}
pat fil
kills ALL
gen jsr {absolute4, ".mon"}
+/* used by the ANSI-compiler to indicate volatile */
pat nop
with STACK
kills ALL
- gen jsr {absolute4, ".nop"} /* */
+/* gen jsr {absolute4, ".nop"} */
#if WORD_SIZE==2
#ifdef TBL68020